DE19744678A1 - Power switching thyristor with insulated gate - Google Patents

Abstract

The thyristor includes base zones (4,6) formed in selected sections of base layers (3) surface, under which is formed a trough zone (5). The second base zone (6) contains a first conductivity source zone (7), while another section contains a first conductivity emitter zone (8). A gate electrode layer is deposited on an insulating film (9) over the first base zone (4), an exposed section of the base layer, and a surface of the second base zone. A main electrode (11) contacts free sections of first base and source zones. A second conductivity emitter layer (1) is deposited o second main face of the base layer and is contacted by a second main electrode (12). A gate electrode (13) contacts the gate electrode layer.

Description

The present invention relates generally to an insulated gate and thyristor more specifically to an insulated gate thyristor used as a power switching device.

Because of their low forward voltage, thyristors are indispensable components for Switching large powers have been used. For example, GTO thyristors are currently used (gate-switchable thyristors) for applications in the area of high voltages and large Currents used. However, GTO thyristors also have disadvantages, namely on the one hand they require a large gate current to switch off, tantamount to a low one Shutdown gain, and on the other hand, are great for safely switching off the GTO thyristors Overvoltage protection circuits, so-called snubber circuits, are required. Since GTO Thyristors show no current saturation in their current-voltage characteristic, must be a passive one Element, such as a fuse, as protection against load short circuits with a GTO thyristor get connected. This results in a reduction in the size and cost of the whole System contrary.

A MOS controlled thyristor (known as "MCT" and hereinafter referred to as) as one voltage controlled thyristor is in the IEEE IEDM Tech. Dig. 1984, page 282 have been described. Since then, the properties of this type of thyristor have varied Institutes worldwide have been analyzed and improved. The reason is that an MCT is because of it it is a voltage-controlled component, a much simpler one Gate circuit requires as a GTO thyristor, but at the same time the property of a relative has low forward voltage. Like a GTO thyristor, the MCT doesn't show any Current saturation and therefore requires a passive element in its practical use, for example a fuse.

From US 4,847,671 a so-called EST (emitter switched thyristor) is known which has a current saturation characteristic. From the publication IEEE Electron Device Letters, Volume 12 (1991), page 387 it can be seen that it has been found from measurements that such an emitter-switched thyristor with double channel (EST-1) shows a current saturation characteristic even in a high voltage range. In the publications IEEE ISPSD '93, page 71 and IEEE ISPSD '94, page 195, the results of analyzes regarding the FBSO area (FBSO area = Forward Bias Safe Operation area) and the RBSO area ( RBSO area (Reverse Bias Safe Operation area) reveals this EST, which paved the way for the development of a voltage-controlled thyristor with a safe operating range within which the component works safely when a load short circuit occurs. Fig. 25 shows the structure of this EST device.

In the component shown in FIG. 25, a first p base zone 4 , a p⁺ well zone 5 and a second p base zone 6 are formed in a surface layer of an n base layer 3 . The base layer 3 is deposited on a p emitter layer 1 with the interposition of an n⁺ buffer layer 2 . The tub zone 5 forms part of the first base zone 4 and has a relatively large diffusion depth. An n source zone 7 is formed in a surface layer of the first base zone 4 , and an n emitter zone 8 is formed in a surface layer of the second base zone 6 . A gate electrode 10 is interposed with a gate oxide film 9 over a portion of the first base zone 4 that is between the source zone 7 and an exposed portion of the base layer 3 and a portion of the second base zone 6 that is between the emitter zone 8 and an exposed portion of the Base layer 3 lies. The length of each of the source zone 7 , the emitter zone 8 and the gate electrode 10 is limited in the Z direction in the arrangement shown in FIG. 25, and the first base zone 4 and the second base zone 6 are outside these zones 7 , 8 and the electrode 10 coupled. Furthermore, the tub zone 5 is formed with an L-shape outside the coupling section of the first base zone 4 with the second base zone 6 . A cathode electrode 11 is formed in contact with a surface of the well zone 5 and a surface of the source zone 7 . On the other hand, an anode electrode 12 is formed over the entire area of the back of the emitter layer 1 .

When the cathode electrode 11 of this device is grounded and a positive voltage is applied to the gate electrode 10 while a positive voltage is applied to the anode electrode 12 , an inversion layer (partial accumulation layer) is formed under the gate oxide film 9 , and a lateral MOSFET is thereby formed switched on. As a result, electrons are supplied from the cathode electrode 11 via the source zone 7 and the inversion layer (channel) formed in the surface layer of the first base zone 4 to the base layer 3 . These electrons act as the base current of a pnp transistor, which is composed of the p emitter layer 1 , the n⁺ buffer layer 2 and the n base layer 3 and the first and second p base zones 4 , 6 and the p⁺ well zone 5 . This pnp transistor works with this base current. As a result, holes are injected from the emitter layer 1 and flow into the first base zone 4 via the buffer layer 2 and the base layer 3 . Some of these holes flow into the second base zone 6 and then under the emitter zone 8 in the Z direction to the cathode electrode 11 . The component thus operates in an IGBT mode (IGBT = Insulated Gate Bipolar Transistor or bipolar transistor with an insulated gate). As the current increases further, the pn junction between the emitter zone 8 and the second base zone 6 is biased in the forward direction, and a thyristor section comprising the p emitter layer 1 , the n⁺ buffer layer 2 , the n base layer 3 , the second p base zone 6 and the n Emitter zone 8 is in the so-called latch-up state. In this case, the device operates in a thyristor mode. To switch off the EST, the MOSFET is put into the blocking state by lowering the potential of the gate electrode 10 below the threshold value of the lateral MOSFET. As a result, the emitter zone 8 is electrically isolated from the cathode electrode 11 and the device stops working in the thyristor mode.

FIGS. 26 and 27 show cross-sectional views improved ESTs, such as those disclosed in U.S. Patents 5,317,171 and 5,319,222. In particular, the improved EST of FIG. 27 differs from that of FIG. 25 and is designed to achieve an improved forward voltage characteristic.

Fig. 28 shows a cross-sectional view of an FET controlled thyristor as disclosed in US 4,502,070. This thyristor is characterized in that the electrode 11 does not contact the second base zone 6 .

As can be seen from the foregoing, the EST shown in Fig. 25 uses the hole current in the second base zone 6 in the Z direction to forward bias the pn junction between the second base zone 6 and the emitter zone 8 , hence the degree of bias in the forward direction in the Z direction to the contact surface of the second base zone 6 with the cathode electrode 11 decreases. That is, the amount of electrons injected from the emitter zone 8 is not uniform over the length of the pn junction in the Z direction. When this EST is switched from the leading state to the blocking state, a weakly biased section of the pn junction near the contact zone with the cathode electrode 11 initially becomes the blocking state, while a deeper biased section of the pn junction further away from the contact zone with the cathode electrode 11 assumes this blocking state only slowly. This results in a tendency towards a local current concentration during shutdown combined with a reduced breakdown strength of the EST during shutdown.

Although the EST shown in FIG. 26 works similarly to that in FIG. 25, the EST of FIG. 26 can be switched off more quickly because the cathode electrode 11 extends in the Y direction and is in direct contact with the surface of the second base zone 6 . Furthermore, the EST of Fig. 26 shows a uniform turn-on characteristic due to the lack of a hole current in the Z direction. However, in the operation of this thyristor, minority carriers are not uniformly injected in the horizontal direction (Y direction) when the pn junction between the emitter zone 8 and the second base zone 6 is turned on, and therefore the forward voltage cannot be lowered as expected. If, for example, to solve this problem, the impurity concentration of the second base zone 6 is reduced to increase its resistance, a depletion layer breaks through the emitter zone 8 when the voltage is applied in the forward direction. This conventional EST therefore does not achieve a satisfactorily high breakdown or withstand voltage.

In the component shown in FIG. 27, the emitter zone 8 extends beyond the second base zone 6 so that the forward voltage is further reduced. However, this structure poses problems regarding forward withstand voltage.

In the component shown in FIG. 28, the emitter zone 8 and the second base zone 6 are completely separated from the cathode electrode 11 , which prevents the non-uniform operation of the thyristor. However, this structure has the following disadvantages. On the one hand, the breakdown voltage of the component is reduced because the hole current flows through the component in such a way that it concentrates on the side of the first base zone 4 . On the other hand, the conductance when operating the thyristor in the IGBT mode is reduced as a result of the contact FET effect.

In addition, both the EST and the FET controlled thyristor suffer from the fact that the maximum Current (limit current) that can flow through the component is large and the components are one have low breakdown strength in the event of load short circuits.

It is therefore an object of the present invention to provide an insulated gate thyristor create, in which the pn junction evenly blocking the turn-off of the thyristor assumes an increased switch-off resistance and a high one Breakthrough resistance in the event of a load short circuit, while at the same time being sufficiently low Forward voltage is guaranteed.

This object is achieved with a thyristor with an insulated gate, as in claims 1, 2 and 3 is claimed. Advantageous developments of the invention are the subject of the subclaims.

When a voltage at a thyristor with a structure according to claim 1 or 4 the insulated gate electrode is applied so that an inversion layer just below the Gate electrode occurs, the potential of the emitter zone of the first conductivity type over a Channel of the MOSFET equal to that of the first main electrode, whereby a thyristor is switched on that of the emitter zone of the first conduction type, the second base zone of the second Conduction type, the base layer of the first conductivity type and the emitter layer of the second Line type is formed. Because the surfaces of the second base zone of the second conductivity type and the emitter zone of the first conductivity type are covered with the insulating film and when the shuttering is used th of the thyristor electrons uniform from the entire emitter zone of the first line Typs are injected, the device quickly switches to a thyristor mode, and the Forward voltage is reduced. Switching on this component does not require any Hole current in the Z direction through the second base zone of the second conduction type, as in the conventional EST is the case. The base layer also contains the first conductivity type a locally constricted between the first and the second base zone of the second conduction type Section. Because the width of the base layer of the first conductivity type in this way is reduced locally, the effective channel length can be shortened, the contact FET effect can can be reduced and the forward voltage can be reduced. When shutting down others on the one hand, the pn junction can assume its blocking capability uniformly without a current concentration occurs, with the result of increased breakthrough strength.

In the embodiment according to claim 2 or claim 5, the conductivity of the inverter sion layer that occurs on the surface of the second base zone of the second conductivity type, and that of the accumulation layer that is on the surface of the base layer of the first Conductivity type occurs when a voltage is applied to the gate electrode, improved.

In a thyristor with a structure according to claim 3 or 6, the length of the Inversion layer, which on the surface of the second base zone of the second conduction type at  Applying a voltage to the gate electrode decreases, which is why a series resistance is reduced with the result of a lower forward voltage.

The second base zone of the second conduction type is preferably essentially strip-shaped or designed according to claim 7. In such a case, the semiconductor substrate can increased efficiency can be used, and by the device or the thyristor flowing current can be evenly distributed, which improves thermal equilibrium ensures importance.

In the development according to claim 8 or 9, that of the emitter zone of the first Current type flowing over the channel zone to the source zone of the first conductivity type far distributed, thereby avoiding a current concentration or localization.

With the development of claim 10, the same effect can be achieved as if the base layer of the first conduction type has a locally narrowed section between the first and the second base zone of the second conductivity type.

In the development according to claim 11, an accumulation layer in the under Gate electrode lying surface layer of the semiconductor layer of the first conductivity type formed, which leads to a reduction in the forward voltage.

In the development according to claim 12, the semiconductor substrate with better Efficiency can be used, and the current flowing through the device or the thyristor can be distributed evenly, which ensures an improved thermal balance.

In the development according to claim 13, the injection of electrons in one Thyristor section amplified and the current amplification factor of the transistor increases, resulting in leads to a reduced forward voltage.

In the development according to claim 14, the first and the second tub zone of the second line type are trained simultaneously and do not need to be separately to be made.

In the case of the further development of claim 15, the charge carrier life can be optimal can be controlled so that there are no lifetime killers in unnecessary sections prevent an increase in forward voltage or other adverse influences.

Embodiments of the invention are described in detail below with reference to FIG Described drawings. Show it:

Fig. 1 is a plan view of the surface of a silicon substrate of an insulated gate thyristor according to a first embodiment of the invention,

Fig. 2 (a) is a sectional view taken along line AA in Fig. 1,

Fig. 2 (b) is a sectional view taken along line BB in Fig. 1,

Fig. 3 Current-voltage characteristics of the thyristor of the first embodiment,

Fig. 4 is a plan view of a basic pattern with a hexagonal arrangement,

Fig. 5 is a plan view of a basic pattern with a strip-shaped arrangement,

Fig. 6 is a sectional view taken along line CC in Fig. 4,

Fig. 7 in a graphical representation of the dependence of the forward voltage of Lgmin in the thyristor of the first embodiment,

Fig. 8 in a graphical representation compromise characteristics between the on-voltage and the turn-off of components of the 1200 V class according to the first exporting approximately example and comparative examples,

Fig. 9 is a plan view of the surface of a silicon substrate of an insulated gate thyristor according to a third embodiment,

Fig. 10 in a graphic representation the dependency of the forward voltage of the thyristors Lgmin at the third and a fourth embodiment,

Fig. 11 in a graphical representation compromise characteristics between the on-voltage and turn-off time of the third with the thyristors and of the fourth embodiment of the invention,

Fig. 12 (a) and 12 (b) are sectional views corresponding to those of Fig. 2 (a) and 2 (b), the portions of the thyristor of the fourth embodiment show

Fig. 13 in a graphic representation the dependency of the forward voltage of Lgmin in an insulated gate thyristor according to a fifth embodiment,

Fig. 14 in a graphic representation the dependency of the forward voltage of Lgmin in an insulated gate thyristor of an eighth embodiment,

Fig. 15 is a plan view of the surface of a silicon substrate of an insulated gate thyristor according to a sixth embodiment,

Fig. 16 is a graph showing the RBSO range of components of the 600 V class according to a sixth embodiment and comparative examples

Fig. 17 shows a circuit arrangement for measuring the RBSO region,

Fig. 18 is a graph showing the RBSO range of components of the 2500 V class according to a seventh embodiment and comparative examples

Fig. 19 is a cross sectional view of part of an insulated gate thyristor according to a ninth embodiment,

Fig. 20 in a graphical representation compromise characteristics between the on-voltage and the turn-off of components of the 600 V class according to a ninth and an eleventh embodiment of the invention and comparative examples

Fig. 21 is a cross sectional view of part of an insulated gate thyristor according to a tenth embodiment,

Fig. 22 in a graphical representation compromise characteristics between the on-voltage and the turn-off of components of the 2500 V class according to the tenth example as well as from the guide Comparative Examples

Fig. 23 is a cross sectional view of part of an insulated gate thyristor according to an eleventh embodiment,

Fig. 24 is a cross sectional view of part of an insulated gate thyristor according to a twelfth embodiment,

Fig. 25 is a perspective view showing a cut-out unit cell of an EST,

Fig. 26 is a cross-sectional view showing an improved EST,

Fig. 27 is a cross sectional view showing a further improved EST, and

Fig. 28 is a sectional view showing an FET-driven thyristor.

During the development of the EST for the production of prototypes of different thyristors with insulated gate with the intention of solving the problems described above, the inventors have found that there is no need to connect the first main electrode to the second To contact the base zone of the second line type. Even if the surface of this second Base zone is covered with an insulating film, the resulting device in the thyristor Be drive mode can be switched to a good compromise between the forward voltage and the switch-off time leads. The inventors also performed analyzes on the level of Components considered patterns as well as impurity concentrations.

As a result of the analyzes, it was found that the withstand voltage property and the through let voltage by changing the diffusion depths and impurity concentrations of the first and  the second base zone of the second conduction type can be improved. It also became found that each of the following measures had a good effect or a good one Influence on the component sets: change the shape of the second base zone of the second Conductivity type, varying the thickness of the gate insulating film on the second base region of the second Conduction type and the base layer of the first conduction type and varying the thickness of one exposed portion of the second base zone of the second conduction type between the base layer of the first conduction type and the emitter zone of the first conduction type.

The first and second base zones of the second conduction type can be in the form of parallel mutually extending strips are formed, but they can also be a polygonal, have a circular or elliptical shape. If the first base zone of the second line is arranged in such a way that it surrounds the second base zone of the second conduction type the current concentration can be reduced or avoided, leading to improved compromise characteristics of the component leads. A plurality of the first base zones of the second conduction type can advantageously be formed around the second base zone of the second conduction type will. It is also advantageous to increase the diffusion thickness of the emitter zone of the first conduction type vary and provide lifetime killers in local areas of the thyristor.

Some embodiments of the present invention will now be described with reference to the drawings, in which the same reference numerals as in Fig. 25 are used to designate structurally and / or functionally corresponding elements. In the following description, "n" or "p" in connection with a zone or layer indicate that the respective zone or layer has electrons or holes as majority charge carriers. While in the following exemplary embodiments the first line type is the n type and the second line type is the p type, these two line types can just as well be interchanged.

First embodiment

Fig. 1 is a plan view showing respective diffusion zones formed in the surface of a silicon substrate of an insulated gate thyristor of a first embodiment of the present invention, and insulating films and electrodes are not shown. In Fig. 1, a pattern is formed in which a generally hexagonal second p base zone 6 with protrusions 6 'is formed in a surface layer of an n base layer 3 and six hexagonal first p base zones 4 are arranged to surround the second base zone 6 . Fig. 1 shows only the basic pattern, which is repeated several times in the thyristor of this embodiment. A generally annular n source zone 7 with a hexagonal outline is formed within each of the first base zones 4 , and a generally hexagonal n emitter zone 8 with projections 8 ′ is formed within the second base zone 6 . The area defined by a dotted line within the source region 7 illustrates a contact zone of a cathode electrode 11. The second base region 6 and the emitter zone 8 are, more specifically, provided there with projections, where the second base region 6 and the surrounding first base regions 4 each to come close. A gate electrode (not shown in FIG. 1) is provided on a zone which lies essentially between the source zones 7 and the emitter zone 8 .

FIG. 2 (a) is a cross-sectional view along line AA of the top view of FIG. 1, that is, along one of the protrusions of the second base zone 6 , and FIG. 2 (b) is a cross-sectional view along line BB in FIGS. 1 and shows a part of the thyristor that has no protrusion of the second base zone 6 . The thyristor shown in these figures has a semiconductor substrate section, the structure of which is similar to that of the EST of FIG. 25. More specifically, the first base zone 4 and the second base zone 6 are formed in a surface layer of one of the opposite surfaces of the n base layer 3 with a high specific resistance such that these base zones 4 and 6 are spaced apart. A p⁺ well zone 5 with a greater diffusion depth than the first base zone 4 is formed in a part of the first base zone 4 in order to avoid locking (latch-up) of a parasitic thyristor. A p emitter layer 1 is formed on an n⁺ buffer layer 2 under the other surface of the base layer 3 . The source zone 7 is formed in a selected section of a surface layer of the first base zone 4 , and the emitter zone 8 is formed in a selected section of a surface layer of the second base zone 6 . As with the thyristor of FIG. 25, a gate electrode layer 10 is formed on a gate oxide film 9 over the surfaces of the first base zone 4 , an exposed portion of the base layer 3 and the second base zone 6 , which are between the source zone 7 and the emitter zone 8 , so that a lateral n-channel MOSFET comprising the source zone 7 , the first base zone 4 and the base layer 3 is formed. The surface of the MOSFET on the side of the gate electrode layer 10 is covered with an insulating film 14 made of phosphorus silicate glass (PSG), and a contact hole or an opening is formed in the insulating film 14 so that a cathode 11 with the surfaces of both the first base region 4 and the source zone 7 is in contact. The surface of the emitter zone 8 is covered with an insulating film 19 . An anode electrode 12 is formed in contact with the surface of the emitter layer 1 . Although a gate electrode 13 in the sectional view of Fig. 2 (b) in contact with the gate electrode layer 10 is formed, are these electrode 13 and the gate electrode layer 10 in this cross-section does not necessarily contact each other. In many cases, the cathode electrode 11 extends over the gate electrode layer 10 with the interposition of the insulating film 14 , as can be seen in the cross-sectional view of FIG. 2 (a).

An insulating film 19 lies on a part of the substrate corresponding to the emitter zone 8 and the second base zone 6 in FIG. 1, and the cathode electrode 11 is in contact with a section surrounded by the first base zone 4 corresponding to the source zone 7 and the well zone 5 . The base layer 3 is exposed between the corresponding first base zone 4 and second base zone 6 and between adjacent first base zones 4 to the surface of the substrate. The gate electrode layer 10 is provided over the exposed portions of the first base zone 4 , the second base zone 6 and the base layer 3 .

The thyristor of the first embodiment can be manufactured essentially by the same method as the conventional IGBT using different masks to form the respective diffusion zones. For the production of a component of the 1200 V class, for example, an n layer with a specific resistance of 0.05 Ωcm and 15 μm thick is used to create the n⁺ buffer layer 2 and an n layer with a specific resistance of 80 Ωcm and 115 μm thick to create the n base layer 3 epitaxially on a p silicon substrate with a thickness of 450 μm and a specific resistance of 0.02 Ωcm for the creation of an epitaxial wafer. The p⁺ well zone 5 , the first p base zone 4 and the second p base zone 6 are formed by implantation of boron ions and thermal diffusion, and the n emitter zone 8 and the n source zone 7 are formed by implantation of arsenic ions and phosphorus ions and thermal diffusion. The edges of the first base zone 4 , the second base zone 6 , the source zone 7 and the emitter zone 8 are determined by the gate electrode 10 made of polycrystalline silicon and others on the semiconductor substrate, and the distances between these zones 4 , 6 , 7 and 8 are determined by determines the diffusion of the respective zones in lateral directions. The cathode electrode 11 and gate electrode 13 are made of an Al alloy and are formed by sputtering, and the anode electrode 12 , which is to be soldered to a metal substrate, consists of three layers of Ti, Ni and Au, which are formed in layers by sputtering. The device is irradiated with an electron beam in order to control the charge carrier life and thereby reduce the switching time.

The diffusion depth of the tub zone 5 is 6 µm in a practical example and that of the first and second base zones 4 , 6 is 3 µm. The diffusion depths of the emitter zone 8 and the source zone 7 are 1 µm and 0.3 µm, respectively. If the diffusion depths of the respective zones are set in this way, the npn transistor of the thyristor section has an increased current amplification factor and the forward voltage is reduced. As for the width of the gate electrode layer 10 , an experiment was carried out by setting "Lg" between the first and second base zones to 15 µm and the distance "Lgmin" measured at the protrusion of the second base zone 6 in the range of 3 -15 µm was varied. The distance between adjacent first base zones 4 is 30 μm, the width of the source zone 7 is 4 μm and the cell grid dimension is 55 μm. The section of the emitter zone 8 , which is close to the first base zone 4 , has essentially the same diffusion depth as the source zone 7 , taking into account the withstand voltage.

The operation of the thyristor constructed as described above will now be described. When the cathode electrode 11 is grounded and a positive voltage equal to or greater than a certain (threshold) value is applied to the gate electrode 13 while a positive voltage is applied to the anode electrode 12 , an inversion layer (partial accumulation layer) is formed under the gate electrode layer 10 , and the lateral MOSFET is turned on. As a result, electrons are initially supplied from the cathode electrode 11 via the source zone 7 and the channel of the MOSFET to the base layer 3 formed in the surface layer of the first base zone 4 . These electrons act as a base current for a pnp transistor, which consists of the p emitter layer 1 , the n⁺ buffer layer 2 , the n base layer 3 and the p base zone 4 (p⁺ tub zone 5 ), and holes are injected from the emitter layer 1 and flow via the buffer layer 2 and the base layer 3 into the first base zone 4 . In this way, this pnp transistor works in the IGBT mode. Since the second base zone 6 is in a floating state in this mode, its potential increases slowly due to the hole current through the base layer 3 . As can be seen from the cross-sectional view of Fig. 2, when the transistor is turned on, the potential of the emitter zone 8 via the channel of the MOSFET is kept substantially the same as that of the source zone 7 , which is why electrons start after a while, uniformly of all Emitter zone 8 to be injected into the second base zone 6 . A thyristor section, which consists of the emitter layer 1 , the buffer layer 2 , the base layer 3 , the second base zone 6 and the emitter zone 8 , thus operates in a thyristor mode.

For switching off, the potential of the gate electrode layer 10 is lowered below the threshold value of the lateral MOSFET in order to block the lateral MOSFET, so that the emitter zone 8 is electrically separated from the cathode electrode 11 and the operation of the thyristor section stops.

When the transistor is switched on, the potential of the emitter zone 8 is kept substantially equal to that of the cathode electrode 11 via the channel formed just below the gate electrode layer 10 . In the thyristor of Fig. 1, both the surface of the second base region 6 as is also the emitter region 8 is covered with the insulating film 14, and the second base region 6 is not in contact with the cathode electrode 11. Therefore, the potential of the second base region 6 gradually increases due to the hole current through the base layer 3 until electrons are injected from the emitter region 8 . In this way, the thyristor consisting of the emitter zone 8 , the second base zone 6 , the base layer 3 and the emitter layer 1 is turned on. Thus, the IGBT mode can be quickly switched to the thyristor mode without a hole current flowing in the Z direction in the second base zone, as is the case with the conventional EST. Furthermore, the forward voltage is reduced because the electrons are injected uniformly from the entire emitter zone 8 .

On the other hand, the pn junction between the emitter zone 8 and the second base zone 6 can assume its blocking capability uniformly, as a result of which a current localization or concentration can be avoided, which guarantees a significant increase in the RBSO range. Furthermore, since a plurality of first base zones 4 with source zones 7 present in their surface layers are arranged around the second base zone 6 , the component of this embodiment is free of current concentrations or localization and has a high breakdown resistance.

The graph of FIG. 3 shows the current-voltage characteristic microns for the case of 15 and Lg Lgmin equal to 6 microns. In Fig. 3, the forward voltage is plotted on the abscissa and the current density on the ordinate. FIG. 3 also shows corresponding characteristic curves of two comparative examples in which the second base zone 6 and the emitter zone 8 have no projections, as shown in FIG. 4, which is a top view of diffusion zones of a silicon substrate. In these comparative examples, Lg = Lgmin. Fig. 6 is a cross-sectional view taken along line CC in Fig. 4. In Fig. 6, as in the case of Fig. 2 (b), the first base zone 4 is spaced a relatively large distance from the second base zone 6 .

In a practical example, the forward voltage at a current density of 50 A / cm ^{2 was} 2.0 V when Lg was 15 µm and no projections were provided, as shown by the middle characteristic curve in Fig. 3, while the forward voltage of the device according to the invention at the same current density was approximately 1.75 V (left characteristic in FIG. 3), which is 0.25 V lower than in the comparative example. This is because the channel (hereinafter referred to as an accumulation layer ) formed on the surface of the base layer 3 in the device of the present embodiment in which the second base zones 6 and the emitter zones 8 are provided with protrusions is shortened and be Resisted is reduced. The dotted characteristic curve in FIG. 3 corresponds to the other comparison example without projections, where the distance Lg between the first base zone 4 and the second base zone 6 was set uniformly to 6 μm. The forward voltage at a current density of 50 A / cm ² in this example is not less than 2.40 V. This is due to the fact that the contact FET effect has been intensified in contrast to the first embodiment described above and therefore the delivery of electrons was limited from the source zone 7 to the base layer 3 , which resulted in a reduced hole injection. As a consequence, the thyristor was turned on more slowly and the forward voltage was increased.

Fig. 7 is a graph showing the dependency of the forward voltage of Lgmin at a current density of 50 A / cm ^2. Lgmin, measured on the projections, is plotted on the abscissa, and the forward voltage is plotted on the ordinate. The service life was controlled in such a way that there was a constant switch-off loss. As shown in Fig. 7, the forward voltage decreased with a decrease in Lgmin and decreased to 1.57 V at Lgmin = 3 µm. This is because the supply of electrons from the source zone 7 as described above was not significantly restricted by the contact FET effect and the resistance of the accumulation layer was reduced. The saturation current density, which was measured for Lgmin in the range from 6 to 15 μm, was constantly 200 A / cm ² , ie did not change within this range. This is due to the fact that the saturation current density is determined by the volume of the gate oxide film and the impurity concentration on the surface of the first base zone 6 just below the gate oxide film. However, no current saturation occurred with a thyristor with Lgmin = 3 µm. This is because the first and second base zones 4 , 6 were connected or coupled in this case and therefore electrons were prevented from being supplied from the source zone 7 to the emitter zone 8 regardless of the potential at the anode.

The dashed curve in FIG. 7 shows the dependence of the forward voltage on Lg when Lg was changed. In this case, the forward voltage increases with decreasing Lg due to the contact FET effect described above. As the Lg increases, the forward voltage decrease decreases because the resistance of the accumulation layer increases and the thyristor area is reduced.

As can be seen from Fig. 7, a thyristor with a sufficiently low forward voltage can be provided by reducing Lgmin while keeping Lg at a certain large value instead of simply reducing Lg.

The graph in Fig. 8 shows compromise characteristics between the forward voltage V _on and the turn-off time T _{ab of} the thyristor when the carrier lifetime has been changed. The forward voltage, measured at a current density of 50 A / cm ² , is plotted on the abscissa, while the switch-off time is plotted on the ordinate. For comparison purposes, FIG. 8 also shows the compromise characteristics of the comparative examples explained above, in which the second base zones have no projections, namely the EST shown in FIG. 25 (hereinafter referred to as EST-1), the EST shown in FIG. 26 (hereinafter referred to as EST-2), the EST shown in Fig. 27 (hereinafter referred to as EST-3) and an IGBT. With the EST-2 and EST-3, the width of the n emitter zone 8 was set to 20 μm.

As is apparent from Fig. 8, the thyristor of the first embodiment has a much better compromise characteristic than the above comparative examples. Of the comparative examples without protrusions of the second base zones, the one with Lg = 15 µm has a property similar to the EST-3, while the one with Lg = 6 µm is worse than that of the IGBT for the reasons described above.

Second embodiment

In the second exemplary embodiment, lifespan control was carried out by implanting helium ions instead of irradiating the component with an electron beam, as is the case in the first exemplary embodiment. The irradiation with helium ions was carried out under the conditions of an accelerating voltage of 24 MeV and a dose amount of 1 × 10 ¹¹ to 1 × 10 ¹² cm ² . After the irradiation, the component was left at 350-375 ° C.

The graph in FIG. 8 also shows the compromise characteristic between the forward voltage V _on and the turn-off time T _{ab of} the insulated gate thyristor of this second embodiment.

Radiation with helium ions is a method of generating crystal defects that Represent lifetime killers in local sections of the device. Because with this method one optimal distribution of lifespan killers can be achieved and the lifespan killers are not in unnecessary sections occur, the thyristor of the second embodiment still shows one better compromise characteristic than that of the first embodiment.

In another insulated gate thyristor, lifetime control was irradiated with protons. The dose amount was essentially the same as that of helium ions used in the second embodiment. The component manufactured in this way had substantially the same properties as that of the second embodiment which was controlled by irradiation with helium ions.  

Third embodiment

Fig. 9 is a plan view showing the respective diffusion regions formed in the surface of a silicon substrate of an insulated gate thyristor according to a third embodiment of the present invention, again with insulating films and electrodes are not shown. According to FIG. 9, a pattern is formed in which a stripe-shaped second p base zone 6 with projections 6 'is formed in a surface layer of the n base layer 3 and stripe-shaped first p base zones 4 are arranged such that they face the long sides of the second base zone 6 . This pattern is repeated in the thyristor of the present embodiment. A stripe-shaped n emitter zone 8 with projections 8 ′ is formed within each of the second base zones 6 and a stripe-shaped n source zone 7 is formed within each of the first base zones 4 . The area indicated by dotted lines in the source zones 7 represents a contact zone of a cathode electrode 11 .

The cross section along the line DD in FIG. 9 is identical to that of FIG. 2 (a) and that along the line EE is identical to that of FIG. 2 (b).

The thyristor of the third embodiment is different from that of the first and the second embodiment only in its pattern viewed in the plane and points in other essentially the same operational and other characteristics as the previous ones Embodiments on.

As for the width of the gate electrode layer 10 , an experiment was carried out by setting the distance Lg between the first and second base zones to 15 µm and the distance Lgmin measured on the protrusions of the second base zone 6 in a range of 3 to 15 µm was varied. Fig. 10 shows a graph showing the dependence of the voltage V _on of Lgmin at a current density of 50 A / cm ^2. Lgmin is plotted on the abscissa and the forward voltage on the ordinate. The charge carrier life was controlled so that there was a constant turn-off loss. As shown in Fig. 10, the forward voltage decreases with decreasing Lgmin and drops to 1.62 V at Lgmin = 3 µm. This is because the supply of electrons from the source region 7 is not significantly restricted by the contact EFT effect, as described above, and the resistance of the accumulation layer is lower. The saturation current density measured for Lgmin in the range from 6 to 15 μm was constantly 300 A / cm ² and did not change within this range. This is because the saturation current is determined by the volume of the gate oxide film and the impurity concentration on the surface of the first base zone 4 just below the gate oxide film. However, no current saturation occurred with the thyristor with Lgmin = 3 µm. This is because the first and second base regions 4 , 6 are connected or coupled to each other in this case, and therefore electrons are prevented from being supplied from the source region 7 to the emitter region 8 , as described above with reference to the first embodiment has been.

The graph of FIG. 10 also shows the dependence of the forward voltage V _{on on} Lg of a comparative example in which the p base zones 6 and n emitter zones 8 had no protrusions in the planar pattern of the diffusion zones on the silicon substrate, as shown in FIG. 5. In this case, the forward voltage increases with decreasing Lg due to the contact FET effect described above. The rate of decrease in forward voltage decreases with increasing Lg as the resistance of the accumulation layer increases and the thyristor area is reduced.

As can be seen from Fig. 10, a thyristor with a sufficiently low forward voltage can be provided by reducing Lgmin while keeping Lg at a certain large value instead of simply reducing Lg.

Fig. 11 shows a graphical representation of compromise characteristics between the forward voltage V _on and the switch-off time T _{ab of} the thyristor of the third embodiment in which the charge carrier life was changed by irradiation with an electron beam. The abscissa shows the forward voltage measured at a current density of 50 A / cm ² , and the ordinate shows the switch-off time. For comparison, the compromise characteristics of the comparison examples without projections of the second base zones, which were explained above, are also shown in FIG. 11.

It can be seen that the thyristor of the third embodiment is a much better compro characteristic curve than the comparative example (Lg = 15 µm) without protrusions of the second base zones having. The comparative example with Lg = 6 µm has one for the reason described above even worse characteristic.

Fourth embodiment

While in the exemplary embodiments described above the n⁺ buffer layer 2 is provided between the p emitter layer 1 and the n base layer 3 , the present invention is also applicable to a similar thyristor without n ohne buffer layer 2 . The Fig. 12 (a) and 12 (b) illustrate cross-sectional views showing a part of an insulated gate thyristor according to a fourth embodiment of the present invention, which is prepared using a solid silicon wafer (bulk silicon wafer) instead of an epitaxial wafer. While the structure on one of the opposing main surfaces of the n base layer 3 of the solid silicon wafer is the same as that of the second exemplary embodiment from FIG. 3, the p emitter layer 1 is formed directly on the other main surface of the base layer 3 by implantation of boron ions and thermal diffusion. In an example of the present embodiment, a silicon wafer with a specific resistance of 60 Ω.cm and a thickness of 200 μm was used.

An experiment was performed on the width of the gate electrode layer 10 by setting the distance Lg between the first and second base zones to 15 µm and varying the distance Lgmin measured on the protrusions of the second base zone 6 within a range of 3 to 15 µm has been. The graph of Fig. 10 shows the dependence of the voltage V _on of Lgmin the case of a current density of 50 A / cm ^2. The charge carrier life was controlled so that there was a constant turn-off loss.

Also in the fourth embodiment, the forward voltage decreases with a decrease in Lgmin and drops to 1.77 V when Lgmin is 3 µm. The saturation current density measured for Lgmin within the range of 6 to 15 µm was constantly 200 A / cm ² and did not vary in this range. However, there was no current saturation of the thyristor with Lgmin = 3 µm. The reasons for these results are the same as those given above for the first embodiment.

The graph of Fig. 10 also shows the dependence of the voltage V _on of Lg in a comparative example in which the second p base regions 6 and the n emitter regions cracks 8 no on in the planar pattern of the diffusion regions on the silicon substrate having, as shown in Fig. 5 shown. In this case, the forward voltage increases with a decrease in Lg. The saturation current density, which was measured for Lg in the range from 6 to 15 μm, was constantly 200 A / cm ² and did not vary in this range, while no current saturation occurred at Lg = 3 μm.

As can be seen from Fig. 10, a thyristor with a sufficiently low forward voltage can be provided by reducing Lgmin while keeping Lg at a certain large value instead of simply reducing Lg.

Fig. 11 shows a graphical representation of compromise curves between the forward voltage V _on and the switch-off time T _{ab of} the thyristor of the fourth embodiment, in which the charge carrier life was changed by irradiation with an electron beam. The abscissa shows the forward voltage measured at a current density of 50 A / cm ² , and the ordinate shows the switch-off time. For comparison, the compromise characteristics of the comparison examples without projections of the second base zones, which were explained above, are also shown in FIG. 11.

It can be seen that the thyristor of the fourth embodiment is a much better comm promiss curve as the comparative example (Lg = 15 µm) without protrusions of the second Basiszo NEN. The comparative example with Lg = 6 µm shows for the reason described above an even worse characteristic.

Although the solid silicon wafer thyristor generally has a slightly larger pass-through chip voltage and a poorer compromise characteristic compared to a thyristor with epitaxial wafer , the use of the bulk silicon wafer eliminates the need for epitaxial growth and is still in terms of cost and reduced crystal defects advantageous. Because of these advantages, the solid silicon wafer thyristor may vary depending on Area of application and the required specifications of the component to be preferred.  

Fifth embodiment

In order to produce an insulated gate thyristor of the 600 V class in the same manner as the thyristor of the first exemplary embodiment, a 10 μm thick n layer with a specific resistance of 0.1 Ω.cm was created to create the n⁺ buffer layer 2 and a 55 µm thick n layer with a specific resistance of 40 Ω.cm to form the n base layer 3 epitaxially on a p silicon substrate with a thickness of 450 µm and a specific resistance of 0.02 Ω.cm to create an epitaxial wafer . The thyristor thus manufactured was used as an example of a device according to the fifth embodiment.

The thyristor of the present embodiment also had the same diffusion depths of the respective zones as that of the first embodiment. That is, the diffusion depth of the p⁺ tub zone 5 was 6 µm and that of the first and second p base zones 4 , 6 was 3 µm. The diffusion depths of the n emitter zone 8 and the n source zone 7 were 1 μm and 0.3 μm, respectively.

An experiment was carried out on the width of the gate electrode layer 10 by setting the distance Lg between the and the second base zones to 15 µm and the distance Lgmin measured at the protrusion of the second base zone 6 in a range of 3 to 15 µm was varied.

The graph in FIG. 13 shows the dependence of the forward voltage V _{on on} Lgmin in the case of a current density of 100 A / cm ² . The charge carrier life was controlled in such a way that there was a constant switch-off loss.

Also in the fifth embodiment, the forward voltage decreases with a decrease in Lgmin and drops to 1.50 V for Lgmin = 3 µm. The saturation current density measured for Lgmin in the range from 6 to 15 μm was constantly 400 A / cm ² and did not change within this range. However, no current saturation occurred with a thyristor with Lgmin = 3 µm. The reasons for these results are the same as those given above for the first embodiment.

The graph of FIG. 13 also shows the dependence of the forward voltage V _{on on} Lg in a comparative example in which the second base zones 6 and the emitter zones 8 had no protrusions in the planar pattern of the diffusion zones on the silicon substrate, as shown in FIG. 5 . In this case, the forward voltage increases as Lg decreases. The saturation current density measured for Lg in the range from 6 to 15 μm was constantly 400 A / cm ² and did not change within this range, while no current saturation occurred at Lg = 3 μm.

As can be seen from the graph of Fig. 13, a thyristor with a sufficiently low forward voltage can be created by reducing Lgmin while keeping Lg at a certain large value instead of simply reducing Lg.

Sixth embodiment

Fig. 15 is a plan view showing respective diffusion zones formed in the surface of a silicon substrate of an insulated gate thyristor according to a sixth embodiment of the present invention, again showing insulating films and electrodes. Although the thyristor of the present embodiment is similar to that of the first embodiment in that hexagonal first p base regions 4 are arranged in a hexagonal pattern in the surface layer of the n base layer 3 , the thyristor of this embodiment differs from that of the first embodiment in that second p base zone 6 , which is arranged in the middle of the hexagonal pattern of the first base zones 4 , has a hexagonal shape without projections and that the tips of the hexagonal second base zone 6 face the sides of the respective first base zones 4 . A generally annular n source region 7 with a hexagonal outline is formed within each of the first base regions 4 , and a hexagonal n emitter region 8 is formed within the second base region 6 . The area defined by the dashed line in the source zone 7 represents a contact area of a cathode electrode 11 .

The method of manufacturing the thyristor of the sixth embodiment and its Operations are substantially the same as those of the thyristor of the first embodiment game and are therefore not explained.

In the present exemplary embodiment, the distance between the first base zone 4 and the second base zone 6 or the width of the gate electrode layer 10 can be locally reduced or narrowed without forming the second base zone 6 with projections. That is, the area subject to the contact FET effect is geometrically reduced, and the resistance of the accumulation layer is reduced to provide a thyristor with a low forward voltage and a good compromise between the forward voltage and the turn-off time.

The graph in Fig. 16 shows the results of measurements of the RBSO region of the thyristor of the sixth embodiment and the EST-1, EST-2, EST-3 and IGBT as comparative examples. The RBSO range was measured at 125 ° C with a measuring circuit as shown in Fig. 17. In Fig. 16, the voltage V _AK between the anode and the cathode and on the ordinate the current I _AK is plotted on the abscissa.

As shown in Fig. 17, the connected to measuring device 21 via the parallel circuit of a 1 mH choke 22 and a freewheeling diode 23 to a power source 24, and the gate of the device 21 is applied via a resistor 25 of 20 Ω to a gate supply source 26. The device of the present embodiment, the measurement results of which are shown in Fig. 16, was manufactured as a 600 V class device, and the devices of the comparative examples were fabricated using epitaxial wafers of the same specification as that of the thyristor of the fifth embodiment described above. The n emitter zone 8 of both the EST-2 and the EST-3 had a width of 20 μm. All five components had a chip size of 1 cm ² . The forward voltage, defined as potential drop in a 100 A power line, was only 0.82 V for the thyristor of the sixth exemplary embodiment, but 1.6 V for the EST-1, 1.7 V for the EST-2, 1, 0 V for the EST-3 and 2.3 V for the IGBT.

As seen from Fig. 16, the device has the sixth embodiment of the invention, a lower forward voltage than the other components, and the safe operating area is three times as large as that of the IGBT and twice as large as that of the EST-1 and EST-3 , which means that the present device has a high breakdown resistance. While the present device has substantially the same breakdown resistance as the EST-2, it is advantageous over the EST-2 because of the lower forward voltage. In other words, the forward voltage can be reduced without adversely affecting the other properties. This is due to the fact that in the arrangement in which the emitter zone 8 and the base zone 6 are formed in a polygonal shape and these zones 8 , 6 are surrounded by a plurality of base zones 4 , no current concentration occurs.

Various structures of the first and second base zones other than that of the first embodiment of FIG. 1 and the third embodiment of FIG. 9 can be used to provide the structure shown in FIG. 15. For example, the first and second base zones can have a rectangular shape or a circular shape, or the first base zones can be arranged in a different way around the second base zone.

Seventh embodiment

The graph of FIG. 18 shows the RBSO range as measured at 125 ° C. for 2500 V class components, specifically for an insulated gate thyristor according to a seventh embodiment with the structure of FIG. 12 and the pattern of Fig. 15 and the EST-1, EST-2 which, the EST-3, and IGBT as comparative examples. In the graph of Fig. 18, the voltage V _AK is applied between the anode and cathode, and on the ordinate the current I _AK on the abscissa. In this case, the thickness of the base layer was 3440 microns. The other dimensions and others were substantially the same as those of the thyristor of the first embodiment. The forward voltages of these five types of components were measured at a current density of 50 A / cm ² and were found to be 1.01 V for the thyristor of the present exemplary embodiment, 2.0 V for the EST-1, 2.2 V for the EST- 2, 1.4 V for the EST-3 and 3.3 V for the IGBT. As in the case of the 600 V class devices with epitaxial wafers as described above, the measurement results shown in FIG. 18 regarding the 2500 V class devices with solid wafers indicate that the thyristor of the present embodiment of the invention compared to the ESTs and the IGBT, has a significantly large RBSO range and a low forward voltage. This is due to the fact that the current concentration when a high voltage is applied can be avoided by making the diffusion depth of the second base zone 6 smaller than that of the tub zone 5 . Furthermore, in the arrangement in which six first base zones 4 with source zones 7 formed on their surface are arranged around each of the second base zone 6 with emitter zone 8 formed on their surface, the first and second base zones 4 , 6 are enlarged Length opposite, which prevents a current concentration.

Thus, according to the present invention, the RBSO area can be increased without lowering the forward voltage regardless of the resistivity of the base layer 3 and the current gain of the pnp wide base transistor. In other words, the present invention is suitable for reducing the forward voltage and increasing the RBSO range regardless of the nominal voltage of the device and the method of manufacturing a semiconductor crystal of the substrate of the device.

Eighth embodiment

Using an n silicon wafer with a resistivity of 200 Ω.cm and a thickness of 600 μm was the same as in the first embodiment Insulated gate thyristor manufactured in the 4500 V class. The thyristor thus produced served as an example of an eighth embodiment of the invention.

The thyristor of the eighth embodiment had the same diffusion depths of the respective zones as that of the first embodiment. That is, the diffusion depth of the p⁺ well zone 6 was 6 µm and that of the first and second p base zones 4 , 6 was 3 µm. The diffusion depths of the n emitter zone 8 and the n source zone 7 were 1 μm and 0.3 μm, respectively.

An experiment was performed on the width of the gate electrode layer 10 by setting the distance Lg between the first and second base zones to 15 µm and the distance Lgmin measured on the protrusion (s) of the second base zone 6 in a range of 3 was varied up to 15 µm.

The graph in FIG. 14 shows the dependence of the forward voltage V _{on on} Lgmin at a current density of 15 A / cm ² . The charge carrier life was controlled in such a way that there was a constant switch-off loss.

In the sixth embodiment as well, the forward voltage decreases with decreasing Lgmin and drops to 1.50 V at Lgmin = 3 µm. The saturation current density measured for Lgmin in the range from 6 to 15 µm is constantly 100 A / cm ² and does not vary within this range. No current saturation occurs with the thyristor with Lgmin = 3 µm. The reasons for these results are the same as those given above for the first embodiment.

The graph of Fig. 14 shows the dependence of the voltage V _on of Lg in a comparative example in which the second base regions 6 and emitter regions having 8 no protrusions in the planar pattern of the diffusion regions on the silicon substrate as shown in FIG. 5. In this case, the forward voltage increases as Lg decreases. The saturation current density measured for Lg in the range from 6 to 15 µm is constantly 100 A / cm ² and does not change within this range, while no current saturation occurs at Lgmin = 3 µm.

As can be seen from the graph of Fig. 14, a thyristor with a sufficiently low forward voltage can be created by reducing Lgmin while keeping Lg at a certain large value instead of simply reducing Lg.

Ninth embodiment

Fig. 19 is a sectional view of a portion of an insulated gate thyristor according to a ninth embodiment of the present invention. The thyristor has the planar hexagonal pattern of Fig. 4 to distinguish its effects . This embodiment differs from the first embodiment shown in Fig. 2 (b) in that the thickness of the gate oxide film 9 varies from one portion to another. In Fig. 19, the gate oxide film 9 , which lies above the first base zone 4 , has the same thickness as that of the first embodiment of Fig. 2, namely 0.07 microns, while the gate oxide film 9 a, the above the second base zone 6 and Base layer 3 lies, has a reduced thickness (in this embodiment 0.05 microns).

In the thyristor of the ninth embodiment, the resistance of the inversion layer which occurs in the surface layer of the second base zone 6 and the resistance of the accumulation layer which occurs in the surface layer of the base layer 3 are reduced, which is why more electrons from the source zone 7 to the emitter zone 8 are supplied, which increases the number of electrons injected from the emitter zone 8 and thus reduces the forward voltage.

Five components of the 600 V class were produced using epitaxial wafers as a pattern, namely the thyristor of the ninth exemplary embodiment with the structure of FIG. 19 and the pattern of FIG. 4, the EST-1, the EST-2, the EST- 3 and the IGBT. The width of the source zone 7 was 4 μm and the width of the emitter zone 8 of the EST-2 and EST-3 was 20 μm. All five components had a chip size of 1 cm ² . The forward voltage, defined as the potential drop at a current density of 100 A / cm ² , was 0.8 V for the thyristor of the ninth embodiment, 1.6 V for the EST-1, 1.7 V for the EST-2, 1 , 0 V for the EST-3 and 2.3 V for the IGBT.

The graph in FIG. 22 shows the compromise characteristics between the forward voltage V _on and the switch-off time T _ab for the five components. The forward voltage is plotted on the abscissa, and the ordinate shows the switch-off time, measured at 125 ° C. As is apparent from Fig. 22, the component of the tenth embodiment shows a better compromise characteristic than the ESTs and the IGBT. Thus, a high voltage insulated gate thyristor using a solid silicon wafer shows a similar effect to that using an epitaxial wafer.

Eleventh embodiment

Fig. 23 shows the cross section of a portion of an insulated gate thyristor according to an eleventh embodiment of the invention. This thyristor has the planar pattern with the hexagonal arrangement shown in FIG. 4 to distinguish its effects . This eleventh embodiment differs from the first embodiment shown in FIG. 2 (b) in that the width of the exposed portion of the second base zone 6 is between the base layer 3 and the emitter zone 8 is smaller than the width of the exposed portion of the first base zone 4 between the base layer 3 and the source zone 7 . More specifically, the width of the exposed portion of the first base zone 4 is about 2 µm, while the width of the exposed portion of the second base zone 6 is about 1 µm.

In the thyristor of the eleventh embodiment, the resistance of the inversion layer appearing in the surface layer of the second base region 6 is reduced, and therefore more electrons are supplied from the source region 7 to the emitter region 8 , resulting in an increased number of electrons from the emitter region 8 are injected, and thus to a reduced forward voltage.

A pattern of the thyristor of the eleventh embodiment having the structure of FIG. 23 and the pattern of FIG. 4 was fabricated using an epitaxial wafer as in the 600 V class device described above. The width of the source zone 7 was 4 μm and the chip size 1 cm ² . The forward voltage, defined as the potential drop at a current density of 100 A / cm ² at 25 ° C, was 0.9 V.

The graph in Fig. 20 also shows the compromise characteristic between the forward voltage V _on and the turn-off time T _{ab of} the thyristor of the eleventh embodiment. The switch-off time was measured at 125 ° C. As is apparent from Fig. 20, the device of the eleventh embodiment shows a better compromise characteristic than the ESTs and the IGBT.

Twelfth embodiment

Fig. 24 is a cross-sectional view showing a portion of an insulated gate thyristor according to a twelfth embodiment of the present invention. This exemplary embodiment differs from the eleventh exemplary embodiment according to FIG. 23 in that a solid wafer with a specific resistance of 150 Ω.cm and a thickness of 440 μm was used instead of an epitaxial wafer. As in the eleventh embodiment, the width of the exposed section of the second base zone 6 between the base layer 3 and the emitter zone 8 is smaller than the width of the exposed section of the first base zone 4 between the base layer 3 and the source zone 7 .

A pattern of the thyristor of the twelfth embodiment having the structure of FIG. 24 and the pattern of FIG. 4 was fabricated using a solid wafer as in the 2500 V class device described above. The width of the source zone 7 was 4 μm and the chip size 1 cm ² . The forward voltage, defined as the voltage drop at a current density of 25 A / cm ² at 25 ° C, was 1.1 V.

The thyristor of the twelfth embodiment has substantially the same compro mismatches between the forward voltage and the switch-off time like the thyristor of the tenth Embodiment and a better compromise characteristic than the ESTs and the IGBT. This shows that a high voltage insulated gate thyristor for which a solid silicon wafer an effect similar to that used using an epitaxial wafer has manufactured thyristor.

Some features of the thyristors according to the invention described above can be used to obtain the respective effects of the features can be combined in order to distinguish a thyristor to create properties.

The conventional EST changes from the IGBT mode to the thyristor mode in which the Thyristor is locked, using the potential drop that is switched from that in Z-Rich flowing current is caused. According to the present invention is against covers the surface of the second base layer of the second conductivity type with the insulating film, and an increase in the potential of this second base layer due to the hole current becomes Switching the device into thyristor mode and used the blocking ability of the pn-over gangs when switching off to restore evenly, which makes the controllable current is increased. Furthermore, the base layer of the first conduction type contains a locally narrowed one Section between the first and second base zones of the second conduction type, whereby the effective channel length can be reduced and the contact FET effect is limited, which leads to a lower forward voltage.

In a preferred embodiment of the invention, the thickness of the gate insulating film is on the second base zone of the second conductivity type and the base layer of the first conductivity type smaller than that of the gate insulating film on the first base region of the second conductivity type. At a another preferred embodiment of the invention is the width of the exposed portion the second base zone of the second conduction type between the base layer of the first conduit type and the emitter zone of the first conduction type is smaller or narrower than the exposed one Section of the first base zone of the second conductivity type between the base layer of the first Line type and the source zone of the first line type. With these arrangements, the Resistance of the inversion layer on the surface of the second base zone of the second Conduction type occurs, and that of the accumulation layer, which in the surface layer of the Base layer of the first conductivity type occurs when a voltage is applied to the gate electrode, can be reduced, which leads to a reduction in the forward voltage.  

Thus the present invention provides a voltage controlled isolated thyristor Gate, which has a better compromise between the forward voltage and the shutdown time and a larger RBSO area than conventional ESTs and the IGBT, and over a wide withstand voltage range from 600 V to 2500 V.

The present invention not only improves the properties of the component itself, but also contributes significantly to reducing switching losses in a power switching device when using such components.

Claims (15)

1. Insulated gate thyristor comprising
a base layer ( 3 ) of a first conductivity type with high specific resistance,
first and second base zones ( 4 , 6 ) of a second conductivity type, which are formed in selected areas of a surface layer of a first main surface of the base layer ( 3 ),
a tub zone ( 5 ) of the first conduction type, which is formed underneath and connected to the first base zone,
a source zone ( 7 ) of the first conductivity type formed in a selected area of a surface layer of the first base zone ( 4 ),
an emitter zone ( 8 ) of the first conductivity type formed in a selected area of a surface layer of the second base zone ( 6 ),
a gate electrode layer ( 10 ) formed on a gate insulating film ( 9 ) over a surface of the first base region ( 4 ), an exposed portion of the base layer ( 3 ) and a surface of the second base region ( 6 ), these surfaces and the exposed portion lie between the source zone ( 7 ) and the emitter zone ( 8 ),
a first main electrode ( 11 ) which contacts an exposed section of both the first base zone ( 4 ) and the source zone ( 7 ),
an emitter layer ( 1 ) of the second conductivity type, which is formed on a second main surface of the base layer ( 3 ),
a second main electrode ( 12 ) which contacts the emitter layer ( 1 ),
a gate electrode ( 13 ) which contacts the gate electrode layer ( 10 ), and
an insulating film ( 19 ) covering entire areas of surfaces of the second base zone ( 6 ) and the emitter zone ( 8 ),
wherein the base layer ( 3 ) has a locally narrowed section which lies between the first and the second base zone ( 4 , 6 ). 2. Insulated gate thyristor comprising
a base layer ( 3 ) of a first conductivity type with high specific resistance,
first and second base zones ( 4 , 6 ) of a second conductivity type, which are formed in selected areas of a surface layer of a first main surface of the base layer ( 3 ),
a tub zone ( 5 ) of the first conduction type, which is formed underneath and connected to the first base zone,
a source zone ( 7 ) of the first conductivity type formed in a selected area of a surface layer of the first base zone ( 4 ),
an emitter zone ( 8 ) of the first conductivity type formed in a selected area of a surface layer of the second base zone ( 6 ),
a gate electrode layer ( 10 ) formed on a gate insulating film ( 9 ) over a surface of the first base region ( 4 ), an exposed portion of the base layer ( 3 ) and a surface of the second base region ( 6 ), these surfaces and the exposed portion lie between the source zone ( 7 ) and the emitter zone ( 8 ),
a first main electrode ( 11 ) which contacts an exposed section of both the first base zone ( 4 ) and the source zone ( 7 ),
an emitter layer ( 1 ) of the second conductivity type, which is formed on a second main surface of the base layer ( 3 ),
a second main electrode ( 12 ) which contacts the emitter layer ( 1 ),
a gate electrode ( 13 ) which contacts the gate electrode layer ( 10 ), and
an insulating film ( 19 ) covering entire areas of surfaces of the second base zone ( 6 ) and the emitter zone ( 8 ),
wherein the gate insulating film ( 9 ) has a first section ( 9 a) lying on the second base zone ( 6 ) and the base layer ( 3 ) and a second section lying on the first base zone ( 4 ), of which the first section has a smaller thickness than the second section. 3. Insulated gate thyristor comprising
a base layer ( 3 ) of a first conductivity type with high specific resistance,
first and second base zones ( 4 , 6 ) of a second conductivity type, which are formed in selected areas of a surface layer of a first main surface of the base layer ( 3 ),
a tub zone ( 5 ) of the first conduction type, which is formed underneath and connected to the first base zone,
a source zone ( 7 ) of the first conductivity type formed in a selected area of a surface layer of the first base zone ( 4 ),
an emitter zone ( 8 ) of the first conductivity type formed in a selected area of a surface layer of the second base zone ( 6 ),
a gate electrode layer ( 10 ) formed on a gate insulating film ( 9 ) over a surface of the first base region ( 4 ), an exposed portion of the base layer ( 3 ) and a surface of the second base region ( 6 ), these surfaces and the exposed portion lie between the source zone ( 7 ) and the emitter zone ( 8 ),
a first main electrode ( 11 ) which contacts an exposed section of both the first base zone ( 4 ) and the source zone ( 7 ),
an emitter layer ( 1 ) of the second conductivity type, which is formed on a second main surface of the base layer ( 3 ),
a second main electrode ( 12 ) which contacts the emitter layer ( 1 ),
a gate electrode ( 13 ) which contacts the gate electrode layer ( 10 ), and
an insulating film ( 19 ) covering entire areas of surfaces of the second base zone ( 6 ) and the emitter zone ( 8 ),
wherein the second base zone ( 6 ) has an exposed portion between the base layer ( 3 ) and the emitter zone ( 8 ) with a first width and the first base zone ( 4 ) has an exposed portion between the base layer ( 3 ) and the source zone ( 7 ) has a second width that is greater than the first width. 4. Thyristor according to claim 2 or 3, wherein the base layer ( 3 ) has a locally narrowed section between the first and the second base zone ( 4 , 6 ). 5. The thyristor according to claim 1 or 3, wherein the gate insulating film has a first section ( 9 a) lying on the second base zone ( 6 ) and the base layer ( 3 ) and a second section ( 9 ) lying on the first base zone ( 4 ) , of which the first section has a smaller thickness than the second section. 6. The thyristor of claim 1 or 2, wherein the second base zone ( 6 ) has an exposed portion between the base layer ( 3 ) and the emitter zone ( 8 ) with a first width and the first base zone ( 4 ) has an exposed portion between the Has base layer ( 3 ) and the source zone ( 7 ) with a second width that is greater than the first width. 7. Thyristor according to one of claims 1 to 6, wherein the first base zone ( 4 ), the second base zone ( 6 ), the emitter zone ( 8 ) and / or the source zone ( 7 ) a polygonal shape, a circular shape or an elliptical shape having. 8. The thyristor according to one of claims 1 to 7, in which the first base zone ( 4 ) and the source zone ( 7 ) formed in the surface layer thereof are formed such that they surround the second base zone ( 6 ). 9. Thyristor according to one of claims 1 to 7, in which a plurality of the first base zones ( 4 ) and a plurality of source zones ( 7 ) formed in the surface layers thereof are formed such that they surround the second base zone ( 6 ). 10. The thyristor of claim 9, wherein the first base zones ( 4 ), the second base zone ( 6 ), the emitter zone ( 8 ) and the source zones ( 7 ) each have a polygonal shape and each tip of the second base zone ( 6 ) and Emitter zone ( 8 ) faces one side of a corresponding one of the first base zones ( 4 ) and one side of a corresponding one of the source zones ( 7 ). 11. The thyristor according to claim 9 or 10, wherein the gate electrode layer ( 10 ) is substantially annular so that it surrounds the gate insulating film ( 9 ) on the second base zone ( 6 ), and that the first main electrode ( 11 ) on the Gate electrode layer is arranged opposite side, wherein an insulating film is formed between the first main electrode and the gate electrode layer. 12. The thyristor according to claim 11, wherein a contact portion between the first main electrode ( 11 ) and the first base zone ( 4 ) and the source zone ( 7 ) has a polygonal shape, a circular shape or an elliptical shape. 13. The thyristor of claim 12, wherein the emitter zone ( 8 ) has a diffusion depth that is greater than that of the source zone ( 7 ). 14. The thyristor of claim 13, further comprising a second well zone of the second conduction type, which is formed under and connected to the second base zone ( 6 ), wherein the second well zone has the same diffusion depth as the first well zone ( 5 ). 15. The thyristor of claim 14, wherein the lifetime killer in local sections of the Thyristors are present.