DE19707668A1 - Method of testing of communication paths in digital communication networks - Google Patents

Abstract

The communication network has a number of elements (NE1-8) arranged in a ring. These are synchronised by signals from a primary reference clock (PRC) source. The network is checked by introducing the reference clock and performing a phase modulation with a frequency less than the filter frequency of the elements. The phase modulation propagates unmodified from stage to stage and so checks the integrity of the connection. Any line break (BRK) between stages is identified.

Description

The invention relates to a method for checking clock paths in one synchronous digital communication system and a network element to carry out the procedure.

When transmitting messages in a synchronous digital Message transmission system, for example an SDH system or SONET system (SHD = synchronous digital hierarchy, SONET = synchronous Optical Network), it is essential that all network elements (e.g. add / drop multiplexers, crossconnects or line multiplexers) work synchronously with each other. In an article by R. Kiefer, ("Measurement tasks on SDH transmission systems", ntz Volume 46, Issue 2, p. 92-96, 1993) it is described that network elements by a reference clock (referred to as central clock, 2 MHz) can be synchronized. Is further described that for the simulation not ideal reference clock behavior an analyzer is connected between the reference clock source and the network element that can be the reference clock factor in certain writings in the Frequency out of tune. The network element responds with pointer operations that be documented by the analyzer to identify weaknesses in the Recognize system behavior. If the reference clock deviates too much switches the network element to substitute synchronization.  

However, the described method does not allow the connections to be over which a network element is supplied with the reference clock and it is not possible to find out via which procedure Connections a network element used for synchronization Receives reference clock.

An object of the invention is to provide a method for testing Clock paths in a synchronous digital message transmission system, indicate in the sense that the existence and functioning of the Connections is checked via which a reference clock on network elements of the synchronous digital messaging system is distributed. Another task is to implement a network element Procedure.

The problem is solved with regard to the method by the features of Claim 1 and with regard to the network element by the features of claims 9 and 11. Advantageous embodiments are the dependent claims.

The method according to the invention has the advantage that an examination of the connections is possible without there being any impairments in the Operation of the messaging system comes and that the Communication system configuration for measurement not needs to be changed.

In the following, the invention is based on exemplary embodiments and the following figures explained. Show it:

Fig. 1A is a synchronous digital message transmission system with plotted clock path (bold arrows),

FIG. 1b, the communication system of Fig. 1a with a different clock path as a substitute sync

FIG. 1c, the communication system of Fig. 1a having a clock path from an external reference clock source as a substitute synchronizing,

FIG. 1d, the communication system of FIG. 1 with an erroneous clock path (synchronization loop)

Fig. 2 is a schematic illustration of a message transmission system during execution of the method,

Fig. 3 shows a clock derivation circuit of a network element and

Fig. 4 shows another clock derivation circuit and a test device for a network element.

The network elements of a synchronous digital Communication systems are using a reference clock synchronized, which is distributed to all network elements. The reference clock is a pulse train with a pulse repetition frequency of, for example, 2 MHz. The Distribution takes place partly via digital communication links, whereby the reference clock in the network element from received message signals recovered and through low pass filtering of frequency fluctuations (Jitter) is freed, and to some extent via clock lines for example between several network elements of a network node. As In the following, the clock path is the physical connection between a Reference clock source, for example one with the reference clock synchronized first network element, and a second network element designated.

Checking clock paths is desirable to ensure that all network elements of the synchronous digital Communication system received the reference clock that in the event of failure from one or more connections or network elements to one Backup sync is toggled d. H. that a network element which loses connection to its reference clock source, another Selects source as the reference clock source, and that when distributing the Reference clock, especially when switching to Substitute synchronizations, no synchronization loops occur, d. H. that two network elements do not use each other as a reference clock source. In this sense, examining a clock path means that it passes  and functioning of a certain physical connections checked via which a network element is supplied with the reference clock.

A basic idea of the invention is now to test a Clock path at the beginning of the reference clock information modulate and this information at the end of the clock path too observe. If the information reaches the end of the cycle path, it is checked. Another basic idea is the modulated one To design information so that it by the low pass filtering in Clock derivation circuits of the network elements are not removed. It must the modulated information should be designed so that it is in the area permissible phase and frequency fluctuations is to the operation of the Communication system during an exam affect.

In a first embodiment, the synchronous digital message transmission system is an SDH system. This is shown in Fig. 1a. It consists of eight ring-shaped network elements NE1,. . ., NE8, which are also interconnected via numerous cross-connections. A central clock generator PRC (primary reference clock) is also shown, from which the first network element NE1 receives a reference clock for synchronization. In addition, the cycle path of the eighth network element is also indicated, indicated by thick arrows. As shown, the reference clock is distributed from the first network element NE1 to the other six network elements NE2,. . ., NE7 up to the eighth network element NE8. The reference clock is recovered from each network element from the message signal received from the previous network element.

In order now to the drawn according to the inventive method The clock path from the first to the eighth network element is checked Marks the reference clock of the first network element by giving it a Information is modulated on. Happens in the first embodiment this by modulating the reference clock in phase. This  Phase modulation has a modulation frequency that is lower than that Filter frequency with which the clock recovery in the network elements NE1,. . ., NE8 filter used low pass filter the reference clock. Thereby plants the phase modulation undisturbed by the intermediate network elements NE2,. . ., NE7 up to the network element NE8 continues. If now observed at the end of the clock path to be checked is that the reference clock of the eighth network element NE8 Phase modulation contains, so the conclusion can be drawn that an intact clock path between the first and the eighth Network element is present. For example, the reference clock, the eighth Network element NE8 from that of the seventh network element NE7 received message signal, with a Storage oscilloscope or can be checked with a frequency analyzer. Becomes the phase modulation is verified, the clock path is checked.

The same SDH system is shown in FIG. 1b, but the connection between the second and the third network elements NE2, NE3 is interrupted at the point BRK. The original clock path from the first to the eighth network element is therefore interrupted. This is affected by the affected network elements NE3, cut off from their reference clock source. . ., NE8 noticed. The network element NE5 switches to substitute synchronization by deriving its reference clock from the message signal received via the connection to the first network element NE1. The network elements NE6,. . ., NE8 now have a reference clock source again, and the fourth and third network elements NE3 also switch over to substitute synchronization by synchronizing themselves with the fifth and fourth network elements NE5, NE4, as shown in FIG. 1b.

In this constellation, the invention can now again Test methods are applied. The phase of the reference clock is at first network element NE1 modulated. On the eighth network element NE8, however on all other network elements NE2,. . ., NE7 can use phase modulation are observed, thereby verifying that the eighth NE8 also all other network elements NE2,. . ., NE7 a working clock path  to the first network element. With knowledge of the interruption BRK can also be concluded that the replacement synchronization of the affected network elements works.

This is different with the constellation shown in FIG. 1c. After the interruption BRK has occurred, the third network element NE3, after it has determined that its reference clock source has ceased to exist, has switched over to another substitute synchronization. It now uses an external reference clock source EXT. This can be either a further network element (not shown) or a second central clock generator (primary reference clock). The other network elements NE4,. . ., NE8 are correctly synchronized again in both cases, which is why there is no need for them to switch to substitute synchronization.

If one uses the constellation according to the invention Test method and marks the reference clock for the first network element NE1 with a modulated information, so you can see from the Fact that the information does not reach the eighth network element NE8, that the clock path from the first to the eighth network element NE1, NE8 is disturbed. Further investigations using the test method according to the invention can now be run so that it is checked step by step whether the clock path from eighth to the seventh network element NE8, NE7, from the eighth to the sixth Network element NE8, NE6, etc. is functional. For example gradually at the seventh, then at the sixth, etc. Network element NE7, NE8,. . . modulates the phase of the reference clock and observed this phase modulation on the eighth network element NE8. Is the Clock path up to the third network element NE3 checked, if known the interruption BRK found that one, for example intended replacement synchronization of the network element NE3 works.

A faulty configuration of the SDH system is shown in FIG. 1d. After the interruption BRK has occurred, the network element NE3 has switched to a faulty substitute synchronization in this case and has derived its reference clock from the message signal received by the seventh network element NE7. This could occur if a presetting for possible substitute synchronizations on the third network element NE3 has been made incorrectly and the third network element NE3 registers the interruption BRK before the seventh network element NE7. In the present case, a clock loop has formed, which must be avoided in any case in a synchronous digital messaging system.

With this constellation, checking the cycle path from the first to the eighth network element NE1, NE8 also that the clock path is interrupted is. Another test according to the method of the invention can now run so that the reference clock on the third network element NE3 in phase is modulated. By forming the clock loop, the Phase modulation, which is in the following network elements NE4 to NE7 is not filtered out on the one derived from the received signal Reference clock can be measured on the third network element NE3. This will the existence of the clock loop is determined and the error can be remedied will.

In FIG. 2, the arrangement is shown of a second embodiment of an inventive testing methods. A network management device MGMT of a synchronous digital message transmission system SDH, in this case also an SDH system, transmits the instruction to a network element SEC to modulate the phase of its reference clock. At a certain point END of the SDH system, the phase modulation is measured with a phase measuring device PMG. From the fact that phase modulation occurs at END, it is concluded again that there is an intact clock path TRACE between the network element SEC and the point END, which is thus checked.

A clock derivation circuit for a network element, which is capable of generating the phase modulation necessary for carrying out the test method, is shown in FIG. 3. It consists of a digital phase comparator DPK, which compares the phase position of the signals applied to its inputs and, depending on this phase position, generates a digital correction signal for a voltage-controlled crystal oscillator VCXO (voltage-controlled crystal oscillator). An external clock signal IN, for example the clock of a received message signal, is present at one input of the digital phase comparator DPK. The other input is connected to the output of the voltage controlled crystal oscillator VCXO. A digital low-pass filter TP is connected between the output of the digital phase comparator DPK and the control input of the voltage-controlled crystal oscillator VCXO, which minimizes the stationary phase error as an integrator, as well as an analog / digital converter ADW, which uses the filtered, digital correction signal to generate a control voltage for the voltage-controlled one Quartz oscillator VCXO generated. With this control voltage, the voltage-controlled crystal oscillator VCXO is adjusted to the external clock signal.

The digital phase comparator DPK has a control input with a target phase control device SPR is connected. By means of this Target phase control device SPR becomes a target phase between the external Clock signal and the output signal of the voltage controlled Quartz oscillator set to settling or VCXO Phase transients, for example when switching to one Avoid backup synchronization. There is a dashed line drawn connection from the digital phase comparator DPK to the Target phase control device SPR, on the large phase jumps from the Target phase control device SPR are registered and the target phase in in such a case.

The target phase control device SPR is with a control device CTR connected. This control device CTR now causes that in the event of a Testing according to the test method according to the invention, the target phase of the Target phase control device periodically between an upper and a lower value is changed. A phase modulation of the  Reference clock generated. This has the particular advantage that none of the existing connections must be separated in order to create an additional one Connect the device (generator) to generate the phase modulation. Opening a connection would configure the Message transmission system changed because in the meantime to a Replacement synchronization would have to be switched over to the clock supply of the relevant network elements. Even the measurement itself is greatly simplified.

In order not to impair the operation of the SDH system, the Modulation strokes, d. H. the difference between the mean of the target phase and the upper or lower value, in the range of plus / minus 125 ns. This value is used in particular if the Phase modulation of a network element at the hierarchy level stratum Level 3 is generated. Such network elements are called SDH equipment Called clock (SEC). In the event that the phase modulation from one so-called secondary clock supply of the hierarchy level stratum level 2 is generated, the modulation stroke can also be plus / minus 250 ns. Such secondary clock supplies are also called SSU (Synchronization Supply Unit). In addition, the duration of each should Modulation strokes in the range from 1 s to 1000 s to pass through Low pass filtering in the network elements cannot be removed. The Phase strokes are dimensioned so that no impermissible phase noise in the SDH system is generated. The temporary frequency offsets also remain below the critical value of 7.5 ppm for SDH network elements.

A modulation stroke, i. H. a phase change from phase mean to upper or lower value, means a binary sign + or -. A A particularly advantageous variant of the test method is the clock instead of the string + - + - + - + -. . . a binary coded string (e.g. CMI-coded). Despite the extremely small Transmission rate of 1 to 0.001 characters / s can be done in this way Information, for example about the synchronization status of the Network element transmitted at the beginning of the synchronization path. On  this way it is also possible to make parallel, independent measurements to perform, for example, the simultaneous checking of several clock paths to different network elements. It is also beneficial to use a as a string use finite string that is repeated periodically. This minimizes transmission errors. Such transmission errors can easily occur because the phase modulation is only slightly above the noise.

Another way to check the reference clock at the beginning of one Marking the clock path could be the clock in frequency to modulate.

For carrying out the method according to the invention, it is advantageous to be able to measure the information modulated onto the clock directly on a network element without the need for a further measuring device. A suitable network element therefore contains means for checking whether the reference clock contains the modulated information during a check. A clock derivation circuit and a test device PE for such a network element is shown in FIG. 4.

As in FIG. 3, the clock derivation circuit contains a voltage-controlled oscillator VCXO, an analog / digital converter ADW, a low-pass filter TP and a digital phase comparator DPK. The phase comparator DP compares the phase position of the input clock signal and the clock of the oscillator VCXO and generates a correction signal depending on this phase position, which is fed to the oscillator VCXO via the low-pass filter TP and the analog / digital converter.

The digital phase comparator has a further output, the with the test device PE is connected. Via this connection the Phase comparator DPK periodically after specified time intervals current phase measurement, d. H. a value for the phase position between Input clock and oscillator clock. The time interval can be, for example  Value between 10 ms and 100 ms. The phase measurements become one Device PSE for detecting phase jumps supplied. That follows an evaluation device AUS, which according to known Data regeneration process works. For example, a Overlay of multiple cycles of the string can be evaluated. This measure suppresses phase noise. Both, Phase shift detection and evaluation can be implemented by software be.

It is also particularly advantageous here during the measurement Bandwidth of the clock derivation circuit by the low-pass filter TP is determined to decrease to an appropriate smaller value so the phase modulation generated during the measurement is not in the Clock derivation circuit of the receiving network element is damped.

Claims (12)

1. A method for checking clock paths in a synchronous digital message transmission system, via which a reference clock is transmitted to network elements for synchronization, characterized in that

• the reference clock is marked at the beginning of the clock path to be checked by modulating information on it,
• - The information is designed so that the operation of the synchronous digital communication system is not affected, and
• - At the end of the clock path to be checked, it is checked whether the reference clock contains the information modulated at the beginning.

2. The method of claim 1, wherein the information consists in that the reference clock is modulated in the phase. 3. The method according to claim 2, wherein the frequency of the Phase modulation is lower than a filter frequency with the low pass filter of network elements of synchronous digital Filter a communication clock received reference clock.   4. The method according to claim 2, wherein the modulation stroke of Phase modulation plus / minus 125 ns. 5. The method of claim 2, wherein the modulation stroke Phase modulation plus / minus 250 ns. 6. The method according to claim 2, wherein the time duration of the individual Modulation strokes of the phase modulation a predetermined size in Is from 1 s to 1000 s. 7. The method of claim 2, wherein the phase of the reference clock binary coded character string modulated from individual modulation strokes becomes. 8. The method of claim 7, wherein the string is is a finite string that is repeated periodically. 9. Network element of a synchronous digital Communication system with a clock derivation circuit that out derive a reference clock from a received message signal, marked by Means (CTR) for marking the reference clock corresponding to the reference clock during an execution of the method according to claim 1 Add information.   10. Network element according to claim 9, wherein the clock derivation circuit comprises the following assemblies:

• - a digital phase comparator (DPK),
• a setpoint phase control device (SPR) connected to the phase comparator for setting a setpoint phase,
• a digital low-pass filter (TP) which is connected to an output of the phase comparator (DPK),
• - An analog / digital converter (ADW) which is connected to the output of the digital low-pass filter (TP), and
• a voltage-controlled crystal oscillator (VCXO), the control input of which is connected to the output of the analog / digital converter (ADC),

and in which the means for marking the reference clock include a control device (CTR) connected to the setpoint phase control device (SPR), which periodically changes the setpoint phase between an upper and a lower value during execution of the method according to claim 1. 11. Network element of a synchronous digital Communication system with a clock derivation circuit that out derive a reference clock from a received message signal, marked by Means for checking whether the reference clock during execution of the Method according to claim 1 contains modulated information. 12. Network element according to claim 11, wherein the clock derivation circuit comprises the following assemblies:

• - a digital phase comparator (DPK),
• a digital low-pass filter (TP) which is connected to an output of the phase comparator (DPK),
• - An analog / digital converter (ADW) which is connected to the output of the digital low-pass filter (TP), and
• a voltage-controlled crystal oscillator (VCXO), the control input of which is connected to the output of the analog / digital converter (ADC),

and in which the means for testing the reference clock comprise a test device (PE) which is connected to the digital phase comparator (DPK) and regularly receives phase measurement values via this connection during the implementation of the method according to claim 1.