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DE19680641T1 - Fehlerspeicher-Analysiervorrichtung in einem Halbleiterspeichertestsystem - Google Patents

Fehlerspeicher-Analysiervorrichtung in einem Halbleiterspeichertestsystem

Info

Publication number
DE19680641T1
DE19680641T1 DE19680641T DE19680641T DE19680641T1 DE 19680641 T1 DE19680641 T1 DE 19680641T1 DE 19680641 T DE19680641 T DE 19680641T DE 19680641 T DE19680641 T DE 19680641T DE 19680641 T1 DE19680641 T1 DE 19680641T1
Authority
DE
Germany
Prior art keywords
test system
analyzer
fault
semiconductor memory
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19680641T
Other languages
English (en)
Other versions
DE19680641C2 (de
Inventor
Takashi Saito
Hiromi Oshima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advantest Corp
Original Assignee
Advantest Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corp filed Critical Advantest Corp
Publication of DE19680641T1 publication Critical patent/DE19680641T1/de
Application granted granted Critical
Publication of DE19680641C2 publication Critical patent/DE19680641C2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
    • G01R31/31935—Storing data, e.g. failure memory

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)
DE19680641T 1995-07-19 1996-07-19 Fehlerspeicher-Analysiervorrichtung in einem Halbleiterspeichertestsystem Expired - Fee Related DE19680641C2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP7205342A JPH0933615A (ja) 1995-07-19 1995-07-19 半導体メモリ試験装置のメモリ不良解析装置
PCT/JP1996/002016 WO1997004328A1 (fr) 1995-07-19 1996-07-19 Analyseur de defauts de memoire pour dispositif de controle de memoire a semi-conducteurs

Publications (2)

Publication Number Publication Date
DE19680641T1 true DE19680641T1 (de) 1997-12-04
DE19680641C2 DE19680641C2 (de) 2000-08-24

Family

ID=16505315

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19680641T Expired - Fee Related DE19680641C2 (de) 1995-07-19 1996-07-19 Fehlerspeicher-Analysiervorrichtung in einem Halbleiterspeichertestsystem

Country Status (5)

Country Link
US (1) US5914964A (de)
JP (1) JPH0933615A (de)
KR (1) KR100277108B1 (de)
DE (1) DE19680641C2 (de)
WO (1) WO1997004328A1 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100468675B1 (ko) * 1997-07-25 2005-03-16 삼성전자주식회사 스태틱램자기테스트회로의어드레스발생기및어드레스발생방법
US6842867B2 (en) 2001-01-26 2005-01-11 Dell Products L.P. System and method for identifying memory modules having a failing or defective address
KR100940563B1 (ko) * 2002-12-06 2010-02-03 삼성전자주식회사 액정 표시 장치용 백라이트 어셈블리
JP4119789B2 (ja) * 2003-05-23 2008-07-16 横河電機株式会社 メモリ試験装置及びメモリ試験方法
JP4130811B2 (ja) 2004-03-24 2008-08-06 株式会社アドバンテスト 試験装置及び試験方法
JP2006012253A (ja) * 2004-06-23 2006-01-12 Advantest Corp 試験装置及び試験方法
JP4370527B2 (ja) * 2005-05-20 2009-11-25 エルピーダメモリ株式会社 半導体記憶装置
KR101199771B1 (ko) * 2005-12-19 2012-11-09 삼성전자주식회사 모드별 논리적 어드레스를 설정하는 반도체 메모리 테스트장치 및 방법
WO2008107996A1 (ja) * 2007-03-08 2008-09-12 Advantest Corporation 試験装置
US20080270854A1 (en) 2007-04-24 2008-10-30 Micron Technology, Inc. System and method for running test and redundancy analysis in parallel
WO2008139606A1 (ja) 2007-05-14 2008-11-20 Advantest Corporation 試験装置
WO2012004832A1 (ja) * 2010-07-07 2012-01-12 株式会社アドバンテスト フェイルキャプチャモジュールおよびそれを用いた試験装置、フェイルキャプチャ方法
JP2012038368A (ja) * 2010-08-04 2012-02-23 Toshiba Corp 不良解析装置及び不良解析方法
KR102634421B1 (ko) * 2016-11-21 2024-02-06 에스케이하이닉스 주식회사 페일 비트 카운터 및 이를 포함하는 반도체 메모리 장치
CN112466386B (zh) * 2020-12-07 2022-06-21 电子科技大学 一种面向故障分类的存储器测试系统及方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61271700A (ja) * 1985-05-27 1986-12-01 Advantest Corp メモリ試験装置
JPS62250593A (ja) * 1986-04-23 1987-10-31 Hitachi Ltd ダイナミツク型ｒａｍ
US5228000A (en) * 1990-08-02 1993-07-13 Mitsubishi Denki Kabushiki Kaisha Test circuit of semiconductor memory device

Also Published As

Publication number Publication date
US5914964A (en) 1999-06-22
WO1997004328A1 (fr) 1997-02-06
JPH0933615A (ja) 1997-02-07
KR100277108B1 (ko) 2001-01-15
KR970705033A (ko) 1997-09-06
DE19680641C2 (de) 2000-08-24

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee