DE19601575A1 - Parallel cutting of binary integer numbers for image processor - Google Patents

Abstract

In a circuit (100) and method for clipping input integers to a specified range, a mask is provided in which a bit is set for each out-of-range bit and not set for in-range bits and the mask is applied to input integers so that any integer outside of the range is clipped to the quantity in the range closest to the integer, thereby producing output integers within a range specified by the mask. The input data are sub-divided into blocks which are clipped in parallel. The arrangement allows clipping from both signed and unsigned input data and to both signed and unsigned output data in any combination. A clip instruction includes a mask field. The data type may be encoded in the instruction opcode and/or in the mask.

Description

The present invention relates to data processing systems and in particular to a method and a Device for parallel truncation of integers.

Since their first use, computers have changed dramatically developed. The first computers were mainly for nu meric calculations used. As well as the spoke Computer recovery and recovery capabilities improved, computers were often used for data management turns. While computer storage in the past mainly for storing text and numerical information mations has been used, modern computers have memory opportunities that are large enough to accommodate large menus image data.

Another dramatic change in computers is that comprehensive improvement in processor speed. A increased processor speed also led to many new applications.

In parallel to the development of computers, the Development of video and sound technology as well as communication cation technology instead. These technologies were increasing mend computerized.

A result of the parallel development of these technologies is the mixing of applications, for example a user is enabled with saved To interact with images and sound. The merger of Vi deo and audio technologies with computer technology is often Called "multimedia". Multimedia builds on skills modern computer to store both large amounts of data as well as perform quick calculations.  

An important functionality for multimedia applications is the ability to view images and sequences of images via exi permanent communication networks, e.g. B. telephone networks from one Transfer computer to another. The amount of data that has to be transferred is huge. A color image on one SVGA terminal, for example, requires a data amount of 780 kilobytes. An image sequence, such as B. a film recording, can contain billions of bytes. Unfortunately the bandwidth of currently existing networks to be very narrow. To the problem of transferring large Solve amounts of data over narrow bandwidth networks several industry-standard image compression tech niken designed such. B. MPEG, JPEG and H.261. This tech Techniques are continuously changed. Although it is possible has been to design processors to make special compresses It is therefore very difficult to carry out sion techniques design a processor that can be programmed to any of the current and future compression to handle techniques.

MPEG, JPEG, H.261 and other compression techniques common that they have integer arithmetic operations execute the numerical representation of the images they compress. These operations can be in numerical sizes result that are outside the permissible range of Hardware. For example, consider the case tends that certain standards only eight bits per pixel to let. It wouldn't be unusual for compression operas be pixel values with 11 to 12 significant bits testify. If the attempt is made such values a hardware display with a limit of eight bits per Displaying pixels, the result is unpredictable. Therefore it is necessary to keep the results within an acceptable range to cut off.

In the prior art, the clipping of bytes for unsigned integer values through use in the following sequence:

if (ix <0) ix: = 0;
if (ix <255) ix: = 255.

Unfortunately, this simple sequence results when it is translated into a machine code, in a code with two comparison operations and two branches. Further would need the sequence even though multiple processors are used are executed sequentially on all pixels in an image will. Because the bus width and the register width of most modern computer is much larger than 8 or 16 bit performing the clipping operation on a pixel the entire performance of the computer at a time not from.

Certain architectures, such as B. RISC (RISC = Reduced In struction set computer = computer with reduced command set) have only a limited number of opcodes on. With these architectures it is therefore important to have one to create new functionality without the number of Opera tion codes used in the processors are essential Lich increase. Such functionality is the Ab intersect integers to specified ranges. It is therefore desirable to use these computers or processors with the Ability to truncate integers to a specific decorated area using only one machine name to fail.

The object of the present invention is there rin, a method of operating a digital processor and to create an integer truncation circuit fen to quickly and flexibly cut off integers len to perform.

This object is achieved by a method according to claim 1 and solved by a circuit according to claim 18.

It is desirable to have a general purpose computer or one  Image processor with the ability to cut quickly of integers. It is also desirable a computer or processor with the ability of Ab truncate integers in a parallel fashion Mistake.

There is therefore an essential need for a verb technology for the fast truncation of integers.

Generally speaking, the invention allows parallel Ab intersect integer values. A hardware that the Invention incorporates means for storing of input data to be cut off. The one Data is saved in one or more input blocks divides which one is cut off in parallel the. The hardware also contains a device for storage a mask. The mask is displayed on the input data applies such that integers larger than the largest Integers of a specified output range are, by this largest integer will be replaced, whereas integers, which is smaller than the smallest integer of the output area are replaced by this smallest number. With the be preferred embodiment, all bits of the input data tenwortes processed in parallel.

The mask defines the area of the output data. The need Ease of truncating an integer is determined by Ver same the mask with corresponding data bits determined. If at least one mask bit is set to one truncated data bit, is generally the clipping necessary. If the cutting is not necessary, will the input data block to the output data block with a any required movement of a sign bit headed. If cutting is necessary, an ab cutting signal set to indicate the hardware that required the smallest or largest number in the output block to force.  

The invention allows cutting both vorzeichenbe liable as well as unsigned input data for both signed as well as unsigned output data in any combination. However, it becomes general not preferred to unsigned input to one before to cut off character-bound output. The data type of the Input and output can either be in the clipping ope ration code, in the mask or in the combination of the Opera tion codes and the mask.

An object of the invention is a parallel Ab to enable integer intersection.

Another object of the invention is for the pa parallel integer truncation and alternative To create embodiments that the parallel Ab cutting function with the minimum number of operations Execute codes that are used in a processor.

Preferred embodiments of the present invention are referred to below with reference to the attached drawing nations explained in more detail. Show it:

Fig. 1 is a block diagram of a processor with an integer clipping circuit according to a preferred embodiment of the invention;

Fig. 2 is a block diagram showing the building blocks of the clipping circuit according to a preferred embodiment of the invention and the data, mask and output registers;

Fig. 3 is a block diagram showing a circuit arrangement for determining the value of the sign bit indicates the entranc be-storage area corresponding to display data of each byte off;

Fig. 4 is a block diagram showing details of the half-word and byte logic circuits of the clipping circuit of Fig. 2;

Fig. 5 is a block diagram showing the size selection gate of each byte logic circuit of Fig. 4;

FIG. 6 is a logic diagram of the bit logic circuit of the byte logic circuits of FIG. 4.

The invention is intended to be used in a general purpose compu processor or in any other programmable processor. The invention enables that the processor truncates integers by one gen assembly language command used. In addition, he the invention allows processors with a bus width that wider than the width of the untruncated integers is the parallel truncation of multiple integers.

Fig. 1 is a block diagram of a microprocessor 100 having a register file 101, an adder 103 and an integer clipping circuit assembly 105. Adder 103 and integer clipping circuit 105 are both connected to receive input from register file 100 and return results to register file 101 . The register file 101 is also connected to a memory 107 . Register file 101 is operable to selectively load its registers from memory 107 and to store the contents of the registers back into memory 107 .

The microprocessor 100 comprises a control unit 109 which is connected to a microcode memory 111 . The control unit is connected via a signal path 113 to the register file 101 , the adder 102 , the clipping circuit 105 and to other components, not shown. Microcode memory 111 contains instructions for controlling the operation of the various components of microprocessor 100 . The control unit can be operated in order to receive commands from a program memory, for example from the memory 107 . The control unit decodes these commands and retrieves a corresponding microcode program from the microcode memory 111 . In response to the microcode commands forming this microcode program, the control unit 109 sends signals to the various components of the processor including the register file 101 , the adder 103 and the clipping circuitry 105 via the signal path 113 .

It is obvious to a person skilled in the art that the microprocessor 100 is connected to further processors and / or peripheral devices via a bus. These components are known to those skilled in the art and are therefore not shown.

In the preferred embodiment, memory 107 contains addressable positions, each 64 bits wide. Furthermore, the registers in the register file 100 are at least 64 bits wide, the paths between the memory 107 and the register file 101 , between the register file 101 and the adder 103 and between the register file 101 and the clipping circuit 105 being at least 64 bits wide.

In an application of the invention, memory 107 contains digitized images. It is known that in image processing arithmetic operations are performed on the integers representing the data associated with a given picture element (pixel). These operations often extend beyond the dynamic range of data that is supported by the graphics hardware. To prevent unpredictable behavior, the data is truncated to fall within the range expected from the display hardware.

For example, a device capable of 256 integers representing values would be 8-bit (1-byte) pixels point. A modification of the picture, such as. B. an edge  improvement with a normal 4-byte integer arithmetic metik performed would result in some values that are less than 0 or greater than 255.

For reasons of illustration, the following 64 bits are considered tet:

example 1

These 64 bits exemplify what can be stored in a storage position in memory 107 . In this example, each half-word (16 bits) contains the value for the light intensity to be displayed by a pixel. Each pixel value is held in one byte while the other byte contains zeros. Certain arithmetic operations, such as those that compression image protocols such. B. MPEG, can cause the pixel values to overflow the 8 bits of the least significant byte of its half-word. For example, an arithmetic operation (or a series of operations) can do the following:

Example 2

If the dynamic range for a device's pixel values is the Range is from 0 to 255, the values in the halfword clipped to match the acceptable range agree to the unpredictable spending of these half words that are less than 0 and greater than 255 must be ver prevent. The cutting is carried out such that ne negative values through 0 (00000000) and those greater than 255 are replaced by 255 (11111111).

Binary data formats exist for the sign  afflicted and unsigned integers. The complex of two mentformat is the most common representation for vorzei integers and is used in this description of the preferred embodiments of the invention used. This enables three different types of clipping dependent on the input and the output type, namely the Ab intersect an unsigned input to a sign loose edition, cutting off a signed Input to unsigned output and clipping a signed entry to a signed entry issue. A fourth option is one unsigned input for a signed output to cut off. According to the preferred embodiment such a clipping is not allowed, however, a ver seek to perform such a truncation in return of the input data results as the result. Naturally alternative embodiments could also the Ab intersect an unsigned input to a sign Allow afflicted output.

A CLIP command instructs processor 100 to cut integer values stored in a register in register file 101 . The CLIP command has the following format:

CLIP, xyz source, mask, target

x gives the size of the input data, i. H. D (D = double word) for 64 bit, W (W = word) for 32 bit, H (H = half word) for 16 Bit and B (B = byte) for 8 bits. y indicates whether the input unsigned (U; U = Unsigned) or signed (S; S = Signed). The flag z indicates whether the output is at a unsigned (U) or signed (S) Integer to be truncated. The mask allows that the integers stored in the source register are cut off to any area. Fer The mask also allows all pixels to be cut off in parallel values that are stored in the register. With an out  example is y = 0 for an unsigned on and y = 1 for a signed entry. On similarly, z = 0 for unsigned output and z = 1 for signed output.

The mask contains a 1 for each bit that is outside of the range, and a 0 for each bit that is located within the area.

Fig. 2 is a block diagram of certain components of the Mi kroprozessors 100th It shows the building blocks of the clipping circuit 100 and the data, mask and output registers. The microprocessor 100 contains a mask register 201 , a data register 203 and an output register 205 . Each of the registers 201 to 205 is contained in the register file 101 . The command CLIP shows the processor 100 which register in the register file it should use as a data, mask or output register.

Microprocessor 100 also includes clipping logic 105 . The cut-off logic 105 is connected to each tab 201 to 205.

The clipping logic 105 is constructed from a set of repeated circuitry. The clipping logic 105 includes a double-word logic circuit 207 , two word logic circuits 209 a-b, four half-word logic circuits 211 a-d, eight byte logic circuits 213 a-h, and 64-bit logic circuits 215 (not individually named). The word logic circuits 209 are identical to one another, the half-word logic circuits 211 are identical to one another, the byte logic circuits 213 are identical to one another and the bit logic circuits 215 are identical to one another. What distinguishes the various repeated circuits is how they are connected to other circuit components. These connections are discussed below in connection with FIGS. 3-5. Each bit of the mask register 201 and the data register 203 is connected as input to a corresponding bit logic 215 . Similarly, each bit of the output register is connected as output to the corresponding bit logic 215 .

The parallel integer input data is in one or split up several input blocks. Any input block could for example, a halfword, in which case under assuming four-bit input data is four on would exist, each 16 bits wide is.

Fig. 3 is a block diagram of the double-word logic 207th This figure shows the circuit arrangement for determining the value of the sign bit of the input data block, which corresponds to each byte of the output data. The foremost bit of each byte in the data register is connected to one or more multiplexers (MUX) 301 a- 301 h. Bit 63 is connected to all multiplexers, for example, while bit 7 is only connected to multiplexer 301 a. The multiplexer is selected using the BHWD control lines (BHWD = Byte Half-word Word Double-Word = Byte Halbwort Wort Doppelwort). The BHWD control lines are set by the value of field X of the CLIP command. Outputs DB0-DB7 are inputs to logic 105 in FIG. 2, and in particular to an input SIGN in logic 215 in FIG. 6. Outputs DB0-DB7 control these sign inputs to B0 to B7 in logic 213 in FIG. 2.

The following table shows for each multiplexer from which bit of the data register 203 the output of this multiplexer is taken depending on the value of the BHWD control lines.

Table 1

The following table contains a pseudo code for each type of clipping operation. The pseudocode refers to each byte in the data register 203 .

Table 2

In this embodiment, the type of input and the output from the cut command operation code  there is no data type information in the mask coded. Therefore, the mask does not depend on the data type of the Inputs and expenses. The mask that is used to for example either signed or signed loose half-word (16-bit) integer inputs to either one signed or unsigned byte (8-bit) Cutting off integer output is shown below:

Example 3

When the mask shown as the bit pattern of Example 3 is on the unsigned input word is applied as a bit pattern (2) is shown, the following is unsigned Get integer result (the first line is the input bit pattern from example 2, the second line is the mask bit pattern of Example 3, and the third line is the Er result):

Example 4

When the mask shown as the bit pattern of Example 3 is on the signed input word, which as a bit pattern (2) is shown, the following sign is used Obtained integer result (the first line is that Input bit pattern from example 2, the second line is that Mask bit pattern from Example 3 and the third line is that Result):

Example 5

If the mask shown as the bit pattern of Example 3 is to the signed input word, which as Bitmu ster (2) is used, the following will be used Get unsigned integer result (the first line is the input bit pattern of Example 2, the second line is the mask bit pattern of Example 3 and the third line is the result):

Example 6

Fig. 4 is a circuit diagram of one of the half-word logic circuits, namely the half-word logic circuit 211 d. The half word logic 211 d contains the two byte logic circuits 213 g and 213 h. The byte logic circuit 213h corresponds to bits 0 to 7 of the data, mask and output word. In similarity Liche, the byte logic circuit corresponds to 213 g bits 8 to 15 °. Each of the byte logic circuits 213 includes bit logic circuits 215 for each bit that corresponds to it.

The data and mask registers are connected to the clipping logic such that the bits in the data and mask registers which correspond to one another are input to the byte logic circuits 213 to which these bits correspond. The byte logic circuits contain all eight XOR gates 401 (XOR = EXCLUSIVE-OR operation), each corresponding to a data bit. Each of the XOR gates 401 has two inputs, namely the data bit to which it corresponds and the sign bit which is determined for the corresponding byte, as shown in FIG. 3.

The outputs from the XOR gates 401 are linked bit by bit with their corresponding mask bit in AND gates 403 (AND = AND link) by means of the logical AND link. The outputs of this AND operation together with the output from a size selection gate 407 are ORed (in a gate 405 ). The output of the OR gate (OR = OR operation) is the signal CLIP of the pseudo code from table 2. The signal CLIP indicates whether the data must be cut off or whether it can be passed on to the output registers 205 . The CLIP signal is input to each of the bit logic circuits 215 .

Each byte logic circuit 213 with the exception of the foremost byte logic circuit 213 a has a size selection gate 407 . Each size selection gate 407 is an AND gate. An input to each size selection gate 407 is the value of the CLIP signal for the next higher byte logic circuit 213 . Each size selection gate 407 also receives as input a signal 409 indicating whether the next higher byte is part of the same input data as the present byte. The signal 409 depends on the size of the input block and where the particular byte in question fits into the input register 203 . Figure 5 shows the inputs to the various size selection gates 407 for the eight bytes in a 64-bit register. For each of the byte logic circuits 213b , 213d , 213f and 213h , the signal 409 has the value "H or W or D", where H = 1 if the input register is divided into half-word boundaries, W = 1 if the input register is divided into word boundaries and D = 1 if the input register is divided into double word boundaries (ie the register has only one input). If H, W and D are all 0, the input register is divided into byte boundaries. For each of the byte logic circuits 213c , 213e and 213g , the signal 409 is "W or D".

Table 3 below is a truth table for the operation of bit logic circuits 215 in Figure 6. Table 3 is divided into three sub-tables, Table 3a the signed input / output case, Table 3b the signed input / unsigned output case and Table 3c describes the case of unsigned input / unsigned output.

Table 3a

Truth table for bit logic 215 for signed input / signed output

Table 3b

Truth table for bit logic 215 for signed / unsigned case

Table 3c

Truth table for bit logic 215 for the unsigned input / unsigned case

Fig. 6 is a diagram of the bit logic circuits 215, which correspond to the truth table of Table 3.

In the embodiment discussed in connection with FIGS. 1 through 6, the type of clipping by the command itself is indicated by two opcode completion bits y and z and passed to the clipping circuit as signals ON_TYPE and OFF_TYPE.

There are three alternative embodiments, the bit in the mask register to use certain or all of the To requests for the opcode completion bit y (signed / unsigned entry) and / or z (signed / unsigned edition) to remove.

The three alternative embodiments are in Table 4 summarized.  

Table 4

Using the mask and completion bits to indicate the data type of input and output in alternative embodiments

In the second embodiment, this becomes the most significant Bit of the mask, d. H. Bit A, used to indicate whether the Input data is signed or unsigned (a Opcode completioner z contains the output data type selection). This can be done as no reason there is a signed 16-bit input to one truncated signed 16-bit output, where at signed 16-bit input data is the sixteenth bit the sign bit must be and therefore never masked away would be. In the embodiment described below  For example, A is 0 for signed input data and for unsigned input data 1.

In the third embodiment, this becomes the most significant Bit in the mask, d. H. Bit A, used to indicate whether the input data is signed or unsigned. If the input data is signed, that divides Mask bit B of the hardware state machine with whether the off give a signed or unsigned value to be cut off, reducing the need for the ope ration code completion z is omitted. If B is the same 0, the hardware cuts the output to sign peeled off integers, and if B is 1 intersects the hardware to unsigned integers. It is possible to use bit B to co-ordinate the output data type if there is a signed 15 bit output is cut off the 15th bit, which is the bit that is under the control of mask bit B, the front is character bit and therefore does not need to be cut off.

In the fourth embodiment, this controls operations code completion bit y the input data type and that Mask bit A controls the output. If A is 0, cuts the hardware to a signed output and if A is 1, the hardware cuts to one unsigned output. The use of the operation code completer y in the input specification lie provides the hardware with prior knowledge of the input type, to make the timing easier.

Table 4a contains examples of the fourth embodiment game and the case where the input is a halfword, for the case of a signed edition.  

Table 4a

Examples of truncation using a completion bit and signed output

The sign bit of the mask indicates whether the input is as before treated with signs or unsigned. The fol The pseudocode describes the clipping operation:

Table 4b

Pseudo code to truncate to signed output using a completion bit

The following example shows the clipping for the front case without using a completion bit represents:

Table 4c

Truncating to an unsigned result using a completion bit

The corresponding pseudocode is shown below:

Table 4d

Pseudocode to truncate to an unsigned result using a completion bit

The third embodiment uses the fact that the leading bit of the unsigned mask in is 1. This is due to the fact that the Truncation to the full width of the input data is not necessary is agile, e.g. B. for halfwords, the clipping on the full 16-bit area never performed. Similar ones It does not make any wise for signed output  It makes sense to move to a signed 15-bit area to cut. It is therefore possible to use the two leading bits of the Use mask to differentiate the cases.

The following halfword examples illustrate the third Design example:

Table 5

Examples of clipping, where the clipping type is encoded in the first two bits of the mask

The following pseudocode shows how the Ab works cutting operation, the type of cutting in the the first two bits of the mask is coded:  

Table 5b

Clipping pseudo code in which the type of clipping is encoded in the first two bits of the mask

The clipping logic 105 is operable to use one of the three alternative embodiments.

An alternative embodiment allows integers variable width too. In the alternative execution case any integer to be truncated have a different width than any other integer that  is stored in a common register, each Integer can be truncated to another range.

As an example, the following 64-bit bit pattern contains six Input elements, each 10 bits wide:

Example 7

The numbers 1 and 6 are positive numbers in the out range. The numbers 2 and 5 are positive numbers, that don't fit in the output area. The number 4 is one negative number that fits in the output range and the number 3 is a negative number that is not in the signed th output area fits. The pseudocode of the first execution Example is used for clipping. The following Bit pattern is used to make six 10-bit numbers into one Truncate unsigned 8-bit range:

0000 1100000000 1100000000 1100000000 1100000000 1100000000 1100000000

Example 8

The pseudocode of Table 1 is used to convert Ab perform cutting operation. Applying the bit pattern from Example 8 to the bit pattern from Example 7 under Ver application of the procedure of the pseudocode of Table 1 resul in the following edition:

0000 0000011010 0011111111 0000000000 0000000000 0011111111 0010101001

Example 9

An input to a signed 8-bit area the following mask bit pattern is used det:

0000 1110000000 1110000000 1110000000 1110000000 1110000000 1110000000

Example 10

Applying the mask from Example 10 to the input of Example 7 using the pseudocode of Table 1 for signed output produces the following Result:

0000 0000011010 0001111111 1110111000 1110000000 0011111111 0010101001

The clipping command for the unsigned and the unsigned truncated integer truncation of the alternative Exemplary embodiment reads as follows:

CLIP, t source, mask, target, where t is either U for the unsigned case or S for the signed case.

It is noted that the command does not specify the Contains input data size, or whether a parallel execution should be used. The hardware directs this information onen automatically from the mask. It is believed that the data in the register are aligned on the right. Which he Ste 1 in the mask gives the position of the sign bit of the first data element. The first 0 indicates the position of the foremost bits in the output field. The next 1 there the sign of the next number. The next 0 gives that first bit in the next output field, etc. until the The end of the mask word has been reached.

Claims (12)

1. A method of operating a digital processor ( 100 ) to truncate binary integers using a command to a specified range, comprising the following steps:

• (a) defining a clipping command having a mask field;
• (b) accepting a mask from the mask field with one bit in the mask set for each bit that is out of the range and bits in the mask not set for bits that are within the range; and
• (c) Applying the mask to the input integers such that all integers outside the range are trimmed to the size in the range closest to the integer, thereby producing output integers within a range defined by the Mask is specified.

2. The method according to claim 1, wherein the masking operation is carried out according to the following steps:
Using the mask to determine if clipping is necessary for each byte;
if clipping is necessary, use the mask to define where the output is set to 0 and where the output is set to 1. 3. The method of claim 1 or 2, wherein the truncation command causes the digital processor ( 100 ) to truncate input integers having a first data type to output integers having a second data type. 4. The method according to claim 3, in which the first data type and the second data type the group that signs the elements contains data with data and unsigned data. 5. The method according to any one of claims 1, 3 or 4,
wherein the clipping command can display input data from both signed and unsigned integers and truncated output data from both signed and unsigned integers; and
for the instruction's opcode completion bit, indicate the data types of integers in the input and output data. 6. The method according to any one of claims 1, 3 or 4,
in which the mask contains codes for specifying the data types. 7. The method according to claim 1, wherein the masking operation is carried out according to the following steps: 8.Integer truncation circuitry ( 100 ) stored in an input source ( 203 ) logically divided into at least one input data block, each input data block being sized to produce a truncated result that can be used in an output destination ( 205 ) is saved, paint with the following characteristics:
a control circuit ( 109 ) operable to accept a truncation command as input, the truncation command defining the size of the input data block and each input data block containing an integer;
a mask source ( 201 ) connected to the control circuit for storing a mask corresponding to each input data block;
a clipping determination circuit ( 401 , 403 , 405 , 407 , 409 ) operable to compare the mask with the input stored in the input source, thereby determining whether clipping is needed for each output block, and to designally produce a clipping whose value depends on the clipping determination; and
at least one bit level clipping circuit ( 215 ) connected to the clipping determination circuit, the input convenient ( 203 ), the mask source ( 201 ) and the output destination ( 205 ) such that each bit level clipping circuit ( 215 ) creates a 1-to-1 mapping between the input source ( 203 ) and the output destination ( 205 ); and
wherein all bit level clipping circuits ( 215 ) corresponding to an input data block are collectively operable selectively in response to the clipping signal to apply the mask to the input such that the bits corresponding to bits within the range become one in the output destination Bit pattern can be set, which represents a number that is in the range, the value of which is closest to the value of the integer contained in the input data block. 9. The circuit according to claim 8,
where each input block and each output block is a byte, and
wherein the clipping determination circuit ( 401 , 403 , 405 , 407 , 409 ) generates a clipping signal for each byte in the output destination. 10. The circuit of claim 9, wherein the truncation fails to specify that each input data block is selected from the set of double word, word, halfword, and byte, and the integer truncation circuit, each integer stored in the input source, has a sign bit. wherein the circuit is organized hierarchically and also has the following features:
a byte sign selection circuit;
at least one byte level circuit ( 213 ) connected to the sign selection circuit such that the sign selection circuit supplies the value of the sign bit of the integer corresponding to the byte level circuit to the byte level circuit, the Byte level circuit includes a plurality of the bit level circuits ( 215 ). 11. The circuit of claim 10, wherein the truncation determining circuit ( 401 , 403 , 405 , 407 , 409 ) is divided over the byte level circuits such that each byte level circuit ( 213 ) except the foremost byte level circuit ( 213 a) has a size selection AND gate, in which one input is connected to the cut-off signal of the next higher byte level circuit ( 213 ) and a second input is connected to a signal line, the value of which depends on the size of the input data block and on the Position of the byte level circuit ( 213 ) with respect to the other byte level circuits ( 213 ) depends. 12. The circuit according to claim 10,
in which each bit level circuit ( 215 ) with the byte level cut-off signal (c), with the byte sign selection circuit (db), with a mask bit in the mask which corresponds to the bit level circuit (m) with a data bit in the input source corresponding to the bit plane circuit ( 215 ) (d) and connected to a clipping type signal; and
in which the bit level circuit has a plurality of logic gates which generate an output bit (o) according to a truth table.