DE1959073C - Method for character recognition and device for carrying out the method - Google Patents

Description

6. Apparatus for carrying out the method A further development of the latter system is known from according to claim 1 with a to a scanner attached to the USA.-Patent 3,233,219 in practical cases allows memory content and whose memory locations are difficult to specify an "absolute" set of conditions with logical mask circuits, or to specify character representations. In order to avoid this and a clock, characterized in that difficulty, the output of each logic mask circuit partial character representation circuits are used in this case (30-0 to 30-9) with a counter (42-0 to 42-9) at ₄₅ Output signals connected to a decision circuit (48) by means of a resistor network are summed, the statistically determined

7. Apparatus according to claim 6, characterized in that probabilities for each character are taken into account by between each counter (42-0 to 42-9) and. The resistor network is a control matrix arranged in the decision circuit (48), the locking circuits (50-0 to 50-9) for each character identity to be recognized. 50 has an output line During the vertical shift of the information in the shift register

Matrix becomes the lowest value of the current one

Signal detected on the character output lines

The invention relates to a method for character- This is the most likely recognition of the

icidentification and a device for executing the ss character are displayed. In other words it will be here

x, which has a shift register matrix, among which for all characters in all positions of the

which information regarding a truth that is available from a vertically shifted piece of information

ikument scanned zone can be saved. probability values according to the highest probability

Such a device for character recognition is wanted. However, there is no summation

known from U.S. Patent 3105,956. The 60 or integration of the probability for each

G. 3, 8 and 9 of this patent show examples of individual characters in the shifted positions of FIG

hit register matrices. Figures 5 and 6 show case information instead.

Many simple mask circuits. Fig. 7 shows a variant of the detection system of the above

The patent shows a register of characters with the US Pat. No. 3,165,717 is shown schematically.

any test and clock control circuits. 65 put in the article »Multi-Channel Character

An improved form of the clock control circuits for the Recognition System "by G. M. B c r k i η and

identification cycle is in an optical character reader K. H. K η i c k m e y e r, IBM Technical Disclosure

r application that has already been published for some Bulletin, Vol. 6, No. February 9, 1964, p. 75 and 76. In

F i g. 1 show J
system with which the

g [ device f ^ corner W ^ placed .st character AA is tester 12 ^^ f ^ output and on by the ^^ "character

^VP J

the form of can be given
z. B from Jm £ J

this system will split the scanned data

It examines the number of blacks wisely

Se ^ uncts or cells s _P old white _f? counted, and Sn the minimum requirement for the presence of a Seeing is fulfilled, the count is the black Points in each column by means of a mask circuit

unfine distribution in different probabilities

Sts values for all different character identities

converted. To get the probability values for

5Ξ relevant characters for all of the columns xo position of which can be accumulated, is a number of counters Jj ^ ^e ^ ^de each to one of the different character identities.

^ assigns at the end of each cycle is fixed

. ! divides which of the counters asked the highest content and thus corresponds to the most likely detection. With this system, no shift register

Ex used so that the geometrical shape of the deviator ^from "**" £ _d S a clock generator of 15 touched characters are only incompletely encompassed. Control of ιarav ". Scanner and

fann. ^ Not recognized are lean 3S _tung-skin g Started overall "u ^at, can reliably X ^; deformed characters or those too fat or generates and ^e ^

^ it concerns an older patent application in German ^^^^ SSS OSenlegungsschriftl 956 164) a symbol recognition ^ en ^ emit characters

AaA ^ ^{And dOrt VorÜ}

In each case one counter provided for each character, _M ^ _is stored from binary memories

x ₅ the paper v
gander ^v ° n

J ^ VerfaS : inventive GesScS right-J HA with a

^ % _t symbolically ei of the writing-

Sr is directed. At rasi ^ _{ß or}

enf through which scanner further- ^ _{Document 11A} ,

% * £ ** elsewhere over are the characters after wera _under

«£ S a clock 15

generated
ao d ^ zugehong «JJ

n generated,

ÄoÄden aforementioned conventional character readers, satisfactory results were achieved, as far as elements to the reading of document is on which satisfies the pressure rather strict requirements, remain in practice the Bedurf- 2 for a machine consisting, the conditions under amounts wemger printed characters readin £ a it With the present invention; will data and signals »^ J
at the intersection

who are. In the ^ hnuJP « _{it in p}

f ^^^ wSi every little square % £ & * column lies and ™ _{B <2} i and 22, represent-

after e «^^ β ^ Γ, ^ Λβηι can. One

conditions to read printed characters, which have a .ta wen ρ _Mauix _

£ aage is. With the present invention; is DA 35} $ £% ££% "£ ^ of the matrix register 20 verher aims to provide a method and an apparatus Toggle RcgjstersteUen '21" - ^ _{rf Ausserd} em Schiebeb di rmöglicht both rich and lean overall connected D " «Ig ^ Jf ^ ₆ matrix register positions. the

g24 dn alternately

aims to provide a method and an apparatus admit, which makes it possible to reliably recognize both bold and lean characters as well as mutilated characters.

For a method for machine character recognition in which the scanning of characters is binary il derived and stored in a memory,

40

gjf, ESng 24 clock pulses are generated on line 16. ™ ^ »Ρ ^ of _{the line} 24 causes a ^ ffS matrix register 20 stored to a matrix register control

F i g. 1 schematically a device for Ze.chen-

^ Schematically the decision circuits are part of the in F i _g . 1 shown device

_F 3 Schematic representations of a matrix register in a hypothetical, greatly simplified application.

the

_{ywiring to {the} top matnx

register place 22 in the second column shifted etc. correct combination of information in the on-A bit value from the lowest matrix register place of the closed matrix register places are evaluated, extreme right column in the matrix register finds further comments on the pyramid structure which no more place to which it can be moved Mask connections and some source references for could and will therefore be eliminated. This infor- 5 specific examples can be found earlier,
Shortly after the information in the matrix register 20 has been moved through by each of the subsequently scanned bits, the outputs of the will run first. After each shift pulse on line 24, the matrix register positions are set to their new binary values and a clock pulse appears on line 16, and as a result, the outputs of the character mask switch, a new bit value is set on line 18 to io lines. The output values are then passed to the first matrix register location 21. Thus, by the next clock pulse on line 16 ab, the black-and-white information for the extreme right is requested, which is connected bit by bit to a number of output AND columns of a character in the extreme left elements 32-0 to 32-9, the other column of the matrix register 20, also called matrix inputs for short, with the outputs of the mask circuits, entered when a character 15 30-0 to 30-9 is connected during scanning. A third input on the document 11Λ is reached. Thereafter, line 33 of each of these AND gates is connected to a signal of this information bit by bit in the second column of the device 34, which shifts an additional mask matrix, while the scanning of the second circuit and the associated timing contains the vertical column of the character. The additional mask circuit has numerous elements within the matrix a real representation of the aborted, which is formed via the output lines 31 with the blanked characters, shifted and finally output lines of a suitably selected collection from the last matrix register position. The complete information relating to a scanned character connected by register positions in the matrix register 20, as well as an output line (not shown), remains in the matrix for a certain time certain information combinations in the, ie the number of columns of the matrix, and on connected matrix register positions, whereby the reason for the circumferential shift appears as a minimum requirement (MIZ) for the information in all possible matrix register positions. Identifying a character is considered. Except in some matrix register locations, the image of the circuit 34 contains suitable, not shown characters, is divided into two parts, in such a way that the upper 30 constituted gate circuits, which according to the generally known part of the image is in the lower part of the matrix and constructed in accordance with principles , serve the following purposes: vice versa, whereas in a number of other matrix- A first gate circuit is opened by an output register position the image of the character as a whole internal signal of the MIZ mask circuit and provides half of the matrix appears. The binary sampling information during an interval of e.g. D. 21 shift pulse mation is therefore allowed to run through the matrix to 35 and 21 clock pulses on the line 16 an earlier or later a real image of the scanned output signal on the input line 33. During this character in a well-centered position within the interval, which at the first acquisition of one for the matrix, and in addition to each time a character begins at least required information in a matrix register position for storing a new matrix register 20, the information in the scan information is to be made free. The in F i g. 1 moved 40 matrix registers 21 times and consequently showed three columns. Matrix 20 has only seven rows and shifted to the right and at the same time five columns in the matrix. This low number of 35 matrix posi- tion complements and centers. As a result of this signal on lionen gives only a rough picture of a scanned input line 3 to the AND gates 32-0 to sign. In practice, however, a finer output pulse is 32-9 these are prepared for this, during each .astraster and a correspondingly higher number of 45 clock pulses on the line 16 output pulses from matrix register positions are used and thereby the abandonment. A second control circuit in the circuit building a higher resolution image display in FIG. 34 is enabled at the end of the signal on the input line 33 matrix. In one on the market switched on and then remains in operation while a loaned machine is z. B. a matrix register with period of e.g. B. 16 shift pulses on the line 17 rows and ten columns used 50 24 and 16 clock pulses on the line 16 to a All matrix register positions 21, 22 are equipped with signal output on a line 36 to the decision output lines on which the ge - to supply circuits 48. This signal initiates stored content is manifested as a bundle of these initiates a decision cycle. Also during the 'output lines in FIG. 1 denoted by 31. During this signal, the information in the comprises the output lines of suitably selected additions is shifted to the right in the final stage by compilations of matrix register positions which are located on two columns to the right. During the preparatory phase a number of mask circuits 30-0 to 30-9 are connected to the signal on the input line 33 and the subsequent ones. Of these ten mask circuits, the signals on line 36, the output must each be assigned one of the numbers 0 to 9, of which only three signals from the MIZ mask circuit are shown in circuit 34 for the sake of simplicity. Each 6c can be blocked to prevent another mask circuit is a combination circuit with signal during this time comes into effect generated switching pulses is connected by matrix register locations for illustration purposes only. In each and in practice, depending on the dimensions of the mask circuit, the received input signals 65 of the matrix and the nominal character width relatively signals are logically combined into one output signal. can be changed to the matrix. As already said, this output signal can be used as a display for a higher resolution of the character _for the presence or absence of a pre-image a matrix with considerably larger images.

Width of a character should be a ^hl ™ SJ5e zShen ^registers * ° ^ώη & * ¹ * ^{111 wuide} · ^DenttufoI 8 ^e " ¹ ^ ^em

blow _at "tight" Y "iJJ" ^^ "5 ggS" ^ the line 55, that no register position

to be able to read. ^^^ S ^ world- * was entered in the sign register. This signal is

Using a matrix satisfies ^W 5 ™ ⁿ · ™ ·, _{in any case at the} beginning of a decision cycle

borrowed is greater than the _existing ^{in this simple example J} _{anden Dic logic} combination circuit 56

chose. Rectangle 10 which only emits a signal on the output line 57,

In Fig. 1 are in the dashed rectangle lü a «^ ^. ^ ^ _Register digits of the χ ^.

for the embodiment of the invention '«J ™. are set, so shows an Erkenten circuits shown. These gfh ° ^ren "" f * "" £ _nu ngskonflikt on. The line 58 eventually goes from binary counters 42-0 to 42-9, each with four with den_iit _def ⁸ _{decision circuit 4g,} and supplies a remotely 1, 2, 4 and steps designated. 8 The outputs ^ ^ _A j ^^ _{if the} decision maker output AND elements ³² ^. ^b * ^ "" duder _a5-making cycle is completed. This signal can be used to OR gates 4C-0 to 40-9 with. ^^ "f ^" * ⁵ _{test? n} of the output lines 51-0 to 51-9 and the other which is applied to the line 44 _are connected to the associated binary counter ^ on Amang _{nd for e ung a} RücksteUsignals bewerden all binary counter 42 furuck ^it ß ™ * · ™ _uses the binary counter can pay to 15 ^Dc% ^ ^{n;?. sandwich} T _{so that the} binary counter 42 and the character register 50 received counting pulse represents all four stages of _zk , _k .

Binary counter back to 0 and ^ rd gk.churrently ^ over 30 S ^ ^ ^^ ^. _qp . _{& Χ} ^^^ a counter output line 43 to the handling β decision circuit 48 which _t by the corresponding register locations ^ '^ ^Z ™ e mark above-mentioned decision signal on the input transformer Thus occur for every ^a J ^ ^st £ ^e /; _ _{baskets circuit} 36 is turned on and a Entscheidungsal- binary counter 42 during passing through the Vorre s _urch. Their main function is to repentant ligand switching-on of the input ung ^ 33 35 g ^^^^ _{number of clock pulses, we} i _c e above certain period of time in Tatigk "t ^ una" n _at ^^^^ _{lfl the} "^^^ Ausgangsimpnlse of the mask circuits30 for ^ eüe ^^^, J ^^ _bjs ^ ₉ separated by theB inar counter42-0 character identity. The neiui ™ " _n - _{42 9 (F} j ^ ^ ₅ artificial counting impulses run to words that the binary counters« «" SSSSS ^ «o lass" This is done in the representation of FIG. 2, integrated over all suitable ^ fj ^ g ^, _{by as} ß clock pulses on line 16 either "..- !! s of Zeichcninfonnatioii in the Ma ^ Ληχ letern aND gate 60 or aND gate 61 * roofs represents the degree in which ^ each ^ emze ne OR element 62 with an output line 63, character mask 30 of the scanned Z? «* ^ ™ ¹¹ ^ ¹ ^ which leads to the mentioned OR elements 40. This M ^ PjJ ^ SSen are 45 directed The operation described below takes place when the output AND process «8 * 5 * ™ °". _d operation.

den and a decision cycle begmm mn oe ^ _{leading edge of a} decision pulse aul

Signal on line 36 to the decisions ^ Le ^ n ₂₃₆ switches a trigger 64 over a

services48. These circuits are more accurate mr g. _Capacitor ^ _um . The trigger was previously z. B.

shown. The binary counters 42 are soMngW, _{owing to} the last previous reset pulse!

their capacity "r ^C \ T _ra " tÄwäh "nd the line 44, which is via the OR gate 66 on the

Overflow signal on an ^A «p ⁿ f ^ ndera Therefore reset input of the trigger had been given

of a mask integration cycle has been deferred. When the trigger is switched

is no rosiuo ^ s. ^ _fc ^ ^. ^ _{output line 6} t at the beginning of the decision cycle

of the character register 50, but this , mm u _AND . _G lied60 in such a way that there is a number in front of it

ähd the decision cycle e "8g" * ¹ ^ ^M ^ d Ziil f dr line 16 practice,

of the character register 50 is set, _AND . _G lied60 in such a way that there is a number in front of it

only during the decision cycle e "8g" * ¹ ^ ^M ^ "following time impulses on the line 16 practice the final decision result aul uruna ^ ^^ described path at the same time as art

50 ^{Crm "orld} · _ΰο1ιε zähijmpuise derives SteUung the character register to all binary 42nd The voi The character register 50 comprises ten 8 "" ™ £ _{the AND} . _G lied 60 impulses let through!

register positions, of which each · ^ai »""" JstenSlen 60 also exists on the counting input 70 of a binary counter 7: memory 5 (M) to 50-9 designated vie isreiner recognizable character ident.ta w «gjg | ^ _{fen included} . oi ^ r counter was previously by de: Oblfimpuls aui oer _f A

is pure to be recognized character ident "gjg | ^ _{fen included} . oi ^ r counter was previously by de:

and is due to an overflow impulse aui oer ^^^ _{] fa on the Ldttmg} 44 _{on its} output

output line 43 has been reset by the ^z "^ Jl ° ^{rd e"} _"by position. The conduit 44 is ai

zähkr Employee All Registerst "" can en durw ^ _R ^e _äckste ".l _teucr circuit 76 for this binary

one in circuits not shown «^ ¹ ^ *? * ;. ^ he connected. It is assumed that dt

on a line 44 back! «^ gSS, initial setting of the counter is 0. The binary / counter T

lige switching status of the individual ^ «jSSS ^ hIt now counts impulses from the AND gate 60. Whom

manifested by a signal on the zugenong ^ ^ ^

9 10

the counter reading 12 is reached, the binary level 1 in the counter 92 is connected. Via the OR counter, a signal via an AND element 80, the one element 96 of which is the other two contacts, are also connected to the outputs of stages 4 and 8, this is connected to the reset inputs of stages 2 and 4 of the counter. The counter is connected via a line 81. When the two-position switch 95 signal from the AND gate 80 to the aforementioned S is in the position shown in the drawing, the OR gate 66 uiid is given to the trigger 64, so that a signal on the line 44 does not reach the resetting the AND gate 60 is more prepared and the input of each stage of the counter 92, and therefore 0 was first cut off for the counting pulses. Therefore selected as the starting position of the counter. If the binary counter 72 is not receiving any further switches in the other position, the counter counting pulses. The signal on the line 81 is io state value 1 as the starting position of the counter and also selects a delay element 82 on one. The two-position switch 95 can be given to the input of an AND element 84, whose input is connected to the machine console or the housing or, if necessary, its input to the line 55. It can also be attached to the control panel or the like, it has already been explained that the line 55 carries a signal to the beginning via the second path and the AND element 61 of the decision cycle, which guided artificial counting pulses continue to run until shows that no register position in the character register has been ORed by the binary counter 92 as a stop signal. If this signal is given during the over-link 97 and a line 98 to the inverter 90 carry the counting pulses over the mentioned first. Then the output signal disappears via the AND gate 60 has not disappeared, the inverter 90, and then the AND gate 61, the AND gate 84 is energized and delivers on a »0 no longer switched on, so that the second path is removed Line 85 a signal which is separated via an OR gate 86. The signal on line 98 also runs: the output line 58 continues. As already done to the OR gate 86, which says the end signal for the, a signal on the line 58 indicates that the decision cycle is on the line 58. The decision cycle has ended. A short delay produced by the V signal from the OR element 97 can be produced in various delay elements 88. When the binary counter 92 contains the required, as by the last, value 3 from the AND element, two inputs of an AND element 60 a character register 99 are switched on, which can be set with the outputs of the level 1 digit. The signal on line and 2 in counter 92 are connected. If the third, 55 disappears after a very short time before the signal connected to the fixed contact of a switch 100 on the line 81 reaches the AND element 84 30 input is already prepared, the AND element can deliver. Then the decision cycle cannot be terminated in the manner described, 99 when a signal is sent to the OR gate 97, and as a result. the cycle is ended. If the third input when the signal on the line 55 disappears, but is not prepared, the AND element 99 becomes non-conductive immediately after one of the counting pulses via the, so that the counter 92 on the value 4 first path and the AND element 60 has been passed, 35 must switch on, and as a result, the output of an inverter 88 delivers a signal on its output of stage 4, a signal directly to the OR line 89, which the trigger 64 via the OR gate 97. Depending on the The position of the two-digit element 66 resets so that the first path cut-off switch 95 supplies the binary counter 92 which is cut and the binary counter 78 cannot receive any further display 0 or 1 and runs depending on the position. (If the counter 78 40 of a switch 100 to the end display 3 or 4 has already reached the level 12, the trigger 64. The switch 100 is a three-position switch whose, according to the above description, is already connected to the switch-on voltage + V, by the pulse. reset on the line 81.) In addition, the cut-off voltage prepares - V and an output of the signal on the line 81, the AND gate 61 before, stage 8 of the binary counter 72 are connected. If the second input has already been activated by the decision switch 100 in the position shown in FIG. 2 is the position shown, the signal on the line 36 and its third input, the third input of the AND element 99 always passes through the signal from an inverter 90, a signal so that the counter 92 is stopped at level 3, which is present at the beginning. If, however, the switch 100 can be used for disconnection, the AND element 61 has now selected a number of Aufein- voltage, the third input is not consecutive time pulses on the line 16 prepared at 5 °, so that the counter 92 stopped at 4 the OR -Link 62 forward which this Im- will. In the third FaH, the final status of the pulse depends on the final status of the counter 72 as further counting pulses via the counter 92 line 63. If this second one is stopped at the same time to all binary counters 42, after it has reached the level 8 or train of artificial impulses is also on the one higher level, the third counter input 91 leads a binary counter 92 with three 1, 2 ss gear of the AND gate 99 via the switch 100 and 4 designated stages. This counter signal, so that the counter 92 stops at level 3, was previously set back by the last reset pulse prepared, control circuit 94 of this counter was given. so that the counter 92 stops at the final value 4. This reset control circuit 94 contains changeover switches 60, a third and final possibility for termination, and circuits which are connected in such a way that one of the decision cycles consists in connecting the number of possible reset states through either the line 57 to the OR gate 86. On Conflicting setting of the changeover switch a certain signal on the line 57 thus delivers a decision state is selected. In the example shown, the end signal on the line 58. This option includes the reset control circuit 94 a two-65 can be omitted, since the signal on the position switch 95, its fixed contact with the line 57 also to the output signals for the line 44 and the belongs to both other contacts with recent detection results, which are shown in FIG. 1 the reset input and the control input shown on the right.

The importance of the decision cycle is evident from the fact that during the mask integration cycle each of the binary counters 42 collects the sampling pulses from the associated character mask. The one in this The highest count obtained in the cycle provides recognition of the character being scanned, provided that this highest reading is not less than a preselected minimum reading and no counter reading for the others Counter is found within a preselected minimum distance from the highest reading. To meet the first condition, decision circuit 48 transmits a first train of artificial counting pulses, which ends when a first register digit of the character register has been set (line 53 in FIG. 1 corresponds to line 89 in FIG. 2) or when a predetermined number of artificial counts is reached has been. This predetermined number is kept equal to the overflow level of the counters 42 and less than the predetermined minimum level. In the exemplary embodiment, the minimum level can be 4 or 8. the The overflow level of the binary counter 42 is 16. The largest number of artificial counting pulses of the first train is equal to the difference and can therefore be between 12 and 8. The highest reading of the counter 72, with which the number of the first artificial counting impulses is monitored is 12, and the starting position of this counter can be selected with 0 or 4, so that between 12 and 8 first impulses are permitted are. Assuming that the preselected minimum level is S, those are not shown Switches in the reset control circuit 76 are set so that level 1 is set and levels 2, 4 and 8 are at Appearance of a reset pulse on line 44 can be reset. Then the binary counter 72 counts from 1 to a maximum of 12, i.e. a maximum of eleven first pulses. The maximum number of eleven first pulses results in one Overflow in one of the counters 42, e.g. B. 42-4, if this counter already has the required minimum level 5 exhibited. The register locations 50-4 of the character register 50 is then adjusted by the eleventh pulse, i.e. H. by the last possible impulse in the first row artificial counts. When the binary counter 42-4 has reached a higher level, the register location 50-4 of the character register becomes when one arrives earlier counting pulse of the first pulse train is set. In both cases the decision cycle is running by generating a subsequent second train of artificial counting pulses over the second path and the AND gate 61 in FIG. 2 next. If, however, the highest level of the binary counters42, e.g. the counter 42-4, was less than 5, the first train of eleven counts does not lead to an overflow, and the decision cycle is terminated by the signal from AND gate 80 via AND gate 84 and OR gate 86, and the error signal on the line 55 indicates the result. The reset control circuit 76 includes switches and circuitry and is similar designed like the reset control circuit 94 for the binary counter 92. The changeover switches in the circuit 76 enable the reset positions to be selected from 0 to 4.

If it has been determined that the highest count is at least equal to the preselected minimum, the second train of counting pulses is and counted in the counter 92. The number of these pulses should be equal to the preselected minimum distance being. The starting position of the counter 92 is 0 or 1, depending on the position of the two-position switch 95. The final score is 3 or 4 and depends on the position ment of switch 100 and possibly from the end stood the counter 72 off. If z. B. it is assumed that the specified minimum distance is 2, the switch 100 is in the position shown and the two-position switch 95 is thrown, then the

so starting position 1 and final position 3, so that two Pulses of the second pulse train are allowed to pass, which leads to an overflow in one of the binary counters 42, e.g. B. the counter 42-9, if its reading is 1 or 2 or less than the highest reading of the counter 42-4 was. This triggers a conflict signal on line 57. The number 2 in counter is 42-9 however, allowed if the highest number in the counter 42-4 is 5. Now there is enough difference as there 11 + 2 = 13 counting pulses the required overflow just miss the number in counter 42-9. When the min minimum distance z. B. is to be increased to 4, the two-position switch 95 remains in the position shown, and the switch 100 is switched to the middle position. The counter 98 then counts from 0 to 4.

The adaptability can be further increased in that the minimum distance is made dependent on the end display of the counter 78, if the switch 100 is in the third, upper position. When the switch 95 is in the position shown stands, the counter 92 counts from 0 to 3, if the level 8 of the counter 72 was set, i. H. if the counter 72, starting from the starting position 1, has counted at least seven impulses of the first move. This means that the highest reading of the counters 48 9 and the lowest S was. Up to a highest level including 9, a minimum distance of 3 is considered sufficient. With a maximum score of 10 and above this a more precise differentiation is desired, which can be achieved by the AND element 99, which was not switched on in this case, so that the counter 92 then counts to 4 If a highest] Stand from z. B. 11 occurs in the counters 42, isl a second highest level 6 is permissible, a 7 would already lead to a conflict signal. This example is summarized in the following table

Table I Switch 100 in the upper position

Minimum distance depending on final position 72 (starting position = 1) Starting position 92 0

Final score 72

Final score 92

Minimum distance Number of first impulses Highest score in 42 Admissible second highest level

2 until 7th 8th until 12th 2 until 7th 8th until 12th 4th 3 4th 3 4th 3 3 2 1 until 6th 7th until 11th 1 until 6th 7th until 11th 15th until 10 9 until 5 15th until 10 9 until 5 10 until 5 5 until 1 11th until 6th 6th until 2

Table I shows that after flipping the switches 95 and 76, the minimum distance exclusively through the Final reading of the counter 72 is determined. In addition, the table shows that a second-highest level 11 is allowed in the counters 48, provided that the highest level is 15. A valid recognition of the character for which 15 was counted is then despite an "incorrect" number 11 in one of the other counters. A much lower value, e.g. B. 5, for the The highest level also provides a valid recognition provided that the second highest level is correspondingly lower.

F i g. 3 schematically shows a matrix register with 17 rows and ten columns in four operating positions. At A, the stored information comprises a strongly divergent number of one-bits for the scanned character "4". For a lean character in which the proof was insufficient or the ink ribbon was almost used up, the line width in the matrix is only one register position. For a character in bold, which has been written with a large pressure or a fresh ribbon or a worn type, the line width in the matrix is three register positions. In the event of further deformations of the printed character, all kinds of variations in the bit density can occur at the individual register positions in the matrix. At B , the minimum and maximum sizes for a non-mutilated "9" are shown in a similar way. The same can be done for all other digits. It is very difficult to define a set of logical statements or character masks, through which a one-bit (black) in some register positions and an O-bit (white) in other register positions, so that at least the correct character mask is used for every deviation from the stored bit pattern responds once and all other character masks never. The further one wants to go in the recognition of deformed characters, all of which have to be recognized as the same character, the further the definition of characters has to be expanded and the sooner another, mutilated character will also generate a response to the same mask. If the requirement that no incorrect address should occur is dropped, the present invention can still validly recognize both light and bold characters as well as numerous deformations of these characters. The given requirement is replaced by the lighter requirement that incorrect statements, integrated over all possible register positions of the information in the matrix, must not become too numerous compared to the number of correct statements. This requirement makes it considerably easier to find a set of logical statements for the characters to be recognized. In addition, adaptability is significantly increased, as the term "not too numerous" can be defined differently depending on the circumstances. That described-

Bene embodiment of the invention enables this adaptability through the provided Options for a minimum distance and a minimum number.

A greatly simplified example should now show how a distinction is made in accordance with the amendment comes The F i g. 3C shows a character mask for the "9", FIG. 3D a mask for the "4". The latter Mask searches for a combination of information in the

ίο Matrix in which a one-bit determines three Register positions and an O-bit are in a fourth register position. The stored character information runs along this mask in the matrix, and the number of statements obtained can be found out manually by placing mask D on mask A and then moving it horizontally and vertically into all possible positions. From this it can be seen that a thinly printed "4" yields seven statements, corresponding to the register positions in which the outermost

“Ο the left single bit of mask D coincides with one of the black positions in the extreme left vertical column of the lightly printed“ 4 ”in mask A. The number of statements in the mask for the "4" in FIG. 3D when one appears

he bold »4«, a lightly printed »9« resp. a bold "9" was noted. The mask for the "9" in FIG. 3 C searches for a combination of at least four black bits in the matrix, where the Register positions of three of these bits are precisely defined

while the fourth bit can be in one of six register locations connected by a serpentine line. This mask provides z. B. six statements for the lightly printed "9", namely in the positions in which the leftmost one of the mask C is to coincides with one of the black register positions in the leftmost column of the lightly printed "9" in mask B. The results obtained are summarized in Table II.

Table II

Lean 4 Fat 4 .. Lean 9 Fat 9 ..

Mask for the "9" Mask for the "4"

O 6th 6th

14th O 4th

From Table II it can be seen that the highly simplified masks selected make a good distinction between the »4« and the »9« if only the lightly printed »4« or »9« appear. When a Minimum level 5 and a minimum distance of 4 required are changed, the leanly printed »4« is recognized there 7> 5, and the bold "4" is recognized because 14> 5 and 14 - 6 > 4 is.

1 sheet of drawings

Claims (5)

Claims: Years «has been on the market. This machine has a 1. Process for machine character recognition - additional mask switching on, with which in the Manung, in which information combinations arising from the scanning of characters are observed Signals are derived and respected in a memory that stores certain minimum requirements, shifted there in places and fill with 5. A mask removed from this additional circuit, each of which a given recognition impulse indicates that the Infor character is assigned, to be compared and at mation a new character affects This impulse is Correspondence of the memory content with one of the clock control circuit supplied with the ErMasken Detection signals are output, identification circuit is synchronized and the one thereby characterized that after io passages of the character register during one past each Shift a comparison of the storage correct time interval for further recognition pulses content with the masks takes place that the blocked by the mask circuit when over- The result of the Detection signals occurring in accordance with the detection cycle remain in the for some time every mask can be counted and the counter contents of the character register received, after which this is returned each scanned character is adjusted with one another only after a second, predetermined one has elapsed be like. Time interval, a new signal is sent from the additional 2. The method according to claim 1, characterized thereby assumed borrowed mask circuit. To this records that a scanned character is ensured in such a way that the deviation from Mask is assigned for which the number of He- predetermined Absland between successive identification signals a specifiable minimum number of characters only go up to a defined limit exceeds and by a predeterminable difference, so that characters printed too close to one another larger than the next smaller one of another mask can be rejected. assigned number of detection signals is further from the USA patent 3,165,717 a similar 3. The method according to claim 2, characterized by a character recognition system with a sliding character, that the difference by which the largest as register matrix is known, but with the sampled Number of detection signals from the next - data not continuously circulating through the matrix Number must differ, depending on. In this case the matrix is displayed in columns under the greatest number is variable. the control of a clock filled after first 4. The method as claimed in claim 2, characterized in that there is sufficient information about the presence draws that one has been found for the ambiguity of a sign. Since ensured identifier significant signal is output if it is that the scanned data is already horizontal Conditions for the difference are not tied for, the information in the matrix is only However, the minimum number is met. shifted vertically. In this known device 5. The method according to claim 2, characterized in that mask circuits are also designated for the characters, that one uses significant 35 for the unsuccessfulness. In Figs. 10 and 11 of the aforementioned t the signal is output if the condition for example is such a mask circuit shown The minimum number is not met. represents.