DE19525100A1 - On-board programming of EPROM memory in microprocessor system - has EPROM and RAM memories sharing identical address space with code entered into RAM and transferred in sequence of operations into EPROM - Google Patents

Abstract

The process provides on-board programming of an EPROM memory for program storage within a microprocessor system and this has hardware integrated separation relative to a read/write memory RAM used for data storage. The EPROM and the RAM have identical address regions distinguished by control signals. Programming is performed in a series of steps commencing with the code sequence being enter into RAM memory followed by selection of the programme mode. The EPROM is then selectively erased and the code sequence transferred followed by a return from the programming mode.

Description

The invention relates to a method for programming an electrical programmable read only memory, hereinafter referred to as EPROM, which in a microcomputer circuit as a program memory is physically integrated and remains in this microcomputer circuit during programming, whereby the Microprocessor-determining microprocessor an explicit, hardware Integrated separation between a read-write memory, hereinafter referred to as RAM designated, and the program memory and in the data memory and Program memory over identical address areas and only over own control signals can be addressed differently. Such microprocessors are for example known as INTEL 8051 or INTEL 8032 usually used for control purposes.

When updating the system software in facilities whose control with Such microprocessors is built, that is in the device EPROM physically against an EPROM containing the current system software exchanged. For this purpose, the device is to be dismantled, if necessary, that the EPROM is accessible. Especially in complex systems with a large number Such facilities, the updating of the system software is very complex and time consuming. In addition, at least part of the system is de-energized switch, with a process to be controlled by the system at least partially interrupt.

The invention is therefore based on the object of specifying a method which allowed an EPROM in a microcomputer circuit, in which the Microprocessor-determining microprocessor an explicit, hardware integrated separation between a program memory and a data memory has and identical in the data memory and program memory Cover over address ranges and differentiate only via control signals are to be programmed when installed.

According to the invention, this object is achieved with the means of claim 1. Advantageous embodiments of the invention are in claims 2 to 4 called.

The invention is explained in more detail below using an exemplary embodiment.

Reference is made to an INTEL 8032 microprocessor. The show the necessary drawings

Fig. 1 shows an address map of the microprocessor in normal operation

Fig. 2 shows an address map of the microprocessor in the "programming mode" mode.

The microprocessor has a 16-bit address bus and an 8-bit data bus and is able to manage two physically separate, directly addressable memory areas, each with a memory volume of 64 K * 8 bits, one of which is used as code area C in the address area 0000 to FFFF can only be selected for reading via a control signal PSEN and the other according to FIG. 1 can be selected as data area D in the address area 0000 to FFFF via control signals for reading RD and writing WR, all address information being noted in hexadecimal.

The code area C is physically represented by an EPROM as a code memory is designed as a so-called flash EPROM. The data area D is in the range of Addresses 0000 to 7FFF reserved for input / output lines I / O and in Address range 8000 to FFFF for temporary data storage with one  Data memory RAM, which is designed as a static data memory SRAM, fitted.

This configuration corresponds to that for the intended purpose Use proposed application and is hereinafter referred to as the mode of operation Denoted "normal operation".

In normal operation, the microprocessor carries code sequences which are in the EPROM of the Code area C are stored in the intended order. The address the currently executed code sequence in code area C is indicated by a Command pointer BZ, this is a register with the width of the address bus in the Microprocessor. In the data area D Input / output lines I / O operated read and write and data in Data memory RAM saved and read out.

For programming the EPROM code memory, in which the code memory In a first step, EPROMs that are to be accessed for writing are loadable Code sequences written from any source into the data memory RAM, where the operating mode normal mode is set. The code sequences for Execution of this step is stored in the EPROM code memory.

In a second step, instructions are changed from the program memory to a second operating mode, hereinafter referred to as the programming mode. For this, the code memory EPROM in the data area D of FIG. 2 remapped keeping the addresses 0000 through FFFF and the data memory RAM of the address range 8000 remapped to FFFF of the data area D in the address range 0000 to 7FFF the code area C. The input / output area I / O is hidden in programming mode and therefore cannot be addressed. Input / output procedures are prevented during programming. The value of the command counter BZ is retained. In programming mode, the data memory RAM is addressed as a code memory with the associated control signals and the EPROM code memory as a data memory with the control signals belonging to the processor on the data memory. The execution of instructions is continued at the address designated by the command counter in code area C, in which the RAM is now addressed.

In a third step, the EPROM is now operated as a data memory at least partially deleted. Known EPROMs are about to be overwritten information already stored, at least in the one to be overwritten Delete address area. As soon as EPROMs become available, their Memory cell contents are directly overwritable, the third and the following fourth step carried out simultaneously in which the loadable code sequences from the RAM in code area C in the EPROM in data area D starting with one specified start address can be copied.

Finally, in a fifth step, the program mode is switched back to normal operation by exchanging the control signals for the RAM data memory and the EPROM code memory, so that the initial state, whose address plan is shown in FIG. 1, is restored.

In processing the code sequences, at the address in the command counter, which now again points to a memory location in the EPROM code memory, continued.

For the complete exchange of those that can be stored in the EPROM code memory Code sequences are steps 1 through 5 depending on the size of the in repeats a code block transferable step cycle.

The EPROM code memory advantageously remains for the purpose of it Programming in the facility with it. This advantage comes especially for wearing in decentrally structured and hierarchically organized Control systems with a large number of so-called controllers are self-sufficient functional microcomputer units, in particular with microprocessors Families INTEL 8051 or INTEL 8032, when replacing the operating software. Here there is no need to at least partially switch off or interrupt the one to be controlled Process, because programming pauses between two consecutive, process-related activities of the microprocessor can be carried out.

In a further embodiment of the invention it is provided that for switching between a control signal is generated for the first and the second operating mode. This  Control signal is generated in processing a code sequence and via a Microprocessor pin output. Depending on the state of this Control signals are the access signals for the data memory RAM and Code memory EPROM interchanged and according to the respective memory type customized.

In a special embodiment, the control signal for changing the operating modes output through one of the input / output ports of the microprocessor, the is independent of the input / output area I / O in data area D.

In a particularly advantageous embodiment of the invention, the loadable Code sequences to be written in the code memory EPROM by an external data bus written into the data memory RAM. About this Data bus is a variety of controllers simultaneously with the current one Code sequences of the operating software can be supplied. In the time unit, the EPROM is required to program a code memory, all EPROM code memory of the selected controller programmed.

Claims (4)

1. Method for on-board programming of an electrically programmable read-only memory as a program memory with and for a microprocessor, which has an explicit, hardware-integrated separation between a data memory designed as a read-write memory and the program memory, with data memories and program memory paint over identical address areas and can only be addressed differentially using their own control signals, and the microprocessor is equipped with input / output connections in addition to data connections, address connections and control signal connections, characterized in that

• that in a first step in a first operating mode "normal operation" loadable code sequences are written from any source into the data memory,
• - That in a second step when executing instructions from the program memory, a change is made to a second operating mode "programming mode", in which the control signals for the data memory and for the program memory are temporarily exchanged while adapting to the memory type, so that the electrically programmable only Read memory becomes data memory and read-write memory becomes program memory,
• that the electrically programmable read-only memory is at least selectively erased in a third step,
• - That in a fourth step the loadable code sequences are copied from the read-write memory into the deleted area of the electrically programmable read-only memory and
• - That in a fifth step it is switched back from the second to the first operating mode by exchanging the control signals for the data memory and for the program memory.

2. The method according to claim 1 characterized, that to switch between the first and second modes Control signal is generated.   3. The method according to claim 2 characterized, that the control signal for changing the operating modes via one of the input / output connections is issued. 4. The method according to claim 1 characterized, that the loadable code sequences from an external data bus in the Data storage can be written.