DE1946337C - Circuit arrangement for an electronic binary counter for high number speeds - Google Patents

Description

The invention relates to aul! a circuit arrangement for an electronic binary counter for high counting speeds with η bistable register stages for counting 2 " counting pulses, which is equipped with a presetting network for controlling the bistable register stages. The network consists of input gate circuits to which the counting pulses are fed in parallel via a counting signal line and which are assigned to both inputs of each of the bistable register studs.

They are binary counters from a chain of unstable register levels known, in which after applying the Zähitaktes through chain transfer the result is formed will. They have the disadvantage that they take a time to set, which depends on the number of stages of the result is needed. This disadvantage will

as is known, solved by the fact that a presetting network is used to control the bistable register stages is used. So is z. B. from the German Auslegeschrift 1 205 147 a static counter for pre and down counting and optionally presetting any binary number and with means for converting into a decimal counter with or without decimal preset known for numbering forward and backward. This counting is done by counting signals and Counting aid sigilal of any form controlled, whereby the auxiliary counting signals offset in time with respect to the counting signals are binary counters with preset networks however, only allow high counting speeds if the setting process takes place in parallel and not in series. Presetting new movements with Time-parallel setting processes have the disadvantage that the circuit complexity per step · of depends on the number of stages, which means that these presetting networks are used for binary meters with a large number of stages become very extensive.

The invention is therefore based on the object of creating an electronic binary counter with a presetting network in which, for a given high counting speed, the management effort per stage is independent of the number of stages. This task is achieved according to the invention in that each register stage is assigned only one holding gate circuit, which logically links an output of a preceding register stage with an input of a subsequent register stage and is connected in series with the holding gate circuits of the adjacent register stage 11 so that the series circuit of the holding gate circuits is connected between an m-th and the (m- ^l ) th register stage is interrupted and a blocking line is connected to a hold signal output of the m-th holding gate switch, through which the input gate circuits of the higher register stages following the m-th register stage are connected in parallel this solution according to the invention is a surprisingly simple Schaltmaßnähme at the connection of the individual bistable register stages the maximum counting speed even with long counting chains independently of their number of steps. in addition, a binary counter erflndungsgemäßer also in integrated form a are usgeführt as are used in each stage is substantially the same logical elements.

A particularly advantageous development is achieved by a further blocking line connected to the hold signal output of the first hold gate circuit.

Ss aims, via which the input gate circuits of the second to the m-th register stage and the holding gate circuit of the m-th register stage are controlled in parallel. This measure serves to further increase the

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maximum counting speed and is special even with a smaller number of unstable levels already very effective because the entire KcI-i-.iilaufzeit of the holding gate circuits to the sum of the running times of only two logic elements \ ..- r shortened without the need for parallel presetting a special circuit effort is ui> li <v

Other developments of an essential circuit arrangement are identified in the sub-claims. _;

For a better understanding, the following examples of the invention are based on the 7-warnings «explained in more detail. It's time

i'ig. 1 e ■ schematic circuit diagram of an according to the invention n-stage, binary counter,

Fi g. 2 is a schematic circuit diagram of the first three '■; ifen this binary counter with an example. for the . . bypassing the bistable register stages,

[• "Fig. 3 shows a timing diagram to explain the V'K'itsweise of the internal payer.

l-'ig. 4 a tabular representation of the Arheits-ι . niches, i.e. the area in which individual re-.i-.ijr stages their condition in processing -. Change in pulse.

! i g. 5 eir Impiilsdiagrainni to explain the ! in terms of the chain running time.

1 i g. 6 another embodiment of an inven- ('. ings according to ßinürzähler and

F 'i g. 7 a preset network with which the meter If this binary counter is expanded so that it is suitable for counting down counting signals is.

In Fig. 1, an embodiment of the invention of a "-step binary counter is shown, which consists of a 2 'count register RK with bistable register stages RO to Rn and a presetting network LN , in which each bistable register stage RQ to Rn input gate circuits S and R are assigned, which are designed as NOR elements. For each bistable register stage RQ to Rn , a holding gate circuit K with NOR function is also provided in the presetting network LN , the complementary outputs of which are connected to one of the inputs of the associated input gate circuits 5 and R, respectively. The counting pulses ζ are fed in parallel to the other inputs T of the input gate circuits S. R via a counting signal line ZS.

To explain the basic mode of operation of the binary counter, the first three stages are shown again in FIG. 2; a possible embodiment of the bistable register stages is also shown. Each bistable register stage RQ to Rn consists of two identically constructed NOR elements A and ß, which are connected to one of the inputs of the other NOR element. Each NOR element A or B has an external set input SE with which each bistable register R 0 to R η can be set externally to an initial value of zero or to any other dual initial value of the binary counter. If, as is customary, an initial value of zero is defined for the binary counter so that the transverse output a _A in each bistable register stage then carries the logic "1" signal, that is, the first NOR elements A are in the set state, the second NOR elements are B. reset and at their outputs a _B there is a logic signal "0". This state is held in the first bistable register stage RO until the first counting pulse r. is fed to the input gate circuits R and S via the counting signal line ZS. The set state is maintained in that the output of the first NOR element A is connected to an input of the hold gate circuit K assigned to this stage via a delay element VZ . Each of the holding gate circuits K has two complementary outputs a _K and a _K , which are connected to an input of the input gate circuits R. or S ίο. If it is also determined that a counting event occurs when the state "0" prevails on the counting signal line ZS , then with the arrival of the first counting pulse ζ - as can be seen from FIG. 3 - the first input gate circuit R of the first stage RO of the binary counter, and a signal »1 κ occurs at its output a _K. A blocking condition is thus given for the first NOR element A of the first bistable register stage RO, and the signal state at its output a _x changes from “1” to “0”. The second Einyangstorschaltung S of the first stage RO ... Bi Nai / ählers is maintained even when the second arrival of the first counts in the blocked state. This is done via its second input, which is connected to the "5 an output" _K , the OR output, the stop gate switch " K ". Therefore, after switching over the first NOR element A, the second NOR element H is set from the state “0” to the state “1”. Higher bistable register levels do not change their signal state, since the holding gate circuits K do not change the signal state either. In order for this Signalzustar.d the first bistable register stage RO can be kept until the arrival of the next count signal, the associated Haltetorschaltung KO is turned on by a delay element VZ zwisehen the output a _A of the first NOR gate A of the register stage RO and the corresponding input e _Ä " whose Zei'verzo ^ erung is so great that the value at the input e _{Ki of} the first hold gate circuit KO during the duration of the counting pulse; is held.

After the counting pulse ζ has decayed, the state at the input ^ _{n of} the first holding gate circuit KO changes and now corresponds to the signal state at the output α _{Λ of} the NOR element A of the bistable register stage KO. Without influence on the signal state of the two NOR gates A and B thus also the signal state at the outputs of the first Haltetorschaltung KO, the first input gate R is blocked, while the second input gate S is prepared for switching upon arrival of the next count changes. With the second counting pulse ζ both of its inputs are in the "0" state and the input gate circuit S switches through. This means that a blocking condition is given for the second NOR element B and the signal state at output a ₀ changes from "1" to "0". Since the first input gate circuit R also remains blocked when the second counting pulse arrives, the first NOR element A of the bistable register stage RO can now switch through, and the signal state at its output a _{A changes} ? from »0« to - »l ·«.

However, the second bistable register stage R i is also set by the second counting pulse; derm with the change of the signal state M of the first hold gate circuit XO, the second gate switch / Cl ₁ that is assigned to the second RcgisterstuftfK Ϊ,

and the first input gate circuit K of this register stage is prepared. Thus, the same processes take place in the second register stage Rl with the second counting pulse as in the first register stage RO with the first counting pulse, while the state of all other register stages is maintained by the fact that the signal state of the third holding gate circuit K% does not change.

How the signal state of the individual register levels changes when processing counting pulses is shown schematically in FIG. 4 using the example of a five-stage register. It can be seen from this that only those positions in the register which are in a so-called work area, which is shown hatched, are changed during the subsequent counting pulse. In the direction of the higher register levels, this work area is limited by the first one of a preceding chain of zeros, and when the following counting pulse is processed, the zeros are reset to ones, while the one limiting the work area is converted into a zero. For this purpose, all holding gate circuits K, which are assigned to the register levels located in the work area, have to change their operating status before the arrival of the next counting pulse.

This is based on the in FIG. 5 illustrated pulse diagram explained in more detail. As already stated, after the processing of the first counting pulse ζ in the first bistable register stage R Q Her, the signal state at input e _{Ko of} the holding gate circuit KO assigned to it changes. Taking into account the gate delay time of the holding gate circuit KO, the signal state at the * one input e _{Kx 0 of} the holding gate circuit K 1, which is assigned to the second register level, changes accordingly with a slight delay.Because, however, with this first counting pulse ζ the state of the second register level R 1 is maintained, accordingly, the signal state at the second input e _{kit of} the holding gate circuit Kl is also retained. Only after the processing of the second counting signal does the second input e _{Klt of} the holding gate circuit Ki also change its signal state, and it is thus controlled through for a short time. This is due to the different runtimes that occur when setting and resetting a "1". While resetting a "1" within a register level only takes into account the runtimes of two logic elements, namely the first input gate circuit R and the associated first NOR element A, three logic elements are required to set a "1", the second input gate circuit S. , the second NOR gate B and the first NOR gate. In the series connection of the stop gate circuits K, a "0", which arises from a "1" first reset in the work area, starts to run to higher-value digits, followed by a "1", which arises from the "0" converted in the work area. This faulty through-connection of a holding gate circuit K must, however, until the arrival of the next counting pulse z, z. B. the third pulse, can be reversed so that the counter can work properly. In a similar way, the running time of holding gate circuits connected in series becomes noticeable when transferring positions when a chain of signal states "0" is to be converted into "1". This is because the "0" formed by the previous counting pulse at the least significant place must run over all holding gate circuits K so that the presetting network is prepared for the coming counting pulse. In any case, the running times generally add up if η is in the work area and is connected in series with stopping gate sound. If one denotes the transit time in a stopping gate sound K with t _K , the result is a total chain _{transit time / (;} = η · t _K. If one adds the transit time, ίο which results from the time between the arrival of the counting pulse and the reduction of the signal state » 1 «results in the holding gate circuit KO of the first register level - it is _{denoted by / sr} - the following general figure can be given:

t _r - t _si f η ■ t _K = f _s , f t _u .

This chain running time f _a can in principle

Do not switch off ao, because ultimately the value of the previous register level of the binary counter is coupled into each hold gate circuit got to; according to the invention, however, their disadvantageous effect on the maximum counting speed can be observed

* 5 Avoid with a simple switching measure. This is done, as can be seen from FIG. 1, that the series connection of the holding gate circuits K is separated between the fourth and fifth register stage R 3 or R 4 and instead A blocking line SP is connected via a blocking element H with an inverter function to the one holding signal output a _K , the NOR output or directly to the other complementary output of the fourth holding gate circuit K 3. Through the blocking line SP

each input of the input gate circuits S and R of the following register stages is connected in parallel and thus these input gate circuits are kept in their state until the signal state on the blocking line SP changes.

The mode of operation of this switching measure is based on FIG. 4 in the event of a job transfer explained in more detail. As can be seen from this, yO lines move to form the position carryover from higher value to lower value positions. Separates If you now open the series connection of the holding gate circuits between the fourth and fifth register level, the chain running time for the fifth to the «th register level begins as soon as the line Y 04 is created with the sixteenth counting pulse, .irst

so after a further sixteen counting events, the position must be carried over. By then, however, all holding gate circuits K up to the «th stage can be prepared, even with long chain running times. This may be explained by a small example.

ss tern. If a minimum pulse repetition time of the counting pulses is set at 100 ns, then the zero delay time from the fifth to the η-th register stage can be 16 · 100 ns = 1600 ns at a maximum. With a running time of 10 ns per holding gate circuit K could Then, during this time, prepare 160 holding gate circuits, which correspond to the number of register stages will.

In FIG. 6 shows a further embodiment of a binary counter according to the invention, ir

which the series connection of the holding gate circuits Λ between the inverted output a _{K of} the holding gate circuit K 1 and an input of the holding gate circuit K1 is interrupted. Instead, the second is "

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Output a _{K of} the holding gate circuit Λ'1, the output is well suited, so that even from the practical Aufmit NOR function, gltedesWl connected to the input of an inverter construction of a circuit arrangement according to the invention, the output of which to the blocking point for short running times in the logical line SPl is connected through which the holding links can be provided,
Gate circuits S and R of the next seven stages 5 Of course, other versions of the binary counter can also be controlled in parallel. For forms of a circuit arrangement according to the invention, the voltage shown in this exemplary embodiment is conceivable. So it is B. quite possible, instead of binary counters with a total of thirty steps, the delay elements shown are to use a further three blocking elements H2, H3 and H4 which are triggered by the takeover pulses derived from the corresponding blocking lines are closed. Via these blocking lines, which are connected to the corresponding inputs of the F i g. fi a are denoted schematically by SPn , Ialtorschaltunf ^ n will be delayed. In contrast to the embodiment shown, there is also a block of seven register stages controlled by their input gate circuits. 7 shows a presetting network that interrupts the 15 holding gate circuits between the first and, corresponding to the pre-second register stage shown in FIG. 6a. Is set up in lean-to-loan network. If this network is connected to the first in FIG. 1 shown embodiment with its outputs e ' _An and e _Bn to the corresponding example could then z. B. a further Sperrchenden inputs e e _B "of the bistable circuit Re- be provided _on or which is to the inverted of the binary counter shown in FIG. 6 ao output of the first Haltetorschaltung KO gisterstufen is turned on, and the outputs e _K are also included and to an additional inverted of the delay elements VZ with the inputs _{έ κ} input of the holding gate circuit K 3 is performed. The presetting network shown in FIG. 7 can be connected to the display in FIG. 1, then the entire arrangement is suitable for counting up and down counting, which is still effective chain running time. For this purpose, the gate delay times of the input gate circuits S and R are reduced from four to two. Of course, it would depend on the logic of the Auf-F ig. 6 shown arrangement for counting up structurally also possible, the second blocking,. Counting pulses z _v ül> er the counting signal line ZS and line on the one hand to the non-inverted output] | _; corresponding to the logic shown in FIG. 7 this holding gate circuit KO and on the other hand directly! see network counting pulses z _H to connect to the input of the blocking element H via the counting signal 30. f ^L line ZS ' for counting * in the reverse direction, this could also run the running time for the stop gate. Using the example of the circuit K 3 shown in FIGS. 6a and 6b. But this is made binary counter for counting in the forward and technically only makes sense if the Haltetor-backward direction is particularly apparent, KO circuit for a corresponding benefit off t that a device according to the invention is placed 35 fully to the inverting blocking member H | also to be kept effective for an implementation in an integrated construction. * ⁽

For this purpose 2 sheets of drawings

Claims (4)

Claims. 1. Circuit arrangement for an electronic binary counter for high counting speeds with η bistable Registersü'fen for counting 2 "counting pulses and with a presetting network for controlling these bistable register levels, in the input gate circuits, to which the _ ihlimpulse are fed in parallel via a counting signal line, to the inputs of each of the bistable register stages, characterized in that each register stage (A; B) is assigned only one holding gate circuit (Kn) which logically links an output of a preceding register stage with an input of a subsequent register stage and for this purpose with the holding gate circuits of the adjacent register stages in series is connected so that the series connection of the stop gate formwork between:?; «. an m-th and the (m ^l l) th register stage (/.B. R 3 and R 4) is interrupted and to a stop signal output (ä _K ) of the" i-th holding gate circuit (K 3) a blocking line (SP) is connected through which d ie the input gate circuits (S or R) of the higher register stages (R4 ... Rn) following the / η-th register stage are connected in parallel. 2. Circuit arrangement according to Claim 1, characterized in that, with a large number of bistable register stages, several blocking lines (SPn) are provided, with only a certain part of the higher register stages being controlled in parallel by a blocking line and each via an inverting blocking element (H \ to H 4) are connected in parallel to a holding signal output (α _Λ ·) of the m-th holding gate circuit (Km) . 3. Circuit arrangement according to claim I or 2, characterized by a further with the hold signal output of the first hold gate circuit connected blocking line via which the Input gate circuits of the second to m-th register levels and the holding gate circuit of the m-th register stage can be controlled in parallel. 4. Circuit arrangement according to one of claims 1 to 3 for upward and downward counting of counting pulses, characterized in that two similarly structured presetting networks (IN) each with a counting signal line (ZS or ZS ') are provided, of which the binary?: Ähier One of the counting pulses for the forward direction (z _v ) and the other counting pulses for the backward direction (z. _R ) are supplied so that the two networks are connected to the bistable register stages in such a way that the output of an input gate circuit of one network is connected to the one The input and output of the corresponding input gate circuit of the other network is connected to the other input of a register stage and that the two complementary outputs of this register stage are each assigned to an input of the corresponding holding gates of both networks. ,