DE1789137A1 - CIRCUIT CONSTRUCTED FROM UNIT CELLS - Google Patents

Description

66l9-ö8B / H / Lb

RCA 58 762

U.S. Ser.No. 648,449

Filed: June 23, 1967

RCA Corporation, New York, N.Y. (V.St.A.)

LSI housing made up of unit cells

The invention relates to a built up from unit cells LSI circuit (integrated large circuit).

The structure of electronic systems on the system and / or subsystem level has been subject to the advent of LSI circuit technology a radical change in terms of performance, reliability and constructive practice. With "LSI circuit technology" a circuit and manufacturing technique is meant in which more and more circuit elements in or on the same plate or substrate are attached, so that the functional electronic complexity of such an arrangement which approximates whole systems or subsystems, in contrast to more elementary functional units such as logical circuits or gates, amplifiers and the like.

The application of LSI circuit technology to digital systems like electronic computers, promises considerable improvements in operating speed. Let it be in this one Context noted that approximately $ 99 of the space or space in even densely packed computers that are not constructed using the LSI principle, as packing space and is used for interconnection purposes. The spatial separation between the individual components or building blocks of the computer means a serious limitation in terms of working

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speed. A significant improvement on this Problem is related to the application of LSI circuit technology, i. E. the integration of a large number of circuit components on a single substrate can be expected.

Another problem with conventional computers, i.e. not built according to LSI circuit technology, is that the electrical signals a large number of interfaces or edge areas between computer elements (e.g. terminal connections, Soldered or welded connections, wire loop connections and plug connections). Because of the human factor involved in making such compounds the reliability of these connections is limited. On the other hand, the LSI circuit technology enables series production Making circuit connections, which improves reliability accordingly.

The traditional dichotomy of the constructive tasks in digital systems between the designer of functional ones or circuit modules on the one hand and the system designer on the other hand it is modified by the LSI circuit technology, resulting in a new separation of the constructive tasks, namely between the series manufacturer on the one hand and both the module designer and the system designer on the other. The aim of the construction of LSI computer systems is to get by with as few LSI units as possible, preferably are all of the same type (in order to keep costs and the number of different parts as low as possible). To however achieving this goal must be done in an LSI unit if possible accommodate a lot of functional capacity. This requires optimal use of the LSI packaging space (i.e. the circuit area) in terms of both the layout of the circuit elements as well as the interconnection at system level. An optimal use of the circuit area (and thus an optimal functional Capacity of the LSI unit) can only be achieved through intensive cooperation between the series manufacturer, the

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reach the expensive and the system designer.

The best possible use of the LSI circuit area is guaranteed by the made-to-measure method (custom method), whereby the individual puncture or system constructions both with regard to the design of the circuit elements as well as with regard to of the metallic circuit connections in each case "after Measure ", i.e. designed according to the respective circuit requirements. However, this assumes that for every new functional or system design a new set of fabrication masks must be designed and manufactured. Currently the cost of a new set of fabrication masks for each new LSI unit is so high that it is only necessary for large orders, however, are not acceptable for small or individual orders.

Another possibility for coping with the structural tasks of LSI circuit technology is the so-called standard template method (Master slice method). The costs of the fabrication masks are distributed among the various functional or system designs, with the exception of those for metallization, i.e. mask or masks used in the last step of the manufacturing process. In other words, given the interpretation, the Circuit elements the same standard template fabrication masks for each functional design such as diffusion and isolation masks, while used for any new or different design other metallization masks are required. So the design of the circuit components is fixed and only that Metallization patterns are made to measure for each new application. The success of this constructive method depends on it whether with a given design of the circuit elements a reasonable number of different application possibilities can be achieved with sufficient functional complexity or versatility. It is therefore important that the circuit elements be designed in such a way that not only the available circuit or sub-surface area is used as well as possible, but also the whole arrangement with regard to the possibility of realizing

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different punctures through appropriate interconnection is designed to be sufficiently flexible.

In the standard template method, the circuit elements are generally designed or organized in such a way that one Arrangement of essentially identical circuit cells (which can be designed in standard design) results. These cells can be seen as building blocks with a fixed or changeable functional identity. A cell with a solid identity can be a NOR gate, for example, with each new application by correspondingly different interconnection of the gates in the Arrangement results. Such an arrangement with cells with a fixed identity may not be satisfactory, since in their constructive Flexibility is limited and the use of the substrate surface is inadequate. Then there is the constructive flexibility limited by the fact that only NOR gates can be used to fulfill the system functions in this case. Another shortcoming is that in many cases not all of the inputs of a gate are used, so that those of unused gate input elements unnecessarily is wasted. In addition, certain circuit functions, for example tactile flip-flops, do not realize.

In contrast, the identity-changeable cell offers one Flexibility in terms of specifying the functional identity of a cell, a group of cells, the parts of a cell and various combinations of these elements that the functional complexity of the entire arrangement is greatly increased. However, it is extremely important that a cell is available in which the substrate area is well used and which is sufficient allows versatile use with sufficient functional complexity that its cost is justified.

The invention, in one of its aspects, therefore relates to an arrangement of mounting brackets attached to a substrate

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cells in a coordinate matrix of rows and columns are designed. Each of these cells can have a number of semiconductor regions a first conductivity type contained in a surface of the substrate made of semiconductor material aes other Conduction type are diffused. The neighboring Rows of the matrix are spaced from one another so that runway surfaces or aisles or corridors are formed between them will. A multilayer conductor arrangement attached to the substrate contains a first conductor layer, which is a second conductor layer is superimposed and separated from this by an insulating layer.

According to one embodiment of the invention, the cell arrangement includes a feed line which is at least partially contained in the first conductor layer and is arranged so that it follows the corridors of the arrangement in serpentine turns.

According to a further embodiment of the invention is a Arrangement of the type described above is provided, in which in the first substrate surface at least one area made of material of the first line type is formed under one of the corridors in order to realize the crossings of conductors. This "at least An "area is therefore used for selective connection to conductors running along the corridor in question through appropriate access openings in the insulating layer (which are known per se).

According to another aspect of the invention, which relates to a LSI arrangement of cells sharing a common substrate. pulls, each cell contains at least three grid-insulated field effect components each with a grid area, which is formed by a current-carrying area formed by a source area and a drainage area Channel is isolated. The first of the components has one relatively large transconductance (transmission conductance) gm, so that it is suitable, for example, for use as an inverter in digital cell applications. The second component has

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a relatively small transconductance gm, so that it is suitable as a load for the inverter elements. The third component has a transconductance gm of medium value, so that it turns out to be Transmission or coupling element in both dynamic and static logic applications.

In the drawings, in which like parts have the same reference numerals are labeled, show:

1 shows the circuit diagram of the standard or unit cell according to the invention using conventional circuit symbols;

FIG. 2 shows the circuit diagram of the unit cell according to FIG. 1 at ' Interconnection as an inverter;

3 shows the circuit diagram of the unit cell according to FIG Interconnection as a two-input logic gate;

4 shows the circuit diagram of a one-bit delay stage of a dynamic shift register;

5 is a timing diagram for the shift register according to FIG

Fig. 4;

6 shows the block diagram of the cladding according to the invention pattern of the LSI array;

FIG. 7 shows a plan view of four cells of the LSI arrangement according to FIG. 6, illustrating the one according to the invention Unit cell;

8 shows a section along the line MM ¹ in FIG. 7;

Figure 9 is a circuit diagram illustrating the derivation path in a dynamic logic arrangement;

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Pig. 10 shows the block diagram of a dynamic logic arrangement according to a further aspect of the invention; and

Figure 11 is a timing diagram for the dynamic logic arrangement according to Fig. 10.

The invention can be used with grid-insulated field effect components any conduction type sharing a common substrate made of a suitable material such as glass, sapphire, semiconductor material and the like. Share, realize. In the present case, for example Grid-insulated field-effect components of the metal-oxide-semiconductor type (MOS) of the p-conductivity type (p-MOS components) used. The semiconductor material can be any of those materials that are generally used for the manufacture of lattice-insulated Field effect components used in semiconductor technology are used. In the present case, for example, it is assumed that that all semiconductor materials, unless otherwise indicated, consist of silicon.

1 shows the circuit diagram of the standard or unit cell 50 according to the invention using conventional circuit symbols. The unit cell $ 0 contains two p-MOS components 20 and 21, which are suitable as inverter elements due to their relatively large transconductance (gm). Furthermore, the cell 50 contains a third p-rMOS component 22 with a relatively small transconductance (gm). The p-MOS device 22 can be used as a load element for the inverter elements 20 and 21. The fourth p-MOS component 22, which has a transconductance (gm) of average value, can serve as a transmission or coupling element in both dynamic and static logic applications.

Each of the p-MOS components has a channel or conduction path, the one at its ends by a source area and a drainage area (for building elements 20, 21 and 22 by appending lower case letters s and d respectively) is limited. For example, has

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the p-MOS component 22 has a source area 20s and a drain area 20d, these designations being based on the normal application of the components 20, 21 and 22, but the designations for source and drain, depending on whether the component works as a source follower or in source circuit, are interchangeable . Since the p-MOS device 22 is normally used as a transmission gate, the source area and the drain area are designated by reference numerals 26 and 27 in FIG. In addition, each p-MOS component has a grid area. which is superimposed on the channel in question and isolated from it by a relatively thin insulating layer. The grid area is indicated by the appended lower case letter g . For example, the grid area of the p-MQS component 20 is designated by 20g. .

The unit cell 30 has two unconditional functional contact points 24 and 25. The contact point 24 represents an unconditional or permanent connection of the source regions 20s and 21s. The contact 25 represents an unconditional or permanent connection of the source region 22s and the source drainage region 26 of the p-MOS Component 23.

Furthermore, a number of conditional or optional contact points 1-12 are provided. The conditional contacts 2 and 9 are assigned to the unconditional contacts 24 and 25 , respectively. The conditional contacts 4 and 5 are assigned to the drainage areas 20d and 21d , respectively. The conditional contact 8 is assigned to the source drainage area 27 of the p-MOS device 22. The conditional contacts 1,2,6 and 7 are assigned to the grid areas 20g, 21g, 22g or 22g. The remaining conditional contacts 10, 11, 12 and 12 are used to connect the cell 50 to various feed lines. For example , the contacts 12 and 12 are used for connection to ground Grd or to the power supply Vdd, while the contacts 10 and 11 are used for connection to two clock signal lines 01 and 02, respectively.

Another permanent or unconditional functional connection

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28 connects the drainage area 22d to the feed line labeled Vdd.

The unit cell 50 is suitable for use as a mutable identity Module in an LSI arrangement for the implementation of desired digital systems such as adders, shift registers, Counters and other logic switching systems. In order to realize a desired system, the designer of the unit cell, one Group of unit cells, parts of unit cells or any Combinations of these elements create a functional identity by having the electrical or functional connections of the conditional or optional contacts 1-12 specified. In Fig. 2, j5 and 4 are some examples of functional identities that the unit cell or a plurality of unit cells or parts thereof can be issued, illustrated, wherein the supply voltage for the p-MOS circuits is denoted by -Vdd.

By using the inverter element 20 in conjunction with the load element 22, the unit cell can be given the identity of an inverter. This is illustrated in FIG. 2 for static logic applications in that the line J> 0 connects the conditional contacts Jf and 12, the line J) I connects the contacts 4 and 9 and the line J> 2. contacts 6 and 10 connects. The function table in FIG. 2 shows the function of the circuit with the input signal A supplied to contact 1 and output signal Cs taken from either contact 4 or contact 9. Namely, when the input signal A is at the high level (H), the output signal Cs is at the low level (L). For example, the level L can correspond to the potential -Vdd and the level H can correspond to the potential Grd. Conversely, when input A is low (L), output Cs is high (H). For static logic applications, line 01 is connected to a static DC voltage, such as either line -Vdd or some other suitable negative voltage. The p-MOS components 21 and not used in this case

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23 can be used in conjunction with other unit cells of the arrangement advertise used for the implementation of other functions.

For dynamic logic applications, contacts 6 and 7 are connected by means of a further line J $. The clock signal line 01 is now fed with a clock signal instead of a static DC voltage, and the output signal can be tapped either from contact 8 or from contact 9 *, depending on whether component 23 is used. In this case too, the arrangement fulfills the function of an inverter.

3 shows a further exemplary functional identity for the unit cell, which in this case is designed as a two-input logic gate. As in FIG. 2, the load and transmission elements 22 and 23 are connected by lines 32 and 33. The line 31 now has an additional or auxiliary line y * r in order to also connect the contact 3 to the contact 9. Again, line 30 connects contacts 3 and 12. Again, for static logic applications, line 01 is connected to a static DC voltage, which may be either Vdd or some other suitable voltage. The input signals A and B are fed to contacts 1 and 2 and the static output signal Cs is taken from contact 9. The function table attached to FIG. 3 shows the circuit function. Namely, when either input signal A or B is low (L), output signal Cs is high (H). On the other hand, when both input signals A and B are high (H), the output signal Cs is low (L). Further, when both inputs A and B are low (L), the output signal Cs is high (H). If the binary quantities 1 and 0 are assigned to the levels H and L, the circuit fulfills the function of a NAND gate. Conversely, if, conversely, the binary quantities 1 and 0 are assigned to the levels L and H, the circuit fulfills the function of a NOR gate.

The conditional contacts 6 and 7 can both be connected to either the line 01 or the line 02 or separately to these two

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BATH

Lines are connected. Furthermore, the line 33 is unnecessary, when device 23 is not to be used, as in most static and some dynamic logic applications the case is. For a typical dynamic logic application where device 23 is used, one can either use the output signal Cd or the output signal Cs.

To fulfill dynamic logic functions with the unit cell multiphase clocking is used for the load elements and the transmission elements in order to control the flow of information and at the same time the grid capacitance of a downstream p-MOS component to be used for purposes of temporary storage in a manner yet to be described. Especially for dynamic logic applications the MOS devices are often the most suitable. The circuits are because of the high input resistance of the MOS components simple. Furthermore, energy or power is only consumed when the clock signal is present, so that the Power consumption is lower than with similar static Logic applications.

The bilateral current conduction properties of the MOS components, ie their ability to conduct the current in both directions, and in particular of the transmission gate element 23, make it possible that the grid capacitance of the next logic function can be either charged or discharged. A one-bit delay stage of a dynamic shift register can be implemented with the aid of two inverters, two coupling elements and two clock generators. Such a one-bit stage of a dynamic shift register with two standard cells 50a and 50b is shown in FIG. The unit cell 50a is connected as an inverter in the same manner as the inverter of FIG. Likewise, the unit cell 50b is similarly connected as an inverter, with the exception of the fact that the line 32 is omitted and a line 35 connects the contacts 7 and 11. In this way, the inverter of cell 50a with clock phase 01 and the inverter of cell 50b with clock phase 02.

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be controlled. The grid capacitance C-20b represents the. Grid capacitance of the p-MOS component 20b in the cell 30b, while the capacitance C-20c represents the grid capacitance of the next following level (not shown). The output terminal Cd of cell 50a is connected to input terminal 1 of cell 50b .

Fig. 5 gives the timing diagram for the dynamic shift register again. In order to ensure a perfect flow of information, the two clock phases never have the same time the L level (-Vdd). The capacity storage time must also be used greater than the time interval between the trailing edges of 01 and 02 or vice versa, whichever is largest. The small steps in the signals run Xn + 1/2 'and Xn + 1 are generated by capacitive coupling in the transmission gate elements 2j3a and 2 ^ b when the clock pulse jumps back on generates the Η level.

The mode of operation is as follows: The one that switches to the L level Clock signal 01 switches components 22a and 2 ^ a a. When Xn has the L level, the grid capacitance C-20b is charged to the H level (Grd) via the components 2 ^ a and 20a or, if Xn has the Η level, via the components 22a and 2 ^ a discharged to the L level. The clock signal 01 switches to the H level back and turns off the p-MOS devices 22a and 2jYes. The information remains stored in the capacity C-20b.

The clock signal 02 changes to the L level and switches on the components 22b and 2 ^ b. The inverse or the complement of the information stored in the grid capacitance C-20b is transmitted to the grid capacitance C-20c via the transmission component 2j5b. The clock signal 02 returns to the H level and switches the components 22b. and 2j5b. The information stored in the capacitor C-20c is transmitted when the clock signal 01 changes back to the L level, during a full period of a clock pulse 01 and a subsequent clock pulse

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02 , the information Xn migrates or flows with a delay of one bit interval from the input of the component 20a of the cell 50a to the grid capacitance C-20c of the next following stage.

The functional identities of the unit cell illustrated in FIGS. 2-5 are only given here by way of example, and other identities can also be assigned to the cells. For example, the standard cell can be used for circuits realize which fulfill the EXCLUSIVE-OR function or the EXCLUSIVE-OR function. Other realizable circuit functions include set-reset type flip-flops and tactile flip-flops. Except for such digital circuit functions the unit cell can also be used to implement a linear amplifier.

In Figs. 6, Y and 8, the LSI arrangement in which the unit cell can be used is shown. Fig. 8 shows an arrangement of four of the unit cells shown in Fig. 6 and serves MOS p-assembly ^to illustrate and the metallization for the two catchy logic gate of FIG. 2. In FIG. 1, the unit cells of the LSI array are laid out in coordinate lines and columns. Each of the unit cells has the number 50 as the first component of its reference number. The second part of the reference number denotes the location of the respective cell in the matrix. The number in the first position indicates the relevant line, while the number in the second position indicates the relevant column. For example, the unit cell in the bottom row and the leftmost column is denoted by 50-61, the number 6 denoting the sixth row and the number 1 denoting the leftmost column.

In a certain cell arrangement, one or more spaces can be left that are too small to be a unity!> (). These practiced spaces can be executed with special foci and in fms. ^ use the LiJ £ arrangement Holcho anderson! '«- LLerx, boiiipU.'LüweLse ULu ' ZuIlan ^u jl, IUl, i> j and

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5 ^. These cells can, for example, have two inverter elements and a load element for interconnection as a two-input log gate contain. . · ·

Above the first or top cell line is a lane or corridor 70-1 · Further such corridors 70-2 to 70-7 are between the different lines and below the last or bottom line. On the corridor areas 70-2, 70-4 and 70-6 is a detailing pattern of. Attached feed lines, which are serpentine-shaped or S-shaped through the coordinate arrangement, so datf all Cells are common. These feed lines include a Vdd line, a Grd line, and an O2 clock signal line

, en

and two 01 clock signal lines. The 01 clock signal line 'are for reasons to be explained later in connection with FIG. 7 ' each arranged on or next to a different row of cells. Corridors 70-1, 70-3, 70-5, and 70-7 are generally for purposes the interconnection of the various unit cells 50.

In a row at the upper edge of the cell arrangement and in a row at the lower edge of the arrangement, a number of contact areas 60 are provided for the edge or external interconnection between the LSI arrangement and other components. Although the contacts 60 can either be diffused or designed as metal webs, they are preferably made of metallic material for the p-MOS arrangement. Some of the contacts 60 can be used as input / output terminals of the arrangement, while others serve to supply the various supply and control voltages to the arrangement. For this purpose, the 01-Taktsignaileitungen are respectively connected to the designated contact plate 01 during the 02-clock signal line connected to the ujt bezeichnete- with 02 contact pads. Correspondingly, the Vdd line is connected to the nut Vdd imU, the irrd line to dar, with ürd denoted Koataktplätbchen.

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BATH ORIGINAL

Under each of the corridors are a number of spaced apart diffused areas. As in detail will be explained, some of these areas under Corridors 70-2, 70-4 and 70-6 serve the dual role of sources or Drainage area in a cell and a diffused connection to the manifold assembly. Others of the diffused Areas, designated 48, pass under the various corridors at a distance from one another, so that ladder crossings are formed will. The access openings to the different diffused areas are arranged in a standstill of one another so that the overlying metallic conductors between them in desired Arrangements can be made.

The serpentine or S-shaped busbar arrangement for the LSI circuit is an important feature of the invention, by making metallic interconnections between the cells of any Row and various of the other rows allows - so that the higher resistance and the larger capacitance are more diffused Ladder areas are avoided. For example, the cells in the first row can match the cells in the fourth and of the fifth row are connected by only metallic conductors, while the cells of the second row are connected to the cells of the third and sixth rows can be connected by only metallic conductors.

Figures 7 and 8 show structural details of both the p-MOS unit cells and the overall arrangement. FIG. 7 shows a plan view of a four-cell group corresponding to cells 50-13, 50-14, 50-23 and 50-24 of the LSI arrangement according to FIG. 6. Cell 50-12, whose reference numerals are those of the unit cell circuit diagram according to FIG . 1 is initially based on the Big. 6, Qie shows a section along the line MM ¹ in FIG.

The p-MOS unit cells 50-13 and the entire LSI arrangement are mounted on an n-type semiconductor substrate 40

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3 0 9 8 1 8/0 9 2 2

(Fig. 8). By a number of spaced p-regions which are diffused into one surface of the substrate 40 the p-MOS components as well as p-connecting conductors (p-tunnel connections) educated. For example, in Fig. 8, "form diffused p-regions 20d and 21d the drainage areas of the p-MOS components 20 and 21, while the p-area 24 is a common source area for the p-MOS components 20 and 21 and an unconditional or permanent electrical connection of this area forms. The space between the p-regions 20d and 24 as well as the intermediate space The channels or conduction paths of the p-MOS components 20 and 21 form between the p-regions 21d and 24.

A relatively thick (e.g. 15000 8) insulating layer 4l, e.g. of silicon oxide, is located over the diffused surface area of the substrate 40. In the oxide layer 41 are a number of access holes or penetrations are provided, which the channels of the components as well as a part or parts of the various diffused p-regions. In the case of the unit cell 50-1J5, these access openings form those in FIG. 1 Optional or conditional connection points or contacts shown, so that they are designated with the same reference numerals. In the p-MOS devices 20 and 21, the access openings are 4 and 5 arranged above the drainage areas 2Od and 21d, respectively, so that they expose part of these areas. The access openings 1 and 2 are located above the channels of the two components. Inside the openings 1 and 2 ″ above the substrate 40 there are relatively thin (e.g. 1008) layers 42 made of oxide, which form the grid regions 20g and 21g.

The other p-MOS components 22 and 23 are similar Manner in the n-type substrate 40. These two components share a common p-region 25 which corresponds to the unconditional or fixed connection in FIG.

When the unit cell is built in the LSI array, the effective mobility or mobility yu the, charge carriers that

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Dielectric constant £ of the grid transformer and the thickness T of the grid insulator is the same for all p-MOS elements, so that the transconductance gm for each p-MOS element is equal to the width divided by the length (γ) of the channel in question. In Fig. 7, these dimensions 1 and w are common to each p-MOS element are defined accordingly, for example for the channel p-MOS component 20 specified. The length 1 is the distance between the p-conducting drainage and source areas 20d and 24, while the width w is the dimension across or perpendicular to the length. These channel dimensions w and 1 and consequently the transconductance gm of the individual p-MOS components are through the diffusion mask used during the production of the arrangement intended for the p regions. In this way, the Transconductances gm of the p-MOS inverter elements 20 and 21 in that that one makes w large and 1 small made large, while the transconductance gm of the p-MOS load element 22 by making the channel dimensions 1 and w makes relatively larger and smaller, respectively, is made small.

Corridor 70-2 between cells 50-13 and 50-14 of the first row and cells 50-22 and 50-24 of the second row provides access to the individual cells from the various feeders 01, 02, Vdd and Grd, which overlay the thick oxide layer and run along the corridor. These conductors generally consist of metal, for example aluminum. The conductors Vdd, Grd and 02 are introduced into the individual cells by contacting the underlying diffused p-regions through the access openings and thus crossover connections. form. Thus, the Vdd line contacts the p-region 28 via the access opening 28, the Grd-line the p-Geblet 46 via the access opening 44 and the O2-line the p-area 47 via the access opening 45. In the drawing, the access openings are 43, 44 and 45 shown hatched to indicate a one-way connection or an electrical connection. The p-regions 28, 46 and 47 run under the corridor 70-2 and are common to the unit cells 50-13 and 50-23. So it has that in every cell

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p-MOS component 22 portion of the common p-region 28.

Every cell has access to the 01 line, there is one on every cell 01 line passes by. The topmost one runs in FIG. 6 01 line is adjacent to the cells of the first row, while the bottom 01 line is adjacent to the cells of the second row runs. The 01 lines can therefore be connected to the desired access opening of a cell without using appropriate metallization Use of diffused p-regions can be connected.

The other p-regions 48, which run under the corridor 70-2, cross the feeder conductors to the cells of the first Row with the cells of the second row to connect to functional systems. As can be seen in Figure 6, these are additional p-areas 48 at various points along corridors 70-2, 70-4 and 70-6 as well as in a certain distribution length of the corridors 70-1, 70-3, 70-5 and 70-7.

Cell 50-14 of the first cell in FIG. 7 has an exemplary metallization pattern for the two-input logic gate according to Fig. 3 · The metallic shown by solid lines Connecting conductors have the same reference numerals as in FIG. 2, so that a further description is unnecessary.

The LSI circuitry may be any suitable Process are produced. In a typical process, only four fabrication masks are used. The first mask is used for diffusing the p-regions into the η-conductive substrate. A relatively thick oxide layer is then applied to the substrate surface containing the diffused p-regions. Then the openings are formed by means of the second mask by etching away the oxide, which the p-regions and the grating regions uncover. The arrangement is then coated with a thin oxide coating. The thin oxide layer is created using the third mask etched away in the p-region access openings. Finally, using the fourth mask, the grid source and drainage

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metallizations and the metallization connections of the p-MOS elements and p-crossing regions are formed. Any number of masks can be used for the metallization step will. For example, critical interconnections such as source, Drain and grid contacts as well as fixed metal connections produced by means of a first fixed metallization mask will.

According to a further aspect of the invention, the lower limits of the clock generator frequency range are extended for dynamic logic applications. FIG. 9 shows the basic circuit diagram of a MOS arrangement for dynamic logic applications. The information labeled INFO is fed to the source or drain 27 of a transmission gate element 23. The clock signal 01 switches on the transmission gate 23 so that the INFO is channeled to a p-MOS inverter element 20. During the time intervals of the absence of the clock signal 01 , the INFO is stored in the grid capacitance C-20 of the grid 20g. The storage time constant in a p-MOS LSI arrangement is a function of the derivative of the pn junction between the source / drain region 28 of the component 23 and the η substrate. This derivation is indicated by the resistance R between source / drain 28 and ground. In general, the larger the area of the pn junction, the smaller the resistance R and the shorter the storage time constant. Therefore, all connections between the output of a transmission gate element and the grid of an inverter element are preferably implemented by a metallic conductor instead of a diffused area.

However, with an LSI arrangement, it is not always possible to Use metallic conductor connections as crossover connections may be required. That in Fig. 10 and in the timing diagram The feature of the invention illustrated in FIG. 11 extends the lower clock frequency limit by adding Levels of the first clock phase to levels of the second clock

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phase purely metallic connections are used, while diffused connections, where necessary, are only used by stages of the second clock phase after steps of the first clock phase. In addition, the time between the end of the second clock phase and the end of the first clock phase is minimized. As shown in FIGS. 10 and 11, for example, the outputs of the stages 80 of the clock generator phase $ 1 are connected via metal connections 81 to the inputs of the stages 82 of the clock generator phase 02 , while the outputs of the 02 stages 82 are connected to the inputs of the 01 stages 80 via diffused areas are connected.

In Fig. 11, the time Ta between the end of the 02 clock pulse and the end of the 01 clock pulse is minimized in accordance with the storage time constant of the grid capacitance C-20. where the bleeder resistor R is a compound with a diffused region. On the other hand, the time Tb between the end of the 01 clock pulse and the end of the 02 clock pulse can be relatively longer (because of the higher leakage resistance). DdLe metal connections 8l (low discharge points) therefore essentially determine the minimum clock frequency. ,

While the invention has been explained above with reference to the use of unit cells of only one type in the LSI arrangement the arrangement can also use other types of standard cells contain. For example, the arrangement may have some rows of unit cells of the type shown in Fig. 1 and other rows with others Unit cells included.

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Claims (1)

6619-68B / H / Lb - 17 ft Q1 7 7 RCA 58 762 UJ I / öS IJ / U.S.Ser.No. 648.449 " Filed: June 23, 1967 PATENT CLAIM LSI circuit made up of unit cells sharing a common substrate, each cell containing at least three field effect components with a control electrode which is isolated from a current channel delimited by a source area and a drainage area, characterized in that the transconductance (gm) of the first component ( 20, 21) is significantly greater and the transconductance of the second component (22) is significantly smaller than the transconductance of the third component (2J>), which has an average value. 30981 8/0922