DE1773993A1 - Electrographic writer - Google Patents

Description

DR. CLAUS REINLÄNDER WPL-ING. KLAUS BERNHARDT _{Ui Ό1 Q1 π}

D-8 MONKS 4C ^{V1 1} ^ ^{1 Ώ} BÄCKERSTRASSE 3

VARIAN ASSOCIATES Palo Alto / California, USA

Electrographic writer

Priority: August 21, 1967 - United States 3rd No. 661.872

Summary:

An electrographic recorder is described which operates with a series of writing electrodes arranged across an electrographic recording strip are. The recorder has an input channel with an analog-digital converter, with the analog input signals can be converted into binary-decimal-coded output data. The output signals become two decade decode logic circuits supplied, each of which supplies decimal output signals on ten lines, which a decoding

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matrix, which decodes the decimal outputs ao appearing on ten lines, da3 output signals 100 lines are generated to control a series of 100 electrodes with which the input signal on the electrographic Strip is recorded. The decoding matrix contains a series connection of two / one high-voltage satter transistors. 100 first gate transistors are provided, one transistor for each electrode of the row of wheels. The control electrodes for the first gate transistors are combined in groups of ten, with every tenth transistor belongs to a group, and these transistors are connected to one of the output signals on one of the ten lines of the decoder of the first decade. 7Js are also ten second gate transistors are provided which are connected in series with the first transistors, ^ one transistor connected in series with each group of ten first transistor gates. The second gate transistors are of the output signals of the decoder for controlled the second decade. The two gate transistors connected in series form a decoding matrix with which the relatively high electrostatic writing voltage is applied to the driven writing electrode to generate the input signal reproduce on the recording medium.

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ORIGINAL BATHROOM State of the art;

Electrographic pens have been proposed which employ a series of writing electrodes which are arranged across a recording strip for recording signals on the recording strip. In one such device will encode the input signal in a binary-decimal Signal converted by means of an analog-digital converter. The binary-decimal-coded data becomes two Decoding matrices supplied, a matrix for the first decade and the other matrix for the second decade. the Writing electrodes are in groups of ten together-.refaiot, wherein every tenth electrode belongs to a group which is connected to one of the ten output lines of the first decoding matrix connected is. A second writing electrode is arranged below the writing row, and this electrode is divided into ten segments to which the ten output lines of the decoder of the second decade are fed.

With this arrangement, the problem arose that the segmentation of the electrode plate into the decade segments to a certain extent interferes with achieving a uniform writing over the full width of the writing arrangement, because the Gaps between adjacent decade plates deliver a

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Line patterns in the recorded image; It is therefore desirable to obtain a decoding matrix arrangement in which the difficulties of a segmented writing electrode plate are avoided, but which has the advantage that two decade decoding logic circuits can be used in combination with two decoding matrices.

Summary of the Invention;

The invention aims to provide an improved electrographic writer.

According to the invention, in an electrographic recorder, in which an analog input signal is converted into a binary-coded output signal, which is the one to be recorded Represents input signal, uses a decoding matrix, which consists of a series connection of two gates to supply the write voltages to the series of signal sequence electrodes to gate, the two gates forming parts of the decoding matrix, so that the decoding matrix is simplified.

According to a particularly advantageous embodiment of the invention, the two gates are transistors that can gate a write voltage of over 200 volts, so that the voltage

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drop across each of the gate transistors is smaller than the voltage drop across the gate, if only one Gate transistor would be used.

According to a particular embodiment of the invention, there are two Decoder decades provided, which work on the binary-decimal-coded output data of the analog-digital converter, so that two binary-decimal-encoded decoding control signals are obtained on ten lines, the first Gates controlled by the first decoding control signals and the second gates controlled by the second decoding control signals will.

Further features and advantages of the invention result
from the following description in conjunction with the drawing; show it:

Pig. 1 schematically, partly as a block diagram, a
electrographic recorder incorporating features of the invention; and

Pig. 2 the part enclosed by the line 2-2 in FIG. 1 with further details.

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The recorder 1 shown in the drawing has two input terminals 2 and 3 to which an input signal to be measured E. is applied. The input signal is fed to a preamplifier 4, in which it is amplified and via a Resistor 5 is fed to an input of a deviation detector 6. The series resistor 5 converts the input voltage E. into an input current I. which is compared in the deviation detector 6.

The error detector 6 forms part of an analog-digital converter 7. The analog-digital converter 7 has a two-decade up-down counting circuit 8. An exit the counting circuit 8 is fed to a series of current generators 9, with which a current I is generated, the amplitude of which corresponds to the count in counter 8. The output current I of the counter forms a reference feedback current which is fed to the other input of the error detector 6, where it is connected to the input signal I. is compared, which is to be measured v / ground.

The output of the error detector 6 is an error voltage E, which is fed to an input of a double comparator 11, in which the deviation voltage E with two

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BATH ORIGINAL

Reference values is compared which correspond to the upper and lower levels of a dead zone, the width of which is preferably equal to the voltage difference represented by adjacent numerical counts of the counter 8. The output of the double comparator 11 is a binary-coded signal which indicates a zero adjustment of the analog-digital converter and can occur in three forms. One output is a DO NOT COUNT command which _{corresponds to an error voltage E 0} which is within the dead zone within the comparator 11. A second command of the double comparator is the COUNT UP command, which is generated when the error voltage E is above the upper value of the dead zone. A third output of the double comparator is the COUNT DOWN command which is delivered when the error voltage E is below the lower value of the dead zone. The output of the double comparator 11 is fed to a decoding control 12, which decodes the binary counting commands and supplies control signals to the counting circuit 8, so that the counter 8 follows the input signal E i.

Another output of the counting circuit 8 is binary-coded Decimal data output; One output is provided for each decade of the two-decade counting circuit 8.

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The binary-decimal-coded data output 15 of the first decade becomes a decoding logic 15 of the first decade, and the binary-decimal-coded data output 14 of the second decade of the counter 8 of the decoding logic circuit 16 for the second decade. Both decoding logic circuits 15 and 16 convert their inputs in decimal outputs 17 and 18 respectively ten lines around. The two decimal outputs 17 and 18 on ten lines each become a combined decoding matrix and high voltage gate circuit 19 which converts the decimal inputs on ten lines into binary data outputs 20 to 100 lines fed to a series of 100 burst electrodes 21 that cross over a strip of electrographic recording paper 22 are arranged by a supply roll 23 on the writing row 21 is pulled past by means of a friction wheel 24 driven by a motor.

The binary data output on 100 lines, that of the write row 21 is supplied, selectively energizes the correct one of the electrodes, so that a charge image 25 on the charge retentive Surface of the electrographic recording paper 22 is laid down. A coloring channel 26 is across the Recording paper 22 arranged and has a Parb-

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slot 27 in one side wall so that liquid paint flowing through channel 26 is in liquid contact with it the charge image to be developed on the electrographic writing paper 22 comes. The color contains a colloid Suspension of positively charged toner particles, which are attracted by the negative charge image 25, so that this is developed at 25 '.

The decoding matrix 19 has two high-voltage transistor gates connected in series on, which are explained in more detail below in connection with FIG. 2 to selectively a to gate relatively high writing voltage to the electrodes of the series. More specifically, the writing electrode structure has a writing electrode plate 29 which, seen from the writing row 21, on the back of the electro- ^ raphi.schen paper 22 lies, and which is on a relatively high Potential works, for example plus 600 to 900 volts. Typically there will be about minua 500 volts on the writing electrodes 21 opposite the electrode plate 29 is required to create a charge image on the charge retentive surface of the Record paper 22 to be knocked down. A relatively high positive voltage of, for example, plus 300 to 600 volts is applied to all electrodes in row 21, with the exception of

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the electrode that is supposed to write. The decoding matrix selects the correct writing electrode and those connected in series Gates drop the voltage of the driven electrode from plus 300 volts to ground potential by creating a gate circuit between the electrode and ground is opened. When the activated electrode 21 is gated to ground potential a voltage of minus 600 to 900 volts appears on this electrode, relative to the plate electrode 29, so that a charge image is deposited on the recording strip 22 will.

In Fig. 2, the decoding matrix 19 is shown in more detail. For the sake of simplicity, the decoding matrix is intended 19 of FIG. 2 only in connection with an output 17 from Decoder 15 for the first decade of three lines, and also an output on three lines from the second decoder 16, in conjunction with a writing row 21 of 9 writing electrodes. With others In other words, the output of the decoding matrix 19 is only shown with 9 lines instead of the lines actually present Lines are shown.

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The plus 300 to 600 volts that are to be applied to the writing row 21 are v / earthed via a rail 31 and a Series of resistors 32 applied to this, which between the separated electrodes 21 and the rail 31 are connected. There is essentially no current from the electrode array 21 flows to the paper 22 or to the writing electrode plate 29, the voltage on the rail 31 is also applied to the electrodes 21.

The collectors of a first row of gate transistors are connected to resistors 32 and their emitters are in groups of three, in the case of a decade of decoding in groups of ten, of course. A second row of transistors 34- is connected to the first group of transistors 33 in series so that each combined group of first transistors 38 has a second gate transistor 34 shown in Row is connected to earth. The collectors of the second gate transistors 34 are connected to the emitters of the first Transistors 33 connected, and the emitters of the second transistors 34 are grounded.

The base of the transistors of the first row of gate transistors 33 is connected to the three output lines 17 (in fact

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relevant circuit 10 lines) of the decoding logic circuit 15 of the first decade, while the base of the second Transistors 34 with the three output lines 1Θ (in the actually implemented circuit 10 lines) of the decoding logic circuit 16 of the second decade is connected. The first line 35 of the three lines 17 of the decoder of the first decade is combined with the base of every third first gate transistor 33 by means of a busbar 36. Similarly, the second output line 37 from decoder 15 is the first decade with the base of every third first gate transistor 33 connected, starting with the second transistor in the series, through a second Busbar 38, and the third line 39 of the three output lines of the decoder 15 of the first decade is starting with the base of every third gate transistor 33 » the third transistor, connected via a bus bar 41.

If the first electrode 21 of the row 21 is to be excited, becomes the first line 35 of the three output lines of the decoder 15 of the first decade so that the base of every third of the gate transistors 33 is energized, beginning with the first transistor 33 'in the series. The output 18 of the decoding logic circuit 16 for the second decade has three output lines 51, 52 and 53, respectively. In order to ensure

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gen that the first electrode 21 'writes becomes the output lead 51 of the first decade is energized, while lines 52 and 53 are not energized, so that the first of the second Gate transistors 34 * is excited so that the voltage through the open gates 33 'and 34' falls to ground potential, which are connected to the first electrode 21 'so that a charge image is deposited on the recording strip 22 will.

The advantage of arranging a combined decoding matrix and high voltage gate transistors 33 and 34 connected in series is that it allows the gate transistors 33 and 34 to form part of the decoding matrix, thereby simplifying the matrix and number the required decoding elements is reduced . In addition, the problems which arise when using a segmented writing electrode 29 as part of the decoding matrix are avoided. Another advantage is that a series connection of two high-voltage transistors 33 and 34 serves to reduce the voltage drop across each of the transistors, so that the reliability and the service life are improved.

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Claims (5)

V1 P181 D Claims 1, electrographic recorder with one input channel, The signals to be recorded are fed to an analog-to-digital converter in the input channel, which follows the input signals and delivers a binary-coded output signal that represents the input signal, a decoder with which the binary output signal is decoded and a decoded binary output signal is generated which represents the input signal to be recorded, and a series of signal sequence electrodes which extend across a recording medium and are responsive to the decoded binary output to produce a curve on the recording medium corresponding to the signal, characterized in that the decoder comprises a series of in series connected first and second gates with which signal writing voltages are applied to the electrodes of the electrode row, means which are responsive to the binary-coded outputs in order to generate two decoding control signals, means with which the 109839/0511 first decoding control signal is applied to certain of the first gates in order to control them, and a device, with which the second decoding control signal is applied to certain of the second gates in order to control them so that the decoded binary output is generated. 2. Writer according to claim 1, characterized in that the writing voltage is greater than 200 volts and the two Gate are transistors. 3. Recorder according to claim 1 or 2, characterized in that the binary-coded output of the analog-digital converter binary-decimal-coded, and the coded on the Data-responding device contains two decoder decoders, each of which has two binary-decimal decimal control channels on ten lines, and that the first gate with the first decoding control signals and the second Gates are controlled with the second decoding control signals. 4. Writer according to claim 3, characterized in that 100 signal sequence electrodes are provided in the row and that a first gate for each signal sequence electrode ... / A3 109839/0511 is provided, a device with which the inputs of the first gate are combined so that / 3 the same Decoding control signal is fed to 10 lines every tenth electrode of the series, 10 being separate Groups of gates are provided, each having a separate output control signal on one of the 10 lines and that one of the second gates is connected in series with each group of first gates, and the 10 lines for the decoding control signal are each connected to one of the second gates. 5. Writer according to claim 4, characterized in that the two gates are transistors, each of which is one Voltage of over 150 volts. 109839/0511 Blank page