DE1673554A1 - Digital control procedure - Google Patents

Description

BÖLKOW limited liability company Ottobrunn near Munich

Ottobrunn, August 21, 1967 BP 645 SX 1 Me / st

Digital control procedure

The invention relates to a digital control method and a device for carrying out the method in which the input signal and the output signal of a controller follow increments are, and the output signal from at least a proportional and a differential component of the input signal is formed, whereby the differential component is approximated as a difference quotient.

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Increasingly, digital computers are used in control processes that digitally handle the entire control process control And also all to the formation of the as an output signal required functions due to a control deviation occurring as an input signal calculate.

So are. e.g. in the journal ETZ-A, Volume 88 (1967), Issue 6, pages 159 to 16Jt control systems in connection with digital computers, whereby the functions to be determined for a controller with PD or PID behavior are from Digital computers are formed. The integral and differential functions are calculated by adding up or Formation of the difference quotient approximated, since with digital computers essentially only additions and subtractions can be carried out in a simple manner.

In the case of the previously known digital control methods of this type Larger digital computers are used, which because of their great effort and therefore also large computing capacity Usually control several control systems at the same time via multiplex lines. Especially with e.g. in missiles The control systems used in the aerospace industry are the expense of such large digital computers and also the large space and payload requirements caused by this, however, are undesirable.

10984A / 0269 BATH ORIGINAL

So-called "Digital Differential Analyzers" have also been used. proposed to represent simplified digital computers for control tasks. Digital However, controllers work on the basis of digital integrators, which, like analog summing amplifiers, are interconnected to form a control network are, with each individual integrator containing a full adder, so that the entire arrangement always is still quite complex, see H. Rechnberger: The Application of Digital Differential Analyzers in Control Loops, IFAC Congress, Basel 196 3. "

The object of the invention is therefore to specify a digital control method that while maintaining the when using greater accuracy achievable by digital computers allows the use of simple logic circuits in order to in order to keep the circuit complexity as well as the size and weight of such a digital computer small, which in its computing capacity is based on the requirements of the computational processes to be carried out in the control process is tailored.

Based on a digital control method in which the input signal γ and the output signal jj of a controller are incremental and the output signal is formed from at least a proportional (P) and a differential (D) component of the input signal ψ (t), the D -Part is approximated as a difference quotient, the-

This object is achieved according to the invention in that the PD component % _{pD of} the output signal J is formed from an undelayed component C ^ «^ Ct) and a delayed component C" · ^ Ct-Z ") of the input signal, the factor C ₁ = selected and the factor C- is realized by the division ratio of a frequency divider.

With such a digital control method it is achieved that the proportional component and the as difference quotient approximated differential component of the input signal summarized and then into an undelayed part and a part delayed by a certain delay time ■ £ · of the input signal is split, with both components multiplied separately by certain factors C. and C " and added, taking into account their sign, and thus the output signal representing the control command form.

\ The differential component, which corresponds to the rate of change γ of a deviation given by the input signal ψ , is approximated by the difference quotient

educated. The usual controller equation for a PID controller for the output signal representing the control command is from the form

PID ^{= K} / V » ^dt ♦ Pyqf, (2)

10984A / 0269

where is the PD fraction

J _PD = P 'f * q * f (3)

In this PD component, according to equation 1, the

Replace the portion containing the rate of change ψ by the difference quotient, so that the following relationship results:

Ct) ♦ ι-

Equation 4- can be separated into two factors, which are assigned to an undelayed component ^ ³ Ct) and a delayed component ^ (t- £ ") of the input signal f .

p _D = Cp + -p) φ (t) - - | r - * e et - r) (5)

According to relationship 5, the output signal containing the proportional and differential components can be built up in an up-down counter, in which the increments of ^ Ct) with the maintenance factor ρ + * * go directly into the counter and the increments of if

q Ct- f) with the stop factor - and inverted pre

characters are given to the counter after passing through a delay line.

Since the information of the input signal φ present as an incremental sequence is contained in the frequency of this incremental sequence, the above-mentioned maintenance factors must be understood as frequency-changing factors. The increments

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therefore pass through a digital frequency divider before entering the up / down counter acting as a command counter, whereby the required division ratios can be brought to favorable values by suitable definition of the increment sizes Δ <f and A j and the delay time T see. The following incremental values may be mentioned as an example of such a favorable definition, the input signal Y and the output signal J acting as a control command here each representing angular values.

1 increment of the offset angle: Δ </ = 0.01 ° 1 increment of the positioning command ίΔ ^ = 0.16 °

When choosing such a definition of the increment sizes it should be noted that the ratio of the increment multiplied by ρ corresponds to a binary number. After this determination, t- ^ j is the number of increments from «f and ^ * -. the number of increments from J. With such a normalization, the PD component of the controller equation can be converted into the following relationships:

If ■ if- ^ T'-i ^ -ii-l * ^ ⁽⁷⁾

λ * q ^s α d> q

The two factors f ^ -. (P + - ^ r) = C ₁ and - ^ - ■ =, = C _P are now the partial ratios to be realized if the PD component of the output signal ^ consists of an undelayed component C ₁ · tf (t) and a delayed component C ₂ · i'it-Z) of the input signal <· / * (t) is formed.

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When defining these factors C ₁ and C-, the incremental quantities Atf and A F are already set to the above-mentioned values and the factors ρ and q originating from the general controller equation are also determined by the respective desired controller behavior. In the factors C. and C_, therefore, only the delay time TT can still be freely selected, with this being less than 0.1 seconds as possible in order to achieve a justifiable technical effort. should be.

According to an essential feature of the invention, the size of t and the ratio ^ -4r was chosen so that on the one hand the factor C ₁ = 1, so that the undelayed portion of the input signal ψ Ct) without passing through a frequency divider causing a switching factor directly to the Command counter can be given, and on the other hand ¹ Ρ a power of two with a negative exponent. If the factor C ₁ = Tc "^ P ⁺ n ^ -" * ■ * ^then with the already determined

th increment sizes of A ^ = 0.16 ° and d * f = 0.01 ° and the

Factors of the controller equation ρ = 1 and q = -g- sec. for the delay time c a value of c -γππ sec. The factor C "xst

-k always of the form 1-2 under the conditions mentioned

-1 ^^^ 15

-, with the sizes selected here it is -r- · - = Te "

2 ^KA 3 L ^lb

which determines the division ratio for the frequency divider running through the delayed component t-f'it-T).

According to a further development of the invention, the output signal X, in addition to the proportional (P) and differential (D) components, is derived from an integral (D component of the input

109844/0269

signals ψ (t), where the I component J> {= ^K k ^dt

J> {= ^K k ^d

is approximated by ^ ₁ = C ₃ ι ^ cA. · At.

According to this embodiment of the invention, a digital control method with PID behavior is additionally used The integral component of the input signal is formed, this I component being formed in a manner known per se by forming the sum of a digital integrator is approximated. The following relationship applies to the I component

Vt ^sk 'S dP'Aii - k Δ t SY (8)

5 ^l ii ι ^I

where Lf ^ = Lp (t · i -4t) are sampled values of the angular deviation which are formed with the period £ t. If, as in equations 6 and 7, the incremental values Δ * f and d ^ are introduced, then with k = 2, for example, the following relationships result:

5 (0 *
AO ^ '

(10) (11)

In this expression 11, At, the integration clock period can be freely selected, its reciprocal value f ^ = -] - £ · corresponds to the upper limit frequency of the integrator in its effect as a low-pass filter. Since smaller values of & t increase the effort, \ t is chosen to be as large as is justifiable within the framework of the required accuracy of the control behavior.

10984 ^ / 0269 - 9 -

With a mean angular deviation of about <~ f = K ° =, which is temporarily regarded as constant, the I component of the controller expressed in equation 11 changes by = -s · Ά t · M-OO = '50 per scan ^ A t increments, i.e. by 50 increments per second. The integration clock frequency fj should therefore be in the order of magnitude of 50 Hz in order to avoid a discontinuous change in the I component, for example in the form of pulse groups. As an example, the smallest binary number above 50 is used as the integration clock frequency

fj = "6" f Hz selected.

To carry out this digital control method according to the invention, a device is specified in a further embodiment of the invention which contains a synchronizing buffer controlled by a first clock signal, at the input of which the incremental sequence of the input signal is and the output with a first up / down counter and a shift register connected is. The output of the shift register is also connected to the first up-down counter via a frequency divider and a Vorzexchenxnverterschaltung, at the output of which a change in its counter reading can be taken as an output signal fc p _D in the form of an incremental sequence.

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109844/0269

The synchronization buffer contained in this device ensures that the incremental sequence of the input signal is applied to the individual logic circuits in a phase-synchronous assignment, the clock signal controlling the synchronization buffer must have a higher pulse repetition frequency than the highest possible incremental frequency of the input signal. The increments synchronized in this way are sent directly as an undelayed component of the input signal to the up-down counter acting as a command counter, which, in addition to an input for the counting signals, has a further input for taking into account the respective sign of the counting signals at the counting input. In addition, the synchronized increments are sent to a shift register ¹ which delays the sequence of inclines by the delay time ~ C and thus forms the delayed component «f (t-7r) of the input signal. This component reaches the counting input of the up / down counter via a frequency divider, the division of which determines the switching factor of the delayed component, and a sign inverter circuit. The frequency divider for the delayed component of the input signal is controlled by a further clock signal which has the same repetition frequency as the first clock signal, but without a phase shift, so that the increments of the undelayed component that go directly to the up / down counter always reach the counter achieve something earlier than a ver> -

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109844/0269

BATH ORIGINAL

hesitated increment, creating a different sign evaluation the two increment sequences in the counter can be taken into account without the occurrence of malfunctions.

According to an advantageous development of the invention, a second up-down counter, which is additionally connected to the output of the synchronization buffer, is provided to form the integral component, which is connected in parallel with a step-down counter, which in turn is connected to a third up-down counter, where the overflow pulses of this third up / down counter reach the first up _{/ down counter as an integral component ξ T}

According to this further development of the invention, a simple digitally operating integrator is specified which additionally to the logic circuits provided for the PD component to the first, which is designed as a command counter Up / down counter is effective. This integrator will controlled by two other clock signals, one of which is the counter clock for clearing the down counter and simultaneous Transferring its contents to the third up-down counter supplies and the other the integration clock for retrieving the in the second up / down counter stored content on the down counter and for releasing the counter clock «

- 12 -

According to a preferred embodiment of the invention, there is the synchronization buffer consists of a first flip-flop stage, the two inputs of which each have an AND circuit from the first clock signal and the input signal or the inverted one Input signal are applied. The outputs of the flip-flop stage are connected to further AND circuits out, whose second inputs acted upon by the input signal or the inverted input signal in reverse assignment are like the inputs of the first two AND switches. The outputs of these two other AND circuits are connected via an OR circuit to an input of another AND circuit, the second input of which is from first clock signal is applied. The output of this last AND circuit is at the input of a pulse shaper stage switched at whose output the synchronized input signal is available.

Such a synchronization buffer ensures that the Incr-P which is present at the input as a static square-wave signal ment sequence is continuously sampled by the first clock signal indicating the synchronization clock and at the output as Pulse sequence appears, with increments appearing at the output in the form of pulses of constant temporal length, independently of the time intervals at which the increment sequence pending at the input - i.e. the states of the there

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1098U / 0269 BAD ORIGINAL

applied static square wave signal changes.

All details of the invention will be carried out on the basis of an exemplary embodiment shown in the drawing of the procedure suitable facility explained:

Show in detail:

Figure 1 shows a partly schematic logic circuit * f a facility suitable for implementing the digital control procedure,

Figure 2 is a functional diagram of the PD component of the Controller determining part of this facility,

FIG. 3 the logic circuit of a digital integrator used in the device,

FIG. 4 shows a functional diagram of this integrator,

Figure 5 is a timing diagram of that used in the device Clock signals and

FIG. 6 shows a logic circuit of the synchronization buffer used in the device.

- 14 -109844/0269

The device shown in Figure 1 for performing the digital control method according to the invention exists from a synchronization buffer 1, at whose input the input signal present as an incremental sequence is present. The exit of the synchronizing buffer 1 is via an OR circuit 11 to the counting input of an up-down counter 2 switched. At the same time, the output of the synchronizing buffer 1 is set to a first via AND circuits 12 and 13 Shift register 3 switched, the outputs of the shift register 3 via further AND circuits IU and 15 are switched to one input each of a first flip-flop stage 4. The one output of this flip-flop stage 4 is switched to a four-digit up-down counter 5 via a further AND circuit 16. The outputs of the Up-down counters 5 are via two AND circuits 17 and 18 interconnected in such a way that it only emits an output signal with every 16th counting pulse. The output signals the AND circuits 17 and 18 are connected to inputs of further AND circuits 19 and 20, their outputs are connected to a common OR circuit 21. The output of the OR circuit 21 is inverted Input of a further AND circuit 22, the second input of which is connected to the output of AND circuit 16. The output of the AND circuit 22 is via the OR circuit 11 also to the input of the up-down counter 2 led.

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In addition to the increment sequence of the input signal given at the input of the synchronization buffer 1, a signal indicating the respective sign of the increments is given directly and inverted to inputs of two AND circuits 23 and 24, the second inputs of which are acted upon by a first clock signal T--, which The outputs of the two AND circuits 23 and 24 are connected to the two inputs of a second shift register 6, the two outputs of which via AND circuits 25 and 26 to a second flip-flop stage 7 are switched. The respective second inputs of the AND circuits 14, 15 and 25, 26 are also acted upon by the first clock signal T. One output of the flip-flop stage 7 is connected to the respective second inputs of the AND circuits 19 and 20 , the second input of the AND circuit 19 being inverted. At the same time, this output of the flip-flop stage 7 is connected to an input of the up-down counter 5 that influences the counting direction connected to an input influencing the counting direction of the up-down counter, which is also connected to the output of AND circuit 23 via OR circuit 28. The second input of AND circuit 27 is acted upon _{by a second clock signal T 2} that at the same time

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the second input of the AND circuit 16 and the clock control inputs the shift registers 3 and 6 are applied.

The device shown in FIG. 1 has a digital integrator 8, shown here in dashed lines, one input of which is connected to the output of the synchronizing buffer 1 and the other input of which is connected to the output of the AND circuit 23. The two outputs of the integrator 8 are connected to the OR circuit 11 for forwarding the increments output by the integrator to the up / down counter 2 and to the OR circuit 28 to apply the up / down counter 2 to the one specified by the integrator Sign connected. To control the integrator 8, two further clock signals T ₃ and T ₁ ^ are fed to it via control inputs.

The PD component of the input signal is built up in the up / down counter 2 in the following manner, shown in FIG. 2 as a function diagram. The increment sequence arriving as an input signal is intended to represent a control deviation that occurs due to an assumed rate of change of ff -5 ° / sec., Which becomes zero after a period of 0.4 sec.

- 17 -

109844/0269

The synchronized increments, which arrive instantaneously via the synchronization buffer 1 on the up / down counter 2, build up in the form of a _{step-shaped curve ^) 1} , which after 0.0t sec. reaches its maximum value and then remains constant. The portion of the synchronized increments delayed by the time delay TT and passed through the shift register builds up as a further step-shaped curve J ", which also reaches its maximum value after a time of 0.04 seconds and remains constant. The four-digit up-down counter 5 is switched so that it does not pass on every sixteenth pulse fed to it by blocking the AND circuit 22, the AND circuits 17 and 18 being connected to the outputs of the counter so that each by output of the eighth, twenty-fourth, fortieth, etc. pulse, the AND circuit 22 is blocked and thus the input of the counter 2 can not be applied. In the stepped curve c5 ₂ shown in FIG. 2, the eighth pulse is therefore missing, so that the greatest height reached by the curve 5 'is one pulse lower than the height reached by the curve ^ i.

The sign input of the up / down counter 2 is influenced via the OR circuit 28 in such a way that the delayed pulses passed by the AND circuit 22 influence the counter 2 in the opposite counting direction

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the undelayed pulse reaching the counter from synchronization buffer 1. _{A phase shift of the second clock signal T 2} controlling the shift registers 3 and 6 and the AND circuits 16 and 27 with respect to the first _{clock signal T 1 controlling the synchronizing buffer 1} ensures that a pulse delivered by the AND circuit 22 to the counter 2 is always arrives a little later than an undelayed pulse coming from synchronization buffer 1

As can be seen from FIG. 2, the up / down counter 2 therefore _{adds up the pulses of the undelayed increments represented by the stepped curve J 1} until a first pulse of the delayed increments shown _{by the stepped curve, J 2, arrives.} Such a first pulse and all further pulses of the delayed increments are each subtracted from the sum of the undelayed increments already counted in the counter Counter 2 increases its counter reading by 1 due to the undelayed increment that arrived shortly before and reduces its counter reading by 1 again due to the pulse of the delayed increments arriving immediately afterwards. After the arrival of the seventh pulse of the delayed increments, the eighth pulse is absent due to the blocking of the AND circuit 22, so that the counter reading of the counter is less than the previous counter reading

109844/0269 " ¹⁹ "

Pulse increases, while the subsequent incoming pulses of the delayed increment sequence this counter reading keep constant again until the speed of angular change is reached Ψ = Ό no further undelayed Pulses of the incremental sequence reach counter 2, so that the pulses still arriving after this point in time reduce the counter reading accordingly if the incremental sequence is delayed.

Those caused by the occurring during this process counts of counter 2 waveform shown in Figure 2, which is designated by 5p _D, is the PD component of the output signal J> ^at · This PD component is made up of the ever-changing D component and the constant P component together

The digital integrator shown only in dashed lines in Fig.l to form an additional integral component to the PD component of the controller is shown in more detail in FIG. The integrator 8 consists of a first up-down counter 81, whose binary! Outputs have a series of first AND circuits 8 2 are led to a series of OR circuits 83. The binary O outputs of the up / down counter 81 are also connected to the OR circuits 83 via a series of second AND circuits 84. the highest-digit level of the up-down counter 81 is

- 20 109844/0269

the sign of the content stored in the counter, so that its binary 1 output is routed to a first AND circuit 8 21, while its O output is routed to a second AND circuit 8 22, the respective second inputs of the AND circuits 8 21 and 8 22 are acted upon _{by a clock signal T 1 ^ indicating the Inte grat ions clock.} The output of the AND circuit 8 21 is connected to all the second inputs of the first row of AND circuits 8 2 and the output of the second AND circuit 8 22 is connected to the second inputs of the second row of AND circuits 84 ·. The outputs of the two AND circuits 8, 21 and 822 are each connected to an input of a flip-flop stage 85, which indicates the sign of the content stored in the counter 81. The counter 81 has an input for the synchronized increments and a further input for taking into account the sign belonging to these increments.

The outputs of the OR circuits 8 3 are each switched to a step of a down counter 86, so that the steps of this down counter 86 via the OR circuits and the AND circuits 8 2 or 8 * are step-parallel with the up-down counter Counters 81 are connected. The highest-digit stage of the down counter 86 is controlled by the clock signal T ^ indicating the integration clock, the binary 0 output of this highest-digit stage with the input of a

- 21 1098U / 0269

AND circuit 861 is connected, the other input of which is acted upon by the clock signal T ₀ indicating a counting cycle.

is beat. The output of the AND circuit 861 is connected to the counting input of the down counter 8 6 and the counting inputs a further up-down counter 87 is connected. In addition to this counter input, the up-down counter 87 has a counter input that takes into account the respective counting direction Input that is connected to the output of the flip-flop stage 85. The output of the flip-flop, ^ Stage 85 is also connected to the output indicating the signs of the increments output by the integrator, which in turn is connected to the up / down counter 2 via the OR circuit 28 (cf. FIG. 1). The exits of the up-down counter 87 are connected via two AND circuits 871 and 872 in such a way that on Output of the AND circuit 871 always occurs an overflow pulse when the up-down counter a Has reached +256. In contrast, an overflow pulse always occurs at the output of AND circuit 872 on when the up-down counter 87 has reached a count of -256. The outputs of the AND circuits 871 and 872 are each connected to an input of two AND circuits 873 and 87H, their outputs in turn are connected via an OR circuit 875 to the output emitting the increments of the integrator 8.

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109844/0269

To form the integral component of the input signal Ψ present as a synchronized increment sequence, the respective count of the up / down counter 81 is changed in accordance with the sign associated with the newly arriving increments. Each time an integration clock arrives _{, which is indicated by the clock signal T 11} , the count currently contained in the up-down counter 81 is overwritten in parallel via the AND circuits 8 2 or 84 and the OR circuits 8 3 in the down counter 86. It is sufficient to store only the binary O-signals representing the count of the up-down counter 81 in the down-counter 86, depending on the sign indicated by the highest-digit level of the up-down counter, which is via the AND circuits 8 21 or 8 22 is read out, the instantaneous count contained in the up / down counter 81 is transmitted directly to the down counter 86 via the AND circuits 8M or inverted via the AND circuits 8 2. At the same time, when the integration clock occurs, the highest-digit level of the down counter 86 is set to zero _{via the clock signal T 1 ^, whereby the AND circuit 861 is permeable to the clock signal T 3} indicating the counting cycle and the down counter 86 is counted to zero according to this counting cycle . If the down counter 86 has reached the count zero, the AND circuit 861 is blocked again and it can

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no further counting clocks on the down counter 86 and so get to the up / down counter 87. In the up / down counter 87 is thus increased with each integration clock one corresponding to the content of the down counter 8 6 Number of pulses counted and there under consideration their respective sign added. When a counter reading of + 256 is reached, the forwards -Reverse counter 87 from an overflow pulse, which as an increment delivered by the integrator to the up-down counter 2 (see. Fig. 1) arrives. The sign circuit of the flip-flop stage 85 is simultaneously the sign of this increment is given for consideration in counter 2.

As shown in the functional diagram of the Integrator 8 can be seen, the up-down counter acts 87 as the corresponding activation factor of the I component effecting frequency divider similar to the up-down counter explained in connection with FIGS 5. The function diagram shown in Fig. 4 is for a 0.2 sec. constant rate of change of angle <-f = 5 ° / sec. indicated, which after 0.2 sec. the value zero er enough. The needles ζ (86), which increase linearly with increasing time at a finite speed of angular change, give the counter transferred to the down counter 86

- 24 109844/0269

stood on. The content of the up-down counter 87 shown here as curve ζ (87) - increases in every • g ^ r sec. by the amount contained in the downward counter 8 6 and thus rises approximately quadratically with a constant, finite VJwinkel change speed ψ. After 0.2 sec. the angular rate of change is equal to zero and the counter content occurring in the down counter 8 6 is constant, since the counter content of the up / down counter 81 ζ (81) no longer changes. The counter content of the up / down counter ζ (87), which increases by taking over this constant counter content of the downward counter 8 6, thus rises approximately linearly at a rate of change of angle of zero. With a count of 256 each of the up / down counter 87, an increment is output by the integrator 8 as the integral component 5 j of the output signal 5, so that there is an approximately linear increase in the integral component J j output by the integrator over the entire function diagram of the output signal% issued by counter 2 (see Fig. 1). The forward-backward counter 87 thus has a partial ratio of C ₃ -T ^ t representing the maintenance factor for the integral component, so that only every 512 th pulse is sent from the integrator 8 to the counter 2 (see Fig. 1).

The frequency of the clock signal T ₃ must be chosen so high that the maximum amount of ¹ ^, in which here selected

- 25 -

6AD ORIGINAL

12th
th example 2 increments, within an integration period dt = -r- from the down counter 86 in the forward

^r I
up-down counter 87 can be counted. As can be seen from the pulse diagram shown in Fig. 5, the repetition frequency-des'Täkt & ignals T _{3 is} 262 KHz, which ensures that at a repetition frequency of 6if Hz of the clock signal T ₁ ^ indicating the integration clock within an integration period At = - grr sec. Up to 2 increments can be counted into the up / down counter 87.

The phase shift is also from the pulse diagram in FIG of the clock signals T. and T «, which are otherwise the same Have repetition frequency to recognize the correct functioning of the up / down counter serving as a command counter 2 (see Fig. 1).

The pulses of the clock signals T. and T- occur, as shown in the pulse diagram, always during pulse pauses of the clock signal T _g indicating the counting rate, which inevitably means that the increments coming from the integrator 8 are also passed on to the up / down counter 2 takes place at a different point in time than the forwarding of the undelayed increments of the PD component.

The synchronizing buffer 1 shown in Fig. 6 consists of a flip-flop stage 100, the inputs of which each have an AND

- 26 10984A / 0769

Circuit 101 and 102 are controlled. _{The first clock signal T 1} , which indicates the synchronization clock, is fed to the first two inputs of the AND circuits 101 and 102. The other two inputs of the AND circuits IQ1 and 102, on the other hand, are connected to the input at which the incremental sequence of the input signal is present in the form of static square-wave signals. The input of the AND circuit 101 receives the inverted input signal and the input of the AND circuit 102 receives the input signal directly.

The two outputs of the flip-flop stage 100 are connected to two further AND circuits 103 and 104, the outputs of which are connected to a common OR circuit 105. The respective second AND circuits 103 and 10U are also connected to the input of the synchronization buffer, but the assignment of the input signal to the inputs of the AND circuits 103 and 10U is reversed to that of the AND circuits 101 and 102. The input of the AND circuit 103 is connected directly and the input of the AND circuit 10U is connected in an inverted manner to the input of the synchronization buffer. The output of the OR circuit 105 is connected to an input of a further AND circuit 106, the second input of which also has the clock signal T ₁ indicating the synchronization clock. The output of this AND circuit is finally connected to the input of a pulse shaper stage 107

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BATH ORIGINAL

bound, at the output of which the increments of the input signal that are synchronous with the clock signal T. can finally be removed.

Is e.g. at the input of the synchronizing buffer a static square-wave signal with the state "0", so the flip-flop stage 100 when a clock pulse of the clock signal T _{1 occurs} via the AND circuit 101 so that its left output 1-signal and your right output carries an O-signal. The AND circuits 103 and 104 are both blocked in this case, so that no increment is emitted at the output. If the static square-wave signal at the input changes so that the state "1" is present at the input, the synchronization buffer receives a first increment. When a pulse of the clock signal T _{1 occurs} , the AND condition of the AND circuit 102 is therefore fulfilled and the flip-flop stage 100 is transferred to its other switching state. After switching over, the right output of the flip-flop stage therefore has a 1 signal and the left output of the flip-flop stage has a 0 signal. The AND conditions of the AND circuits 103 and 104 are therefore no longer met after the flip-flop stage 100 has been switched over.

Before switching over the flip-flop stage 100, however, the AND condition of the AND circuit 103 is due to the at the input pending 1-signal of the static square-wave signal changing its state is fulfilled, so that with the occurrence of an im-

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BATH ORIGINAL

pulses of the clock signal T ^ just before switching the flip-flop stage 100 the AND condition of the AND circuit 106 is fulfilled and thus the pulse shaper stage 107 in its unstable Switching state is transferred. The hono flop level 107 has such a time constant that it flips back into its stable state after the same time and so that it forms the trailing edge of the pulse appearing at the output as a synchronized increment.

During an increment at the input of the synchronizing buffer that means a change of state of the static square-wave signal in each case, there is a synchronized increment at the output of the synchronization buffer 1 a pulse of finite duration, which therefore consists of a leading and trailing edge.

The state at the input static square wave signal changes again, it is in a corresponding manner to _k of the switching state of the basic flip-flop 100, resulting yet from the respective preceding switching state of the static rectangular signal, the AND condition of the AND circuits 103 and 104 fulfilled, so that simultaneously with the occurrence of a pulse of the clock signal T ^ the AND circuit 106 is permeable and the flip-flop stage 100 is switched over according to the new switching state «

The pulse repetition frequency of the clock signal T ₁ indicating the synchronization clock must be selected so large that between two

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BATH ORIGINAL

successive pulses of the clock signal T. none Change of state of the static square-wave signal present at the input of the synchronizing buffer can occur.

Claims: 109844/0769

Claims (7)

Claims 1. Digital control method in which the input signal and the output signal of a controller are incremental sequences and the output signal is formed from at least a proportional (P) and a differential (D) component of the input signal (f , the D component being approximated as a difference quotient is characterized in that the PD component 5 _{pD of} the output signal 5 is formed from an undelayed component C .- ^ Ct) and a delayed component C ₂ * ψ (t- f) of the input signal »f ³ , the factor C. chosen equal to 1 and the factor C "is realized by the division ratio of a frequency divider. 2. Digital control method according to claim 1, characterized in that the output signal 5 is formed in addition to the proportional (P) - and differential (D) part of an integral (I) part of the input signal ψ (t), the I-part ^ £ = k | t / dt is _{approximated by ^ 1} = C ₃ ¹ ^ ^ n i '/ i *. 3. Device for performing the method according to claim 1 or 2, characterized in that 10984 ^ / 0769 BATH ORIGINAL - 31 - _{a synchronization buffer (1} ) controlled by a first clock signal (T 1) is provided, at the input of which the incremental sequence of the input signal ^l f is present and the output of which is connected to a first up / down counter (2) and a shift register (3), that the output of the shift register (3) via a frequency divider (5) and a sign inverter (24.7) is also connected to the first forward-backward counter (2), at whose ™ output a change in its count as an output signal rp _D in Form of an incremental sequence is removable. 4. Device according to claim 3, characterized in that the shift register (3) and the Frequency divider (5) controlled by a second clock signal (T ") is that of the same repetition rate as that first clock signal (T.) but compared to this phase-shifted i is pushed. 5. Device for performing the method according to claim 2 and claims 3 and 4, characterized in that a for forming the integral component with the output of the synchronizing buffer (1) additionally connected second up-down counter (81) is provided which is step-parallel with a down counter (86) - 32 - 1098ΛΑ / 0269 BATH ORIGINAL is connected, which in turn is connected to a third up-down counter (87), the overflow pulses of this third up-down counter (8 7) as an integral component J _τ on the first up-down counter (2) reach. 6. Device according to claims 3 to 5, characterized in that the down counter (86) and the third up / down counter (87) are controlled _{by a third clock signal (T 3) indicating the counting rate of these counters (86, 87)} , the repetition frequency of which is a multiple representing a binary number greater than the repetition frequency of the first two clock signals (T ₁ , TJ and its phase position in relation to these clock signals (T ₁ , T «) is selected so that the pulses of the first clock signals (T., T ") fall in the middle of the pulse pause of the third clock signal (T ₃ ) and that the points in time for the transfer of the counter content of the second up-down counter (8Ϊ) to the down counter (86) and the transfer of its content to the third forward Down counters (87) are determined by a fourth clock signal (T ₁ ^) indicating the integration clock. 7. Device according to claims 3 to 6, characterized in that the Synchronxsxerpuffer (1) - 33 1098 A4 / 0269 consists of a first flip-flop stage (100), the two inputs of which each have an AND circuit (101, 102) are acted upon by the first clock signal (T.) and the input signal or the inverted input signal that the outputs of the flip-flop stage (100) are led to further AND circuits (103, 104), the second inputs of which from the input signal or the inverted input signal in reverse assignment to the first two AND circuits (101, 102) are acted upon so that the outputs of these two further AND circuits (103, 104) are connected via an OR circuit (105) to an input of a further AND circuit (106) whose second input is acted upon by the first clock signal (T.), and that the output of this last AND circuit (10G) is connected to the input of a pulse shaper stage (107), at whose output the synchronized input signal is available. 109844 / Γ) 769
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