DE1589779A1 - Semiconductor circuit - Google Patents

Description

Fairchild Camera and

Instrument Corporation F 66O7

300 Robbins Lane

Syosset, Long Island, New York (V.St.A.)

Semiconductor maintenance

The invention relates to a semiconductor integrated circuit and to the method of making such a circuit.

In the case of integrated circuit arrangements made of silicon, the monolithic piece must have external electrical connections, so that power is supplied, so that multiple circuits can be connected together, and for other purposes. To make such connections, each circuit contains a number of areas of conductive material (e.g. Aluminum layers), which in the following are also called "connection points" (pads). These connection points are usually arranged on the circumference of the circuit components, in order to obtain the highest possible density and flexibility when connecting the components. The connection points have such a size that a wire connection with Can be attached to it using known bonding methods, such as ultrasonic or thermocompression bonding.

As mentioned, the connection points have hitherto been arranged outside the area of the circuit components. Such a design and arrangement of the connection points increases the overall space requirement of the integrated circuit arrangement considerably, and at the same time limits the maximum achievable density of the components. The number of circuits that. can be processed in batches in a single operation, for example with diffusion ovens and photographic

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lithographic masking stencils also depend, at least in part, on the extent of the integrated circuits away. An increase in the dimensions of an integrated circuit due to the space required by the connection points therefore disadvantageously limits the output in the manufacture of integrated circuits.

The invention aims to remedy the disadvantages described, and in particular it aims at an effective reduction the space required by an integrated circuit,

In an integrated circuit arrangement according to the invention there are several electrical components and their connections arranged on or in a larger part of the surface of the base body, an applied insulating layer lies over at least a portion of the components and connections, and over the insulating layer, there is one electrical conductive connection point which is connected to at least one of the circuit components and to a connection conductor can be connected.

In the production of an integrated circuit arrangement, the procedure according to the invention is that within one Basic body several cooperating circuit components be formed on or in a larger part of the surface of a semiconductor body that a first insulating layer is formed at least partially over the greater part of the surface that electrical Connections made on the first insulating layer between at least two of the components that a second insulating layer is disposed over at least a portion of one of the connections, and that a conductive connection point is formed over the second insulating layer on or over the greater part of the surface which is electrically connected to at least one of the circuit components and substantially within the topographical limit, which is determined by the components

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th and the connections are formed.

Embodiments of the invention are described in more detail with reference to the drawing:

Fig »1 shows a simplified and schematic plan view of an integrated circuit as it is after

Prior art is known. Fig. 2 shows a simplified and schematic plan view

to an integrated circuit according to the invention. FIG. 3 shows an enlarged partial section along the line

3-3 of Fig. 2
Fig. H shows in a similar representation as in Figure 3 · ei * ¹ further embodiment of the invention.

In the case of the integrated circuit 10, as shown in FIG. 1 as an example of an arrangement known from the prior art As shown, several circuit components (e.g., 22 in Figure 3) are within the designated area 12, which is delimited by the dashed line 14 is available. The area 12 of the integrated circuit constitutes a major part of the surface of a Base body 13. The components within area 12 can be resistors, capacitors, transistors, diodes or other known electrical, electronic or solid-state components · Outside the area 12 of the integrated Circuit components there is a region 15 in which a plurality of electrically conductive connection points 16 available. The connection points 16 are arranged around the periphery of the area 12, and they are so formed and sized so that a conductor, such as a wire, can be attached to them; such a wire can for example are made of aluminum or gold and are about 0.025 mm (1 mil) in diameter. The area such a junction can be on the order of

Be 0.0065 to 0.013 mm (10-20 sq. Mils). The connection points 16 are integrated with various circuit components by thin-film interconnections within the Circuit connected. In the cone there are such

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known arrangement, the connection points together with the connections between the components of the circuit are formed simultaneously over the insulating layer together with the connections which pass through the insulating layer and form electrical contact with the various components and elements. The method of forming these connections, fasteners, etc. is described in detail in U.S. Patent 2,981,877, which issued April 25, 1961 to Robert N. Noyce. Although the known arrangements of this type are very advantageous, they still require improvement insofar as the area 10 of the integrated circuit requires a relatively large amount of space. As can be seen from FIG. 1, there are no circuit elements under the area 15 of the connection points. The area is therefore used exclusively as a base for the connection points 16. In some arrangements, the area 15 of the connection points takes up to kO $ of the integrated circuit

The integrated circuit arrangement and the method for forming connection points according to the invention enable it to eliminate the disadvantages of the known arrangements and methods in that the connection points in the are arranged essentially over the area of the integrated circuit components. As with the integrated Circuit 10 of Fig. 2 is shown, the connection points 16 are immediately above the area 12 of the integrated Circuit components. In this way, the special area 15 is exclusive to the previous arrangements the inclusion of the connection points (Fig. 1) was reserved, omitted, and one can overall a considerable achieve greater density of components. In addition, the entire surface area of the base body, required for a certain number of components can be significantly reduced.

'Is in the embodiment of the invention, · as shown in FIG.}

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A circuit component 22 is formed in a base body 20 (ζ.B, single crystal semiconductor material, in particular silicon) of a first conductivity type (for example η conductivity). In the present case, the circuit component 22 is a transistor with a first single-crystal semiconductor base region 2k, the conductivity type (eg p-conductivity) of which is opposite to that of the base body 20, which serves as a collector; In addition, there is a second single-crystal semiconductor emitter region 26, the conductivity of which is opposite to that of the base region 2h (for example n-conductivity). In this way transitions 25 and 25a are formed. On a larger part of the surface 28 of the base body 20, several such components are arranged together with components of other types. In the context of the invention, components of any suitable type can be provided, for example diodes, field effect transistors, metal-oxide-silicon components (MOS transistors), resistors, capacitors, inductors and devices of other types hybrid integrated circuits or thin film type integrated circuits. The circuit component 22 is produced according to the known method of double diffusion and the photographic engraving technique, as described, for example, in US Pat. No. 3,025,589 of March 20, 1962 (jAHoerni).

On the surface 28 of the base body 20 there is a first insulating layer 30 »which, when using a Silicon base body can consist of silicon dioxide, which at the same time or after the formation of the areas 24 and 26 is made. As is known, the layer will 30 used to passivate and protect the components formed in the base body 20, and it serves as electrically insulating layer. Over this first insulating layer 30 is a network of conductive Material. 32, which shows the various components of the

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Circuit connects. The network 32 can with the help of the known photographic engraving technology and be formed by vacuum evaporation, as in the already mentioned U.S. Patent No. 2,981,577. (In the prior art, the ports 16 would be simultaneous with the formation of the interconnection network 32 and over the first insulating layer 30 outside the components 22 can be produced. In this point, the invention deviates from the teaching of the prior art.)

According to the invention, a second insulating layer 3k is arranged over the connections made of conductive material 32 and the first insulating layer 30. The second insulating layer 3k covers both the network of conductive material 32 and the circuit components 22. The second insulating layer 3k can be produced by one of the many known application methods, and there are also many options for the nature of the material. For example, natural and synthetic silicates can be used, heat-resistant metal oxides, mixtures of silica and other metal oxides (natural and synthetic), sated glasses, etc. Such substances can be used as stocks for processes of thermal vacuum application, atomization, vapor deposition and other known Process for applying thin layers are used. The layers produced can advantageously be used as insulating material between the multilevel conductive metal films, for example the connection points 16 and the conductive material 32. Layers that are formed from a supply of the type mentioned are hard, chemically resistant, etchable and electrically conductive. The application of insulating layers of the type mentioned is relatively easy to master in terms of process technology.

In the second insulating layer 3 ^ and the first iso-

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lying rail 30 is an opening 36 through which an electrical connection to the circuit component 22 can be made. The formation of such an opening can be done with the aid of the known technique of photographic engraving and etching. The opening can be worked out with the aid of two etching processes as well as in a single etching process. For example, one can proceed in such a way that a part of the opening 36 is produced through the first insulating layer 30 by etching before the formation of the network of conductive material 32} the corresponding part of a contact 39 which is passed through the first insulating layer 30 can simultaneously be made with the formation of the network of conductive material 32. After the formation of the second insulating layer 3 ^, the remainder of the opening 36 is produced through the second insulating layer 3k in a second etching process. Then the contact 39 is extended over the second insulating layer 3k , and the connection point 16 is formed. The connection point 16 can, together with the remaining part of the contact 39, by vacuum deposition of a conductive metal (e.g. aluminum) over the surface 38 of the second insulating layer 3 ^ be made. Alternatively, however, the opening 36 can also be produced through both layers 30 and 3 ^ in a single etching process. During the vacuum application over the surface 38, the opening 36 would then be essentially filled with conductive material. The geometric shape of the junction 16 is produced by photographic engraving or other suitable metal forming process which removes the excess metal as required. The formation of such ohmic contacts by vacuum application is described in the aforementioned US Pat. No. 2,981,877 (Robert N. Noyce) of the owner of the present property right.

The integrated circuit can be connected to another circuit

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or to an external device with a connection 40 which is connected to the connection point 16 preferably by soldering, by thermocompression or by ultrasonic connection. Care must be taken that any forces that are exerted on the connection point 16 must not exceed a certain maximum value, since an excessive force can lead to a break in the second insulating layer 3k , so that possibly a short circuit between the connection point 16 and the Network of conductive material 32 enters. With regard to the size of the connection point 16, it is necessary that there must be enough space to attach a connecting wire 4o. As a rule, it will be sufficient if the connection point 16 is a

Size from 0.0065 to 0.013 now (10-20 sq. Mils) while for lead 40 a diameter of 0.013-0.05 mm (0.5-2 mils) will be the norm.

As can be seen from Figures 2 and 3, the invention provides the essential advantage that in an integrated circuit arrangement a special area for the connection points in addition to the field of integrated circuits, and that practically the entire area of the Base body for the inclusion of circuit components is available.

A further advantageous embodiment of the invention is shown in Figure k. The base body 20, the circuit components 22 and the first insulating layer 30 in this exemplary embodiment are essentially the same as in the exemplary embodiment according to FIG. 3. The exemplary embodiment according to FIG. K differs from that according to FIG 16 from. When, in the exemplary embodiment according to FIG. K, the network is formed from conductive material 32, a short section 52 is formed from electrically conductive material at the same time. The section 52 is in ohmic contact with

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the emitter region 26 and extends over the first insulating layer 30. The second insulating layer 3 ^ is then formed, as was described in connection with the exemplary embodiment in FIG. 3, but with the difference that a part 50 of the section 52 remains uncovered. The part 50 can be exposed, for example, by applying the second insulating layer 3 ^ · through a temporary mask which is placed over the surface during application, or by using the lift-off or etching technique, such as is used in the USA Patent application No. 509 825 of November 26, 1965 by the owner of this property right. The connection point 16 can be formed by vacuum deposition and photo-engraving in the manner described above in such a way that contact with the part 50 is made. In this way, a connection point is obtained which is designed in the manner of a convolution and is separated from the network 32 by the layer "^ h .

As can be summarized, the particular advantage of the invention lies in the fact that space is saved, which was wasted in the arrangements of the known type, since it was not available for the accommodation of circuit components. The invention has now made it possible to increase the circuit density considerably and also to reduce the production costs by increasing the number of circuit elements per semiconductor wafer. For example, by eliminating 0.127 mm (5 mils) in size pads at the edges of a 1.016 mm (^ O mil) body, the body can be reduced to 0.762 mm (30 mils) in size. This increases the number of semiconductor elements per 6.52 cm (1 sq in) from 625 to 1112, so that the yield per unit area is almost doubled with only a small increase in manufacturing costs.

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The invention is not limited to the illustrated and described exemplary embodiments, but rather it can in any expedient manner within the framework of a professional Actions are changed, for example by using other suitable semiconductor materials, or the materials of the conductive layers and the insulating layers are changed.

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Claims (6)

Claims 1. Semiconductor circuit in which the specified overall scope is miniaturized and in which several electrical components and their connections to or in a larger part of the surface of the base body are arranged, characterized by an insulating layer over it at least a portion of the circuit components and connections and one overlying the insulating layer electrically leading connection point, which one? is connected to at least one of the circuit components and with can be connected to a connecting conductor. 2. Semiconductor circuit according to claim 1, characterized in that that the circuit is designed as an integrated circuit and the conductive connection point dimensioned so large is that a wire can be connected to it * 3. Semiconductor circuit according to claim 1 or 2, characterized in that the circuit is an integrated semiconductor circuit and several connection points are arranged on the surrounding area of the integrated circuit. k. Semiconductor circuit according to Claim 3, characterized in that the connection points are arranged essentially within the area of the integrated circuit. 5. Semiconductor circuit according to one of claims 1-4, characterized in that it consists essentially of single crystal silicon, the insulating layer silicon dioxide is, and the conductive connection point is made of aluminum. 6. A method for producing an integrated circuit according to any one of claims 1-5 »characterized in that that within a basic body several cooperating with one another Scarf do ^ skoinponenten on or in one 009819/088 5 - 1 " - larger part of the surface of a semiconductor body can be formed that a first insulating layer at least partly over the greater part of the surface is formed so that electrical connections on the first insulating layer »wipe at least two of the components be prepared that a second insulating layer is disposed over at least a portion of one of the connections, and that a conductive pad over the »Veiten insulating layer on or over the larger part of the Surface is formed which is electrically connected to at least one of the posture components and lies essentially within the topographical boundary formed by the components and the connections is. 7 «Method according to claim 6, characterized in that the conductive connection point via the second insulating one Layer is laid over in the manner of a fold 009819/0885