DE1474080C - Device for forming the exponent when converting a binary number from fixed point to floating point representation - Google Patents

Description

The invention relates to a device for forming the exponent when converting a binary number from the fixed point to the floating point representation, comparing the binary number with the one by one Bit position to the right shifted binary number to determine the position of the highest bit of the binary number.

In electrical computing devices, it is known (USA. Patent 3,022,006) to process binary numbers in floating point representation, in which a mantissa part referred to as the binary number the actual ^infor-: contains mation while another part referred to as exponent of the binary number, the relative Indicates the position of the arithmetic comma in the information. Mantissa and exponents are saved in separate memory locations. As a result, the computing device is able to work with numbers that are larger than the pure binary numbers that can be stored in the memory locations.

It is known to convert a binary number from fixed point to floating point representation (USA.-Patent 3 037 701, German Auslegeschrift 1 110446), the binary number gradually to the left shift until its highest bit is next to the sign position, and the individual left shifts to count.

In the case of long binary numbers, the left shifts require a relatively long time. The invention is based on the task of converting the fixed point representation of a binary number into the Reduce the time required for floating point representation. The invention solves this problem a device of the above type in that the outputs are one with the binary number and the A plurality of group identifiers and bit identifiers are assigned such that in each case a group of several bit positions of the result number of the half addition is connected to a group identifier and a bit identifier, the Outputs of the group recognizers linked to one another via AND gates and connected to a converter corresponding to the group containing the highest bit of the binary number to be converted, a first order of exponent signals, which forms the higher digits of a multi-digit Represent exponents, and that each of the bit recognizers is the same with the group recognizer Group is connected, that each bit detector is effective whose group the contains the highest bit and a converter for forming a second order of exponent signals according to the position of the bit within the group affects, which reflect the lower digits of the exponent. ·

Further developments of the invention are characterized in the subclaims.

By subdividing the binary number to be converted or the result of its half-addition with the number shifted one place to the right into several groups, each of which has several Bits, all groups can be examined simultaneously to see which of the groups has the highest Bit of the binary number and at which position within this group this bit is located. This will be determines the determination data for the exponent without lengthy left shifts.

FJn exemplary embodiment of the invention is explained in more detail below with reference to the drawing. It shows ■; . · - ■; ■; ■■ - ■ {· '{'; ■ ^"■;,:;. '. ■■■■ ■ ■ .. ■■■' - ■ '

Fig. 1 is a block diagram of a device for . Conversion of a binary number from fixed point to floating point representation, "

F i g. 2 a logic circuit of a stage of a shifting circuit: K; I,

3 shows a block diagram for determining the count word of a left shift or a ίο right shift,

F i g; 4 the link circuit of a group recognizer,

Figures 5A and 5B show the logic circuits a bit recognizer, the group and bit converters and a subtracter.

Example I shows a machine word in the conventional fixed-point position notation, * which comprises a sign position 5 and 35 bit positions with a numerical value, which are identified from 34 to 0 in descending order. ^v

Example I.

A positive number is denoted by a binary 0 in the sign position S and a negative number by a binary one in the sign position S. The fixed point or radix point is located between the sign position S and the bit position 34. In example I, the binary 1 in bit position 32 represents the decimal fraction Ve and binary 1 in bit position 31 represents the decimal fraction Vie. Therefore, the binary number in example I has the Decimal value + ³ Ae.

In the floating point representation, the binary number is shifted to the left until its highest bit position next to the natal point. Shifting the number changes its binary value so that the number is in the radix or floating point notation an expo-

.. must have elements. This exponent has the value

2 ~ ", where η is the number of left shifts required to bring the highest bit off the radix point.

S.
0 34
1 33
1 32 3
0 2
0 1
0 0
0 . ".- ■■■ example II

Example II shows the value + ¹ VKi in floating point representation. In example II, the mantissa has the value '/ 2 +' / 4- ³ A. The exponent which is connected to the mantissa and is stored as a separate word has the value -2, since the highest bit position of the binary number is two places moved to the left. Therefore the numerical value in example II is ³ AX 2-2 or ³ Aj X ¹ U = ■■ ³ / ie. In operation, the means to be described below converts a word from the form in Example I to the form in Example II and generates a binary representation of the exponent.

Example III shows a machine word in floating point representation. The word contains a sign bit S, an exponent consisting of 8 bits and a mantissa consisting of 27 bits: In the floating point representation, the .radix point is between the bit positions 26 and 27. ^{! r} - ^;;> -ti; ~; ; r ν; s

34
O O exponent 0 0 ^: 27.
r ι '■■■ Ό Mantissa" S.
1 0 0 0 6; - ^r 25 ^: - ^: 0

Example III

'Both the expnent and the mantissa are expressed in one's complement. Therefore, a negative exponent for a negative number is the one's complement of the negative exponent for a positive number. Negative exponents indicate that the number has been shifted to the left, to bring them into floating point representation. Correspondingly, a positive exponent is a negative one Number of the one's complement of a positive exponent for "a positive number. A positive exponent indicates that the number has been shifted to the right to make it floating point.

Example ΠΙ shows the value - ¹ It in the floating point representation. Since the sign bit is a 1, the mantissa is negative, and the binary 0 in bit position 26 of the mantissa has the value ^l h = -Va. The exponent has the value 1, but since the sign has a negative value, this value must be complemented to get the value - 1. Thus, the power expression has the value 2 " ¹ or ¹ It. If the mantissa is multiplied by the power expression, then

ao results in the value- ¹ A. ' . '· ■■ - ■ "■'■■> ■ - ■

Example IV shows the value rf ¹ / «in floating point representation. In Examples III and IV the exponent has the same value, but is expressed differently, since the sign of the mantissa is different in both cases.

34
1 exponent 1 I " 27
0 mantissa S.
0 1 I 1 26 25 Ö
1 0 --- 0

Example IV

The in F i g. The arrangement shown in FIG. 1 contains several binary storage registers A, X, D, Ki, K2

.and K 3, a control matrix 25, an adder 1, a normalizing device 3, a subtracter 5, a shift matrix V with the three control levels El, E2 and E3 _? Decoding means 13, 15 and 17 and an instruction generator 19. With the exception of the normalization device 3 and the shift matrix V are all. Elements in Fig. 1 are of conventional construction and therefore need not be described in detail., _. ^

ί * : The instruction generator 19 comprises means which store and decode instructions and issue the instructions for executing the instructions.

The A register is a 36-bit memory register and consists of a set of logic elements that respond to the command "D to A" . The output of the D register is applied to these logic gates via a transmission line 21, and when the command "D to A" is given, the contents of the D register are entered into the / ί register. The /! Register is cleared before a number is entered. -

The output of the ^ register leads to the control matrix 25. The control matrix 25 is connected to various operand sources and, in many operations with arithmetic circuits, serves as a control means which controls the operands in the arithmetic circuits. When converting to floating point representation, the control matrix 25 s only serves as a transmission path between the - ^ - register and a Z register. The output of the A register leads to the control matrix 25, and when the command "A to Y" is given, the value in the A register is fed into the control matrix 25. The output of the control matrix. 25 is connected to the X register: via a transmission line 27; with the command “Y to X” the content of the control matrix 25 is transferred to the AT register. . ,: The D register is also a Registefj-Def comprising 36 bits. The output of the ^ register is connected to the D register via a transmission line 29; When the command "y4, to D (Rl)" is given, the contents of the ^ register are put into the D register, shifting one place to the right. ,,.

The contents of the X and D registers are given to the adder 1 on transmission lines 31 and 33. The adder 1 can consist of 36 bits, as it is normally used in arithmetic operations. The normal output of the adder is not used in the conversion instruction. Instead, the adder generates output signals which represent the result of half the addition (without transfer processing) of the content of the D register to the content of the ΛΓ register. These signals are given to the standardization device 3 on a transmission line 35. The transmission line '35 is only 34 wires because the outputs from the sign stage and the low stage of the adder are not used in the conversion operation. The normalization device 3 determines the position of the highest bit in the signals that occur on the transmission line 35 ^ :: SK v> ~ -'y- ^{: c} -IVv ■ ni.v ;;]; ■■: ■;> * * :; ■ ? Ϊ́ -; ^ ί = \. '

If a number in the X register is via the ^ register to one input of the adder 1 and via the D register, shifting by one place

is placed on the right at the second input of adder 1, then the position of the highest bit of the signals appearing on line 35 corresponds to the position of the highest bit of the number in the A register.

The normalizer 3 counts both left and right shifts. The counting of the left shift comprises six binary bits and represents the exponent of the number in the A register. The count value of the left shift is given via the line 37 to the register K1 ; if the command "Kennziffer an Ä'l"'(Char- + Kl) is given, this count is controlled in the lower levels of the register Kl. Register Kl is activated by the command "Delete Kl". (CLK 1) immediately before entering the counter value of the left shift

The shift matrix is able to shift a number up to 72 places to the right in the circle, but it cannot shift a number directly to the left. A left shift is achieved by shifting to the right and in a circle by as many places as the 72 minus the left shift value. "" Z

The right shift count; which is formed by the normalization device 3, corresponds to 72 minus the count value of the left shift; it is given on transmission line 39 to the seven lower stages of register A'3. If the command "Shift count to K 3" is given, the count value of the right shift is placed in register A "3. Register K 3 is cleared by the command" Clear A3 "(CL A3) immediately before the shift count is entered.

The shift matrix V comprises three levels El, £ 2, £ 3 of logic elements and has no storage facility. A number in the A 'register is always given on line 41 to the input of the first control level El . The decoder 13 'decodes the two lowest bits 00, 01 of the count value in register A3 and generates one of four output signals ΛΌ0, XHl, X 02, ΛΌ3, so that the first control level El after the input number by 0, 1, 2 or 3 bit positions shifts right.

The in F i g. The logic circuit shown in step 00 of the first control level El consists of 4 AND gates 43, 45, 47 and 49, each of which is connected to an OR gate 51 with an output. The AND gate 43 has one input connected to ΛΌ0 and has another input which receives a signal SH-O from the decoder 13. When the decoder 13 generates the signal 5H-0 and the stage ΛΌ0 contains a binary one, AND gate 43 generates a positive output signal which is applied via OR gate 51 to the stage 00 of the second control level El . ■ 55 '

The AND gate 45 has an input connected to X 91 and has another input for receiving the signal SH-I from the decoder 13. If the decoder outputs the signal SH-I and the stage X 01 contains a binary 1, this is AND gate 45 from an output signal, which via the OR gate 51 to the stage. . Reaches 00, the second control level / _(· · · ^ - ;; _..; ^ '* -.> - _^{^;;;>} V ^{JC ;;:} - · ■ - .:.... ..

The AND gate 47 has an input connected to X 02 and has another input for receiving the signal SH-I from the decoder 13. If the decoder outputs the signal SH-2 and X 02 contains a binary 1, the AND outputs Element 47 from an output signal, which arrives at stage 00 of the second control level via OR element 51, j χ: ....

The AND gate 49 has an input connected to ^ 03 and has another input for receiving the signal SH-3. When the decoder 13 emits the signal SH-3 and A "03 contains a binary 1, the AND gate 49 generates an output signal which is passed via the OR gate 51 to the stage 00 of the second control level.

The first control level El receives a number consisting of 36 bits from the X register, and since this number can either be shifted by 0, 1, 2 or 3 bit positions to the right, this control level El is provided with 39 outputs. These outputs lead via a line 53 to the corresponding numbered inputs of the second control level E2.

The decoder 15 decrypts the bit positions 02 and 03 of the register A 3 and generates one of four signals which indicate whether the input to the second control level E 2 should be shifted 0, 4, 8 or 12 positions to the right. Since the second control level E 2 receives an input number consisting of 39 bits and the lower bit of this number can be shifted to the right by up to 12 places, the second control level E 2 has 52 outputs that are connected to the appropriately numbered outputs via a line 55 Inputs of the third control level are placed.

The decoder 17 decrypts the bit positions 04, 05 and 06 of the register A3 and generates one of 5 output signals, which indicates whether the input to the third control level £ 3 should be shifted by 0, 16, 32, 48 or 64 bit positions to the right. The third control level E3 is switched in such a way that a circular shift takes place for those numbers which are shifted under position 71. For example, the input of the point 50 of the third control level £ 3 leads to 5 AND gates (not shown), each of which is switched by one of the output signals from the decoder 17. The shift signal 0 from the decoder 17 controls the input 50 of the third control level E 3 to the output point 50. The shift signal 16 from the decoder 17 controls the input 50 to the output point 66. The shift signal 32 from the decoder 17 controls the point 50 to the output point 25 Decoder 17 controls input 50 to output point 9, and shift signal 64 controls input 50 to output point 42. ^■:;

The output of the third control level £ 3 of the shift matrix V , which consists of 72 bits, is divided into an upper half with the bit positions 35 to 0 and a lower half with the bit positions 36 to 71. The output from the upper half of the control matrix is applied on line 57 to the D register and the output from the lower half of the shift matrix is applied on line 59 to the D register. The "SML to D" command controls the output from the lower half of the shift matrix into the D register, and the "SMU to D" command controls the output of the upper half of the shift matrix into the D register. The D register is cleared by the »Clear D (CLD) command immediately before a transfer. . ..

The "SMU to D" instruction occurs during every conversion operation to put the bits of the .Y register into the D register.

If the instruction requires the conversion of a binary number into floating point representation, in which the The highest bit to the left of bit position 26 in the Z register can be shifted to the right instead of a Left shift may be required. In this case, the low digits of the D register do not remain free. The nine upper bit positions of the D register, on the other hand, are free, they become later with the exponent the converted number is filled.

The exponent is formed by registers K1, K2 and K 3 and a subtracter 5. Each of these registers and the subtracter each contain nine bit positions for the sign and the eight-bit exponents. In the following description it is assumed that the register K 2 is cleared during the conversion operation and contains the count value 0. The register K 2 can optionally be loaded with a constant, predetermined value.

If the number is converted to floating point representation and a left shift is required for this, the counter value of the left shift is controlled by the command “Exponent to Jt 1” (Char - * - Kl) in this register Kl . The sign of the output number in the / 4 register determines whether or not the counter value of the left shift should be complemented before being entered in the code number part of the D register. The sign bit of the ^ (register is given to the command generator 19, and if the sign is negative, the command generator 19 gives the command " Kl-K 2", which controls this difference from the subtracter 5 via the transmission line 63 into the register K3. If the sign of the number in the / 4 register is positive, the command generator issues the command "K2-K1", and this command controls the output of the subtracter 5 on transmission line 67 into register K 3.

After entering the difference in register K 3, the sign of the number in the / 4 register is entered in the highest position of register K3 . The output A 35 from the sign position of the Λ (register leads to register K3 and to the command generator 19. The command generator 19 outputs the command “A3S to ΛΓ3”, which moves the sign of the./4 register to the highest position in register K 3 controls.

The exponent of the number in floating point representation is now in register K 3 and its mantissa in bit positions 0 to 26 of the D register. The command generator 19 issues the command "CL _{D (/ 9} ", which clears the upper nine bit positions of the D register. Then the command generator 19 issues the command "K3 to D ₁ J _n ", which outputs the code number from the register K 3 the transmission line 71 into the D register. The number in the floating point representation is now in the D register. The command generator 19 then gives the commands "Delete A" (CLA) and "D an Α.", which contains the / i- Deletes the register and transfers the number in floating point representation to the yi register.

The counter value of the left shift, which is formed by the normalizing device 3, is not entered into the register K1 if a number is converted into the floating point representation, the highest position of which is to the left of the bit position 26. If the highest digit of the number of signals to be converted is in one of the bit positions 27 to 34, the normalization device 3 generates the signal shift right on the line 61. This signal is sent to the command generator 19 in order to block the commands “Exponent to Kl” (Char- * Kl) and “SML to D” . The command generator 19 issues the command "shift count to K 3", and the right shift count is entered in the register K3 in the normal manner. This count is given to the decoders which control the right shift of the value in the ΛΓ register when it is transferred to the D register.

The right shift signal given by the normalizing device 3 also controls the command generator 19 so that it issues the command "3O to Kl" , which controls the complement of the count value of the right shift from the transmission line 73 into the register K1. The sign of the A register is then scanned, and depending on whether the sign is negative or positive, the command generator 19 issues one of the commands “K1-K2” or “K2-Kl”. In both cases, the resulting difference is entered into register K3 . The command generator then gives the command »Λ35 to K3«, which controls the sign of the ^ [register to the highest position in register K 3 , thereby completing the creation of the code number. The code number is entered in the nine high places of the D register by the commands “CL D _U9 ” and “K3 to Dy ₉ *. Then the normalized number in floating point representation from the commands »Delete A« and »D to A« is entered in the .4 register.

5 6

0 0001011

0 0 0 0 0 1 0

0 0 0 0 1110

Example V

X without shift
D push right vci
HA

The mode of operation of the standardization device shown in FIG. 3 3 is based on the fact that if a number is shifted one binary digit to the right and the shifted number is compared digit by digit with the starting number, the highest digit that indicates a mismatch which is the highest bit digit of the seed number. Example V shows this principle for a positive number. The highest bit of the output number is in the Bit position 3, while the lower bits appear in positions 1 and 0. After moving the Number one place to the right contains the number shifted to the right bits in the places 2 and 0. If the output number is compared with the number shifted to the right, is stored in the Bitstcllcn I, 2 and 3 indicates a mismatch. The highest, indicating a mismatch Digit corresponds to the highest digit of the initial number that contained a bit.

I! In comparison is nothing but the operation

209 626/60

a half addition. For this reason, the half-addition output of an adder is used in the standardization device 3, which is usually present in the computing circuits of a computer. The outputs of registers X and D lead to

Adder 1 that generates output signals on transmission lines 81 to 85. These signals represent that Result of the comparison of each level of the F register with the corresponding level of the D-Re-5 gisters represent.

The result number is divided into five groups, A, B, C, D and E. Table I shows the bit positions of the individual groups.

Table I.

A. B. C. D. E. 35
0 abcdefgh abcdefgh abcdefgh abcdefgh ABC 34 27
00000000 26 19
00000000 18 11
00000000 10 3
00000000 2 0
101

The sign bit is not assigned to any group. Groups A, B, C and D each receive 8 bit positions, for example, and group E three.

With the exception of group E , each signal group is assigned to one of the group recognizers GA to GD . The group recognizer GA receives the half-addition outputs from the bit positions 27 to 34 of the half adder 1, the group recognizer GB receives the output signals from the bit positions 19 to 26, the group recognizer GC receives the output signals from the bit positions 11 to 18 and the group recognizer GD receives the output signals from the bit positions 3 to 10. Each group recognizer is used to determine whether one of the signals applied to its group indicates a mismatch or not.

The group identifier GA (FIG. 4) consists of an AND element 86 and a negative OR element 88. The negative OR element only emits a positive output signal when all inputs are negative. The AND element 86 is connected to the outputs of the stages 27 to 34 of the half adder 1, which belong to the group assigned to the group identifier GA. If the stages 27 to 34 of the AT register match the stages 27 to 34 of the D register, all inputs of the AND gate 86 are positive, and it supplies the positive output signal UR-H. If, on the other hand, one or more stages 27 to 34 of the Af register do not match the corresponding stages of the D register, then one or more bit positions contain a bit, and the corresponding inputs of the AND gate 86 are negative, and the AND- Member 86 emits a negative output signal. This signal is reversed by the negative OR gate 88 and becomes the positive group signal GR-A. The signal GR-A indicates that the highest position of the number to be converted is in one of the bit positions 27 to 34 of the group of bit positions assigned to the recognizer GA.

The group recognizers GB, GC and GD are similar to the group recognizer GA. If, however, one of the group recognizers GB, GC or GD generates a positive group signal GR-B, GR-C or CiR-D , then this signal simply means that one of the bit positions assigned to the group in question contains a bit. Whether or not this bit is the highest bit of the number depends on whether a group recognizer of a higher group generates a group signal or not. Generate z. B. the groups B, C and I) group signals, while the group recognizer GA generates the signal GR-H , then B is the group which contains the highest bit of the number. Four AND gates 90, 91, 92 and 93 are used to determine the group identifier of the highest group, which generates a group signal.

When the recognizer GA delivers the signal GR-A , this indicates that the highest bit is in group A. The UK-H signal is applied to one input of each of the AND gates 90 to 93 to block these gates and thereby prevent the group B, C, D and E signals from passing through. The AND gate 90 also receives the signal GR-B. When the highest bit of a number is in group B , signals UK-H and GR-B are positive, so AND gate 90 produces a positive output. The signal UK-Έ is applied to an input of each of the AND gates 91, 92, 93 to block them. When the highest bit of the number is in group C, the GR-C signal is positive and the TJR-H and UK-Έ signals are positive so that the AND gate 91 produces a positive output. At the same time the signal GR-Z! negative and blocks AND gates 92 and 93.

If the highest digit of the number is in group D, then the signal GR-D is positive, and the signals UK-H, 7ΤΚ-Ή and UK-Z! are positive. Since all inputs are positive, AND gate 92 generates a positive output signal GR-D. The UK-Ti signal is negative and blocks gate 93.

If the highest point de r Za hl i n Gr uppe E is, the signals UK-H, UK-Έ, UKJZ and UK-V are all positive, and the AND gate 93 generates a positive signal GR-E.

The signal GR-A and the output signals from the AND gates 90 to 92 are applied to a group converter 100 which forms the high 3 bits of a number consisting of 6 bits. This number is known as the left shift count and represents the amount by which the number to be converted must be shifted to the left in order to bring the highest bit next to the decimal point. The counter value of the left shift is transferred to register K 1. In the case of a normalization process with a non-floating decimal point, the counter value is the digit factor. When converting to floating point representation, the counter value is the. Exponent if the highest bit of the number to be converted is not in group A.

The standardization device has five bit identifiers

BA, BB, BC, BD and BE provided. These bit identifiers are used to determine the position of the highest bit in the group that contains the highest bit of the number. The bit identifiers ΒΛ, BB, BC and BD each receive seven input signals from the half adder 1. According to Table I, each of these groups contains 8 bits. The 7 upper bits are given to the bit recognizer. If a certain group signal was generated and the highest bit is not in one of the seven higher bit positions of the group in question, then it must be present in the lower position of this group. Thus the outputs from stages 27, 19, 11 and 3 of half adder 1 are not applied to the bit recognizer.

From Table I it can be seen that group B contains only 3 bits. Only two of these bits are given to the bit identifier E. The output from stage 0 of half adder 1 is not applied to the bit detector. If the highest bit is in group E and not in its bit positions 2 or 1, then it must be in bit position 0.

Each bit detector can only generate an output signal if it depends on the corresponding Group signal is excited. Each of the bit recognizers has 7 outputs that correspond to the 7 inputs of the half adder 1 correspond. When a particular bit detector is excited by a group signal, then it is generated he output signals on each output line for all positions to the left of the highest bit.

All outputs from the bit recognizers are given to bit converter 101, the three low ones Bits of shift count generated. The binary value of these three bits corresponds to the number of Place by which the highest bit of the group that contains the highest bit of the number to the left must be moved to bring it to the highest position assigned to the group.

The count value of the left shift, which is formed by the group converter 100, is given to the subtracter 103 as a subtrahend. The subtracter 103 is always connected in such a way that it has the binary equivalent of the decimal value 72 as the minuend input. The minuend is chosen as 72 because this is the number of places by which the number can be shifted from the shift matrix V when shifting to the right. If a left shift is desired, but which cannot be achieved directly by a left shift, it is done by a right shift by an amount of 72 minus the counter value of the left shift. The subtracter 103 carries out the subtraction and forms at its output a binary number consisting of seven bits which represents the count value of the shift to the right which is required to carry out the desired shift to the left.

When converting a number to floating point representation, the number is required Left shift 8 minus the number of shifts that occurred during normalization in fixed point representation required are. In the former case, the comma is to the left of bit position 26 and in the latter Case to the left of bit position 34. A command FP given by the command generator is on the line 105 to the group converter 100, which changes the counter value of the left shift, which was formed by the group converters 100, 101.

If a number is converted to floating point representation and the highest bit of the non-standardized number is in one of the bit positions assigned to group., 4, then the number must be shifted to the right and not to the left in order to move the highest bit to position 26 bring. In order to achieve the correct count of the right shift, the count value of the left shift is formed in the usual manner and given to the subtracter 103. However, the output from the highest point of the subtracter is blocked. An AND gate 107, which receives the selection signal "Group A" when the highest bit of the number is in the group Λ, is switched by the command FP and supplies a positive output signal, which is reversed by a negative OR gate 109 and on the AND gate 111 is given in order to block the output from the highest point 26 of the subtracter 103.

Stage 4 (FIG. 3) of half adder 1 comprises two AND gates 113 and 115 (FIG. 5A), each of which has an output connected to a negative OR gate 117. The output of 117 is reversed at 119 and becomes signal HA-04. The AND gate 113 receives the signals IP and 2503, and the AND gate 115 receives the signals X 04 and D 04. If the bits in stage 4 of the registers X and D are both ones, the inputs to the AND gate are 115 is positive and it produces a positive output which is reversed at 117 and again at 119 so that signal HA-04 is positive. If the bits in stage 4 of registers X and D are equal and both zeros, then both inputs to AND gate 113 are positive and its positive output is reversed at 117 and again at 119 so that a positive output is provided. If the bit in stage 4 of the ΛΓ register does not equal the bit in stage 4 of the D register, then at least one input of each AND gate 113 and 115 is negative and both AND gates produce negative outputs. If both inputs are negative, then 117 supplies a positive output signal, which is reversed at 119 and becomes the negative signal HA -04. The signal HA-04 is therefore only negative if the bits in stage 4 of registers X and D are determined to be different. The other stages of the half adder 1 are the same as those shown.

The group identifier GD comprises seven AND gates 120 to 126 (FIG. 5 A). The AND element 120 receives the selection signal GR-D as an input and the output from stage 10 of the half adder 1 as a further input. The output of AND element 120 is connected to an input of AND element 12t, which receives the output from stage 9 of half adder 1 as a second input. In a similar way, the AND gates 122 to 126 are each connected to one input to the stages HA-08 to FLA-04 , while the second input of each is branched off from the output of the preceding AND element in the series. The output of each AND element leads to the bit converter 101.

The bit converter 101 consists of several negative OR gates 127 to 140, several AND gates 141 to 146, several positive OR gates 147 to 149 and three flip-flops 150 to

152. 127 has five entrances. These inputs are connected to the outputs of the first AND elements in each of the five bit recognizers. 128 also has five inputs that are connected to the outputs of the second AND gates in each of the five bit recognizers. Each of the negative OR gates 129 to 133 receives the outputs from corresponding AND gates of the bit recognizers BA, BB, BC and BD. 129 receives the outputs from the third AND gates of each bit detector. 130 receives the output from the fourth AND element of each bit detector, etc. The output from 127 is reversed at 134 and given to an input of AND element 141. The output of 128 leads to the AND gate 141 and via 135 to the AND gate 142. The output of 129 leads to the AND gate 142 and via 136 to the AND gate 143. The output of 130 leads to the AND gate 143 and over 137 to AND gate 144. The output of 131 leads to AND gate 144 and via 138 to AND gate 145. The output of 132 leads to AND gate 145 and over

139 to AND gate 146. The output of 133 leads to AND gate 146 and a negative one OR gate 140.

Each of the AND gates 141 to 146 has its output connected to 140. Besides, the exit is of the AND gate 141 is connected to an OR gate 149, the output of the AND gate 142 to a OR gate 148, the output of AND gate 143 to OR gates 148 and 149, the output of AND gate 144 to an OR gate 147, the output of AND gate 145 to OR gates 147 and 149 and the output of the AND gate 146 to OR gates 147 and 148. The output of

140 leads to the OR gates 147, 148 and 149. The bit converter 101 thus receives inputs from

the bit recognizer, determines the position of the highest bit in the group, which is the highest bit of the number and forms a three-bit binary number indicating the number of digits to convert which the highest bit must be shifted to the left in order to put it in the highest digit of the relevant Bring group. This binary number appears in the outputs of the OR gates 147 to 149 and is on lines 153-155 to the subtracter 103. The three bits are also stored in flip-flops 150-152. The outcome of this Flip-flops represent the three low digits of the left shift count.

The group converter 100 consists of several negative OR gates 156 to 161, several AND gates 162 to 166, two positive OR gates 167 and 168 and from the three flip-flops 169, 170 and 171.

The selection signal GR-D is applied to 156, 157, 158 and the AND gate 164. The selection signal GR-B goes to 156, 158 and the AND gate 162. The selection signal GR-C is given to 156, 157 and the AND gate 163. The selection signal GR-A is applied to 156. The command FP on the line 105 is given to 159 and the AND gates 162, 163, 164 and 165.

The output of 159 is to one input of AND gate 166 and its second input is on switched the output of 156. The output of AND gate 166 is to the set input terminal of the flip-flop 169 and also connected to stage 5 of the subscriber 103.

The output of 156 leads to AND gate 165, and its output is to an input of each the OR gates 167 and 168 switched. The outputs of 157 and the AND gate 163 lead to 160, and the output of 160 leads to the second input of the OR gate 167, its output the flip-flop 170 and stage 4 of the subtracter is switched. The output of 158 and the outputs from AND gates 162 and 164 ίο lead to 161. The output of 161 is to the OR gate 168 switched. The output of the AND gate 163 is connected to a third input of the OR gate

168 is switched and its output is switched to flip-flop 171 and stage 3 of the subtracter.

The outputs from AND gate 166 and from OR gates 167 and 168 are the three highest Represent the counter value of the left shift. These bits are in the flip-flops 169 to 171 stored until the counter value of the left

ao shift from the command »Exponent to K 1« (Char - * - Kl) is entered in this register Kl . The flip flops

169 to 171 of the group converter 100 and the flip-flops 150 to 152 of the bit converter 101 are cleared immediately after the counter value of the left shift has been entered in the register K1 .

The subtracter 103 subtracts the left shift count from 72 ₁₀ . The low output 2 ° is branched off directly from the output of the OR gate 149 in the bit converter 101. This is because the right shift count must be odd when the left shift count is odd. The outputs 2 ¹ and 2 ^{2 of} the subtracter 103 result directly from the implementation of the outputs of the bit recognizers. The OR element 172 comprises stage 1 of the subtracter 103. This OR element is connected to the outputs of the AND elements 141, 142, 145 and 146 of the bit converter 101. The OR element 173 comprises the second stage of the subtracter 103 and is connected to the outputs of the AND elements 141, 142, 143, 144 of the bit converter 101.

The three low digits of the count value of the right shift, which the subtracter 103 are the result of subtracting the counter value of the left shift from the value 3. Therefore, if any of the three low digits of the left shift count is a binary 1, then it must a borrower from level 3 in subtracter 103 may be given. The outputs of the OR gates 147, 148 and 149 all lead to the OR gate 147, the output of which is on line 175 to the borrower input level 3 leads.

Stages 3 through 6 of subtracter 103 can be conventional. The minuend entrances these stages are connected to voltage sources, so that stages 3 and 6 are consecutive ones and the levels 4 and 5 receive zeros as inputs.

Numerical examples
example 1

It is assumed that the Λ register contains the number shown in Table I. It is also assumed that the exponent of this number is to be formed and the number is to be brought into the normalized non-floating point representation. The instruction normalize TT is given to the command generator 19. The command generator gives the command »A

15 16

to Υ "and then the command" 7 to A "to combine the number and bit converter 101 in the Λ register to the Z register. This is the counter value of the left shift 011110, the command generator 19 then gives the command »A to D, which is the binary equivalent of the decimal value 30. (R 1) «, which shifts the number one place to the right. This is the correct value for the left shift, shifts it and puts it in the D register. 5 since, according to Table I, a left shift of 30 Bi-The half adder 1 adds half and compares närstellen is required to get the highest bit of the corresponding places in the X and D registers. Number to be shifted from bit position 4 to bit position 34. Levels 5 to 34 generate positive outputs. The count value of the shift to the right becomes signals which indicate a match, and at the same time, with the count value of the shift to the left, the stages 0 to 4 generate negative signals that form an io and result as follows: The out of disagreement. Thus, together with the output of the OR element 149 in the bit converter 101 is borrowed inputs of the group identifiers GA, GB and negative, so that the output of stage 0 of the subtract GC is positive. The group recognizer GA generates that 103 is a binary 0. The positive output signal GR-Zi, the recognizer GB the signal GR-Έ of the AND element 146 in the bit converter and the recognizer GC the signal TJR ^ C. 15 line 137 and through OR gate 172 so that the negative outputs from stages 3 and 4 output of stage 1 of the subtracter cause a binary 1 of the half adder that the group is. The AND gates 141 to 144 of the bit converter c.rkcnncr GD generate the signal GR-D. As a result 101 are all blocked, so that all inputs are all inputs of the AND gate 92 (Fig. 3) of the OR gate 173 in the subtracter 103 are negative positive, and the element supplies the positive signal 20 are. Therefore stage 2 of the subtracter produces Gr-DSEL. All other group signals are negative. at the output a binary 0. · All output signals from the bit recognizers The four high levels of the subtracter 103 received BA, BB, BC and BE (Fig. 5) are negative, since the ten as the minuend input the binary value 1001. The corresponding group signals are negative . The bit value 011 generated by the group converter 100 is recognized BD received from stages 5 to 10 of 25 subtracted from this value. In addition, half adder 1 has positive signals, from stage 4 to stage 3 of borrower 1. The outputs of the half adder gates have a negative signal and a positive one. 147 and 148 in bit converter 101 are both positive, signal GR-DSEL, which is transmitted via AND gates 120, so that OR gate 174 on line 175 carries boron 121, 122, 123, 124 and 125 (FIG. 5) , but generated ger signal. Taking into account the Borbcim AND gate 126 is blocked. The positive 30 gers is the output of the four high levels of the output from the AND gate 121 causes 128 a subtracter 0101. The entire binary output of the negative output signal is generated, which the AND subtractor 103 sets the count of the right gate 141 blocks. The shift is effected in a similar way and has the value 0101010. positive output signals from the AND gates The command generator 19 gives the commands "delete 122 to 125 that the negative OR circuits 129 to 35 # 3" and "shift counting to K3" to deliver negative output signals to the counter 132, which lock the value of the right shift in the register K 3 cin-AND-Glicder 142 to 145. Spending negative.

The output of 132 is reversed at 139 and controls the decoder 13 decrypts the 2 lower digits to an input of the AND gate 146. All len of the register K 3 and causes the first control inputs of 133 are negative, so that this member 40 level El of the shift matrix V to a right generates a positive output signal which the shift by two places. The decoder 15 controls the split input of the AND element 146, codes the next two digits of the register whose output signal via the AND element 147 sets the K 3 and causes the second control level E2 to set a flip-flop 150; in addition, it moves 8 places to the right via AND shift. The deco element 148 a flip-flop 151. Thus, the three digits are decrypted the next three digits of the lower bit of the count value of the left shift register K 3 and causes the third control level E 3 equal to 110 to a circular shift to the right by 32 digits. The signal FP on the line 105 in FIG. 5 is. The output of the A 'register is constantly negative, since it is not a conversion process shift matrix V transmitted, so that the transition is now in floating point representation. The negative 50 value in the Af register at the outputs of the third signal blocks AND gates 162, 163 and 164, so control level E 3 occurs in a shifted form. That the signals on lines 180, 181 and 182 bits 010101 in bit positions 5 through 0 of the output are negative. As a result of the positive signal dialing number (Table I) occur in the Auspangsstellcn 35 to GR-D SEL generates 157 on the line 184 a negative 30 of the third control level E3 . The binary zero output signal, and 158 generates a negative output signal on line 55 in positions 35 to 6 of the output number. If the lines in the output points 42 to 71 of the third control circuits 180 and 184 are both negative, 160 delivers level E 3.

a positive output signal, which sets the flip-flop 170 via the AND element. and then the command "SMU to D". The latter BeIf lines 181, 182 and 185 are all negative 60 returns the value 010101 in the high digits of the, 161 generates a positive output signal, wel- D-Registers. Then the command generator gives this via AND gate 168 GR-D SEL of the flip-flop command i> SML to /) «, in order to set the zeros in the output 171. put 42 to 71 in the bit positions 29 to 0 of the /> - Regi-The signal GR-D SEL is reversed at 156 and give sters. The formation of the normalized blocks the AND gate 166, so that the flip-flop 169 completes 65 number.

is not set. Therefore, the three high After the normalization of the number, the command bits of the count value of the shift to the left are 011. generator the commands »Delete" K 1 "and"Kcnn-'Wc η η the outputs of the Giuppemimsetzcts 100 digit to Α.Ί «To display the count of the I. left

17 18

exercise in the KI register. The four high order subtracter commands are 1001 and

K1-K2 then controls the output of KV via the subtrahend input of these stages from the group

Subtracter 5 to register K2>. The register Kl should pen converter 100 is 010. If the subtrahend from

Get a zero value so that the minuend is subtracted into the register and the borrower is on the line

K 3 entered value the counter value of the left shift S 175 is taken into account, the result is

shift is. The command generator then gives the issuing output from the high levels of the subtract

miss »Delete ÄT« and »K3 to X« to activate the digitizer 103 0110. If all seven exits from

factor of the normalized number are taken into account in the lower bits of the subtracter 103, is

Z register. Counter value of the right shift 0110010.

_R. . _Io ίο The command generator gives the commands »Delete

Example l ^ _{3 <<U [ul} "Shift counting at K3" in order to

It is assumed that a binary number is converted into floating point representation after the right shift in the register K 3, and the shift matrix V is controlled. He must. The input into the command generator 19 decoder 13 decrypts the two lower bits struktion reads "normalize FP". The command generator 15 of the count value of the right shift and causes rator 19 gives the commands "A to y", "F to Λ""and the first control level £ 1 for a right shift " A to D (A1) ". The operation of the recognizers GA to bung 2 places to the right. the decoder 15 GD, Biterkenner BA to bE and Bitumsetzers decrypts the next two locations of the REGI 101 are exactly the same as in the previous examples sters K 3 and since both bodies are zero, causing the Therefore, the three lower digits of the 20 decoders are the second control level E 2 for a zero count of the left and right shift, the shift to the right. The decoder 17 codes the next three digits of the register K3

Since this is a conversion into sliding and causes the third control level E 3 to

The command generator shifts 48 places to the right. Therefore he

19 the positive command FP. This command is set to 25, the number appears in the Ä ^ register at the output of the third

of line 105 to group converter 100 shifted control level 50 places to the right,

ben and at Ü159 to block the AND element. The command generator 19 issues the command »SMU

166 vice versa. Therefore the highest point is at D «, which is the upper half of the output signals

Counter value of the left shift controls a binary 0. of the shift matrix in the D register. There-

The signal GR-D SEL is positive so that both 30 through are the binary zeros originally in

Inputs of the AND gate 164 were activated and included in positions 35 to 14 of the X register,

this input a positive output signal on line 182 into the 22 low digits of the D register,

generated. The negative OR gate Ό 161 reverses the- The command generator 19 gives the commands »Delete

This signal converts, creating a negative signal on Lei Kl « and» Kennziffer an Kl « to the count value of the

processing 168 is placed. The signal GR-C SEL must be entered in the register K1 with a negative 35 left shift.

tive and blocks AND gate 163. The negative output The command generator samples the sign bit of the

of AND gate 163 leads on line 180 to the number in the Λ register, and there the sign of

AND gate 168. The positive signal GR-D SEL is number positive, the command generator gives the command

reversed at ü 156 and blocks the AND element 165. K2-KI. Since a zero value is currently in register K2

This makes line 191 negative. If all 40 are stored, the complement of the count value

Inputs negative, then the OR gate 168 generates the left shift entered in the register K3 ,

a negative output signal. The bit position 4 of the counter therefore contains the register K 3 the value 111101001.

The value of the left shift is therefore a binary 0. The command generator gives the command »A 35

The positive signal Gr-DSEL is reversed at 157 by K3 ", by the sign of the output number, so that the signal on line 184 is negative 45, the highest digit of the / ^ register. The K- is. If the lines 178 and 184 both negative registers now contain the value 011101001. The Besind, Ό 160 generates a positive output signal, error generator 19 gives the commands “Delete D ₀ ,” which is used to set the flip-flop 170 via AND and “O” D _Uo «, by which the code number of K3 arrives at link 167. That's why the. Bit position 5 of the 9 high bits of the D register to be transmitted. For counting the left shift a binary 1. If at this point in time the D register contains the normalized number and its exponents are summarized in floating point terms, the count value has the left shift. Then the command generator issues the commands Shift with the value 0010110. "Delete A" and "D to A", around the normalized number

Transfer the three lower bits of the count value of the arithmetic and exponent to the /! Register.

shift are carried by the subtracter 103 to exactly 55. .

formed the same way as in the first example. The example 3

Borrow signal on line 175 is also set to The binary number shown in Example VI is to be in

generated the same way. The minuend input of the floating point representation can be converted.

35 34 27 26 19 18 IL K) 3 2 0

0 OIOOOOOO () () () () () () () () () () () () () () () () 00000000 000

Example VI

For this purpose, the highest digit jn must be the 65 shift, in contrast to the examples i

Position 33 can be shifted until it and 2, where the shift to the left occurred, one

is located at Hitstelle 26. Fine shift be right shift,

around 7 digits is required for this. This must be finer. The instruction »Normalize FP« is attached to the

error generator 19 is given, and this gives the commands "A to Y", "Y to X" and v> A to D (Rl) "as in the previous examples.

Bit positions 33 and 32 of the half adder sample mismatches and provide negative outputs. All other outputs of the half adder are positive. The negative signals are given to the recognizer GA , and the positive signal GR-A SEL is generated. In FIG. 3, the signal Gr-A is negative and blocks the AND gates 90 to 93.

In Fig. 5, all outputs from the bit recognizers BB, BC, BD and BE are negative, since the corresponding group signals are negative. The first AND element of the bit memory BA supplies a positive output signal, since the position 34 of the half adder 1 generates a positive output signal. This signal occurs on line Aa , is reversed at Ό 127 and again at Ό 134 and controls an input of AND gate 141. The second AND element of the bit detector BA generates a negative output signal, since the output from the bit position 33 of the half adder 1 is negative. This signal appears on the line Ab. All inputs of the element Ό 128 are negative, so that it generates a positive output signal which controls the second input of the AND element 141. The output of the element Ό 128 is reversed at Ό 135 and blocks the AND element 142. The other AND elements of the bit detector BA supply negative output signals which are applied to the negative OR elements 129 to 132. Since all inputs are negative, the negative OR gates emit positive output signals, which are initially reversed and then sent to AND gates 143 to 146 to block them.

The left shift count can be disregarded as it is during a conversion are not used in floating point representation, in which a right shift is required. The right shift count is calculated as follows. The AND gate 141 of the bit converter 101 generates a positive output signal because both inputs are activated. This signal reaches line 155 via AND gate 149, so that the output of stage 0 of subtracter 103 is a binary one is. The output of the AND gate 141 also runs through the AND gates 172 and 173, so that the output signals from stages 1 and 2 of subtracter 103 are also binary ones.

All three outputs from group converter 100 are binary zeros. The signal GR-A SEL is positive and is reversed to disable AND gates 165 and 166 at Ό 156. The signals GR-B SEL and GR-CSEL are both negative, so that Ü157 generates a positive output signal which is reversed at Ü160. Since signal GR-C SEL is negative, AND gate 163 is blocked, so that the signal on line 160 is negative. The signals GR-B SEL and GR-D SEL are both negative, so that ü 158 generates a positive output signal which is reversed at ü 161 and becomes a negative signal on line 190. Therefore, the outputs of AND gates 166, 167 and 168 are all zero.

The four high digits of the subtracter 103 receive the value 101 as the minuend input and as Subtrahend input has the value 0000. Furthermore, the positive output from OR element 149 transfers OR gate 174 on line 175 and becomes a borrower signal. Therefore the outcome is the four high stages of subtracter 103 1000, and the total output of subtracter 103 is 10000111.

The output of the subtracter 103 must be modified to get the correct count of the Create reverse shift if a right shift is required for conversion to floating point representation is required because the next bit is the

ίο Number to be converted in bit positions 27 to 34 is located.

The positive signal GR-A SEL (FIG. 3) is given to one input of the AND gate 107. Since this is a floating point process, the signal FP on line 105 is also positive, and AND gate 107 generates a positive output signal which is reversed at Ό 109 and blocks the output from the highest point of subtracter 103. This will make the right shift count in

so changed the binary value OOOOll 1. The command generator 19 issues the commands “delete K 3” and “shift count to O” in order to enter this value into register K 3 , where it can control the shift matrix V.

The decoder 13 scans the two low digits of the register K3 , and since both digits contain binary ones, the decoder 13 supplies an output signal which causes the first control level Et to shift three digits to the right. The decoder 15 scans the next two locations of the register K3 and generates a signal which causes the second control level El to a shift by four positions to the right. The bit positions 4, 5 and 6 are scanned by the decoder 17, and since all these bits are zeros, the decoder gives an output signal to the third control level E 3, which causes a zero shift to the right.

The command generator 19 gives the commands “Loosen D” and “SMU to D”, whereby the upper half of the output signals of the shift matrix V is controlled in the Z) register. As a result, bits 36 to 7 of the output number are placed in bit positions 28 to 0 of the D register. The highest position is in bit position 26 of the D register.

The output of AND gate 107 (FIG. 3) becomes the right shift signal, which is on the line 61 appears. This signal is given to the command generator 19, and it prevents this

gives the commands "SML to D" and "Identifier to K 1". In response to the signal on the Leiturig 61, the command generator 19 gives the command "K3 to Kl", which controls the complement of the value in K3 in the register Kl.

The command generator 19 now scans the sign of the output number in the / (register, and since this sign is positive, the command generator issues the command "K2-K 1". This command controls the content of the register K1 via the subtracter 5 into the register K 3. This register now contains the number 000000111 consisting ^{of 1) bits.}

The command generator 19 then gives the command "Λ35 to O", whereby the sign of the output number is moved to the highest position of the register K3 . K3 now contains the code 000000111.

The command generator 19 gives the commands “delete /) i /“ ”and “ Ki to D _{f; il} ”, which do nine upper bits

of the / ^ register and enter the exponent. The normalized floating point number and its exponent are in the / ^ register. "The command generator now issues the commands" Delete A "and" D to A ", which transfer the normalized number and its exponent to the / 1 register.

The invention is also suitable for a computer system where the exponent of the number in the form of a prime has a voltage. The bias can be added to the exponent by entering its value in the register KI during the conversion.

Claims (6)

Patent claims: 1. Device for forming the exponent when converting a binary number from the fixed point to the glcitpunktdarstcllung by comparing the binary number with the one bit position to the right shifted binary number to determine the 1 .agc of the highest bit of the binary number, thereby geke η η ζ cich net that several group identifiers (GA, GB, GC, GD) and bit identifiers (IiA, IiIi, IiC, BD, Uli) are assigned to the outputs of a half-adder (1) fed with the binary number and the binary number shifted to the right by one frame, that in each case a group of several Bilstcllen of the result number of the half-addition is connected to a group identifier and a bit identifier, the outputs of the group identifiers (GA, GIi, GC, GD) linked to one another via AND gates (90 to 93) with a converter (100) are connected, which, corresponding to the group containing the highest bit of the binary number to be converted, forms a first order of exponent signals which the higher digits e ines multi-digit exponent, and that each of the bit recognizers is connected to the group recognizer of the same group in such a way that the bit recognizer whose group contains the highest bit and a converter (101) for forming a second order of exponent signals corresponding to the position of the Affects bits within the group that represent the low digits of the exponent. 2. Device according to claim 1, characterized in that the number of group identifiers (GA, GB, GC, GD) is one less than the number of groups. 3..Einrichtung according to claim 1, characterized in that the group recognizer (GA, GB, GC, GD) consists of an AND element (86) with a downstream negative OR element (88) from which complementary signals are output on two lines and that the second of these lines is linked to the first line of the group identifier of the next lower group by means of an AND gate (90 to 93). 4. Device according to claim 1, characterized by a shifting device (F) which is suitable for shifting a binary number by η bit positions to the right, a subtracting device (103), one input of which is the constant value (N) and the other input of which is the exponent , ie the count of the left shift, which is required to place the most significant bit of the number to be converted next to the sign bit, the difference produced by the subtractor (103) reproducing the count of the right shift, and control devices (13, 15 , 17), which cause the shifting device (F) to carry out a shift corresponding to the difference generated by the subtracter, after which the highest characterizing bit of the binary number appears in the bit position adjacent to the sign position. 5. Device according to claim 4, characterized in that the control devices of the Displacement device (F) comprise a plurality of decoder (13, 15, 17) which differ from one another Bit positions of the count value of the right shift generated by the subtracter (103) to initiate evaluate shifts of varying magnitude. 6. Device according to claim 5, characterized in that in the absence of a group signal from the group detector (GA) for the highest group of bit positions of the result number of the half adder (1), the count of the left shift is entered in the bit positions of the highest bit group in the memory. For this purpose 2 sheets of drawings