DE1449411C - Method and circuit arrangement for sequentially reading out several unequal words or word parts which contain bits corresponding to one or more search bits from an associative memory - Google Patents

Description

The present invention relates to a method and a circuit arrangement for sequential Reading out several unequal words or parts of words, the bits corresponding to one or more search bits contained, from an associative memory with a bit memory element matrix laid out in rows and columns, the lines of which are each able to store a word containing a number of bits and their columns each have a plurality of place values that are the same as the bit storage elements in all Rows leading column conductors contain, where

a) one or more columns the search bit or! the search bits and

b) all columns of interest are queried.

Associative or content-addressed memories are known. They contain a matrix of in columns and storage elements arranged in rows. An information item (word) is stored in each line. The memory is queried by adding the bit or bits of a "search word" to one or more Columns of memory. There may be one or more words in memory that contain match the search term. This means that a stored word corresponds to a search term that those bits of the stored word that are in the bits of the search word Columns are each equal to the bits of the keyword. The memory can be, for example a read-only memory, e.g. B. with diodes as storage elements, a cryoelectric Memory or a magnetic core or transfluxor matrix, act as they are all known per se. Two types of diode read-only memories, to which the invention can be applied, for example, will be described below. At a of these embodiments, which in their nature has already been proposed, the binary value becomes "0" or »1« due to the position of the coupling element (e.g. diode) with respect to one of two assigned to a bit position Output lines shown, as it is also known per se for read-only memories.

To get several unequal words corresponding to the search term one after the other from an associative To read out memory of the type mentioned at the beginning, one must use a query program the query scheme for a given step through the scheme and the results determined of the previous step is determined, which effectively creates a "decision pyramid" receives. In fact, one must one after the other those Africa drivers who were originally in the inactive state are, according to such a scheme, in the active state, which emits one of the two binary values switch that the ambiguities that result when several words corresponding to the search wordT are stored, eliminated and each of the words originally selected by the search term isolated and is read out individually *. The value of the particular query program mainly depends on the speed with which all answers (churned Words) can be read out, as well as the circuit complexity required for this.

In a known method ("IRE Transactions on Electronic Computers", December 1961, P. 718 to 722) a relatively simple Atisle.seschaltimg is used for each query step only indicates whether one or more words have been selected or not. The one based on it Inquiry process has the following disadvantageous peculiarities: First, you have to get an answer read out, all query drivers must be in the active state and it must be indicated that a or several words are selected. For example, if a single word has been chosen, one however, a large number of query drivers are still in the. is inactive state, so must before the word

ίο can be read out, all of these drivers in be switched to the state corresponding to the selected word, which of course is a considerable one Time expenditure means. Second, it can be that many query steps are run through in which not a single word is isolated, d. H. there is no indication that a corresponding word has been found, which means an additional waste of time.

Another known method ("IBM Journal", January 1962, pp. 126 to 136) works with something more complicated arrangement in which the readout circuit indicates three possible states, viz that no corresponding word is chosen, that a word is chosen, or that several words are chosen are. With the additional circuitry of a word driver per word and one of the number of bits A corresponding number of sense amplifiers per word can be saved considerably in terms of time by Whenever it is indicated that a word has been selected, the corresponding word driver is activated and read out the entire word immediately, d. H. perceived by the sense amplifiers, and even if some of the query drivers are inactive. The application The query process resulting from such an interpretation circuit has the following disadvantageous peculiarities: If at a given step e.g. B. two words have been chosen, a large part of the query

• However, the driver is in the inactive state if the inactive drivers continue from left to must be switched to the right, if the two words, for example, only in the rightmost Bit positions are different from each other, the considerable time that is needed to be expended all inactive drivers one after the other in those corresponding to the identical bits of the two words To switch the state before the ambiguity is only removed in the last digit and a response is read out can be. Furthermore, it can again happen that many query steps are run through, where no words are chosen.

In both known methods, it can also happen that in several successive Steps the same word or words are isolated. In addition to this, in both cases the number of steps to be run through depends on the number of bits per word, such that at As the word length increases, the number of steps required and thus the time required for the query process elevated.

The invention is based on the object while avoiding the above-mentioned disadvantages of the known Methods to specify a method and a circuit arrangement by means of which from the associative memory all the respective

gen search word corresponding information words can be isolated and read out, namely preferably in a predetermined, ζ. B. the number word the order of the words, where-

with the number of required query steps significantly reduced compared to the known method should be.

According to the invention, this object is achieved in a method of the type mentioned at the outset in that, in the event that the query according to step b) results in a signal X in at least one column,

c) a signal Y is fed to one of these columns and step b) is repeated,

. c ') this step c) is repeated until the query no longer results in a signal X in any column,

in the event that the query according to b) or c) or c ') results in a signal X in none of the columns,

d) the relevant word or the relevant part of the word is read from the memory,

e) that following step d) for the case that there is still an interrogation driver which emits the signal Y. is present, this driver is switched to a signal Z and the query according to step b) is repeated in addition to the reading according to step d), according to the query result of step b) before the Step d) if necessary, steps c) or c ') are carried out,

e ') that this step e) is repeated until there is no longer an interrogation driver emitting the signal Y , and then the switched-on Z signal drivers are switched off, with

Signal "Af" on the presence of two or more unequal words having bits corresponding to the search bit or bits or word parts indicating signal (in the case of two conductors per column one signal, which consists of one bit "1" each in both column conductors),

Signal “Y” a signal corresponding to one bit of one value (e.g. “0”) (in the case of two conductors per column, a signal consisting of a bit “0” in the first and a bit “1” in the second conductor exists), and
Signal »Z« is the signal opposite to signal »Y« and corresponding to a bit of the other value (e.g. »1«) (in the case of two conductors per column, a signal consisting of a bit »1« in the first and off a bit "0" in the second wire) means.
This method has the advantage over the known methods that every word found which contains bits corresponding to one or more search bits is read out immediately. It is also not possible for the same word to be found in two successive searches. If there are several words that correspond to the search term, one of these words will be determined when the query is made. Finally, the number of interrogations required to read out all the words corresponding to the search word is independent of the size of the memory and the number of bits per word, namely at most Im- 1, where m is the number of words corresponding to the search word in the memory . The known methods require considerably more steps, and the number of steps also depends on the length of the word.

A further development of the present method for reading out the words or parts of words in a Sequence corresponding to their numerical value from a memory, in which the position values of the bit memory elements are in a row from left to right decrease, is characterized in that the columns, starting with the leftmost Column in which a signal "Λ" "was previously determined, a signal" Y "is fed in sequence and that the columns, starting with the rightmost column, that of the previous A signal "Y" was fed to step, the signal "Z" was fed in sequence will. .

A circuit arrangement for carrying out the present method is characterized according to the invention that with each column a reading and interrogation circuit with a driver stage έ connectable to the column conductor is coupled, which, if the column in question is to be controlled with a search bit, for the entire duration of the readout process is switched to the active state that emits the search bit, while when the relevant column is a column to be queried and by the reading stage connected to the column conductor during the presence of the. Search bits Signals which in this column indicate the storage of at least one bit of one value and at least one bit of the other value in the words or parts of words corresponding to the search bit or bits are determined, the column with signals under the control of a logic stage Controls »Y« and »Z« according to the respective query program.

In the following, embodiments of the invention are explained in more detail with reference to the drawings, it show ' · .

F i g. 1 a to Ie circuit symbols used in the following Wiring diagrams are used,

F i g. 2 a circuit diagram of one of its kind already proposed associative read-only memory matrix to which the invention can be applied,

F i g. 3 shows a detailed block diagram of some control stages of the read-only memory drive circuit, F i g. 4 is a block diagram showing the interconnection between the various logic levels of the Control stages of the memory according to FIG. 2 illustrates

F i g. FIG. 5 is a detailed block diagram of one for each column of the memory of FIG. 2 belonging logical level of F i g. 4,

F i g. 6 'is a schematic circuit diagram of the driver circuit 20 in FIG. 5, each consisting of a transistor stage exists for each of the two conductors in the relevant column,

F i g. 7 a and 7 b are block diagrams that illustrate how the logic levels of the memory are interconnected in different ways be able, .

8 is a schematic circuit diagram, partly in block form, of another embodiment of a Memory to which the method according to the invention can be applied,

F i g. 9 is a block diagram of a group of. Column conductors in the memory according to FIG. 8 belonging logical levels,

FIG. 10 is a block diagram of the logic levels that make up a single conductor / column conductor group / in FIG. 8 belong

• ■ ■. 5 · .. '. ■■ ■ - ..'; . 6th

11 is a block diagram showing that the interconnection is this single bit scanned in a column

between different logical levels in the memory "zero", the scanning result of this column is 0.1

f i g. 8 illustrates (a "zero" in conductor α and a "one" in conductor b).

12a and 14b show a functional diagram which shows several content-addressed memories decrypted with the search word via the query program for a 3-4 code matching words or parts of words in the memory, then in at least one column both . _: '' ν the bit "one" as well as the bit "zero" scanned,

In the following description is arbitrary unless these words are the same, and it

assumed that a positive signal from one column appears in this one, possibly also in other columns

given value. exceeding size in each case the io "scanning result 1.1. If no match is determined-

Binary digit "one" and a given quantity superposed, this is expressed in the fact that in no column

increasing negative signal, the binary digit is sampled one bit, and consequently the sampling

Represents "zero". For simplicity, the occasional result is 0.0.

borrowed instead of an electrical signal transmitted to a second type of erfln block, discussed later or a logic level is fed from 15 storage devices to be controlled according to their content The individual columns each consist of the »Eins« or chermatrix supplied to the relevant level "Zero" can be spoken. a group of column ladders. The individual lines

In the figures, both uppercase letters len each store a word that consists of several bitais and lowercase letters for the representation of groups. Signals embodying binary digits are used in each case with two such bit groups. 20 represent a “character”. Each bit group contains a, for example, k can represent the binary digit “zero” or the “one” bit, while the remaining bits all represent “zero” binary digit “one”, with Tc being the complete . In the case of a special kind of ment of k which is explained here, means. In some figures, the upper / fixed-value memory matrix consists of consecutive * letters or lower-case letters at the bottom right with the following bit groups, the first group of indices each being provided. In general, although not four bits, the second group of nine bits, the third always, such an index denotes the stage, the group of four bits, the fourth group of nine bits, the binary digit in question is supplied. Is it, etc. This type of encryption is referred to as z. B. around the level / and leaves a signal k 4-9 code, since each group of four bits, this level in the direction to the right follows by a group of nine, embodies a character, ßenden level, then this signal carries the The invention can, however, also be applied to such spinning & ,, ·, _jV. The signal k entering stage i is chermatrices which are denoted by other terms kj . encryption, for example a 3-4 code, a

In some cases, letters in Boolean 5-7 code etc. will work. -

Equations used to describe how the stored "word" is supposed to mean the entirety relevant circuit to describe, for example 35 or a part of the stored in a memory line wise in Fig. la to Ie. In these figures the information is to be labeled. The number of Spalfür the elementary logic circuits in the memory determine the number of bits in the various other characters used word symbols. Such a "word" can be proportional shown. Fig. 1 a shows an inverter, Fig. Ib a long one and, for example, a whole "sentence" AND gate, Fig. Ic a flip-flop, Fig. Id a 40 or a complete, e.g. a disease-or gate and Fig. Ie an AND gate with story or the name, the address, the Policencinem his input number, the premium due date, etc. of a manufac- turer. correspond to the secured containing data set. . According to the method according to the invention, if in the present case it is said that stop-addressed memory matrix to be controlled, which 45 multiple words are queried from the memory, For example, implemented as a diode fixed-value matrix, this should mean that the content of several feeds can is laid out in columns and rows. It reads cherzeilen.

it should be arbitrarily assumed that the individual The driver stages, i.e. those stages which

Store one word at a time on each line. For the first, control the columns with the search bits, each

Type of memory matrices discussed here (the one in FIG. 2 50 because it is in the active or inactive state. And

shown) each column consists of two conductors, although one driver stage is inactive when it is not

those on the left with λ and the right with & denotes a signal representing a binary bit in the connected

is. The memory matrix is queried by feeding its column conductor. It is in this state

certain columns with certain, d. H. Search bits to the relevant driver stage practically from theirs

controls. A column 55 column conductor is »switched off«. An active driver stage

with a "one" by connecting the conductor α with a can be "original" or "non-original". "Original"

"One" and the conductor /> with a "zero" should in the present case be a driver stage that

beats. Correspondingly, a column is loaded with a search bit and its corresponding

"Zero" by loading the conductor α with a "zero" -relating state during the entire interrogation

and the conductor h controlled with a "one". Is kept unchanged in the 60 of the memory. "Non-original"

Store only a single one with the search word matches - is a driver stage. which according to the respective, contain the correct word or part of a word, abfrace program to be discussed below in this way, when the not with search is scanned, a "1" or a "0" is found in the associated column bits A single bit conductor sends only a single bit conductor to the activated columns. The state of this driver stage can true noirim-ii. Is it in the just-under-65 changed during the query of the- ' asked for a "one" on that single bit, art. that it delivers a "1" instead of a "0" or so the scanning result 1.0 appears in this column reversed or that it is reversed into the inactive state (ciiie »F-ins" in the ladder and a »zero · 'in the ladder /»). Is switched.

Fig. 2 .. ven voltages in columns 3, 4 and 5 as well

The in F i g. 2, the structure of which has already been proposed for the positive voltages in columns 1, has seven rows and. and 2, which are filled with the search term, true, five columns. This simple execution is here only the perceived word, which at the same time is chosen from the for the sake of clarity; represents a data word read out in 5 memories means that in practice such a memory matrix can look very much like 11001. To this extent, this is a simple example and can be much larger. The individual columns each have just one word in the memory with the search word divided into two conductors α and 6, while the individual lines speak.

each consist of only one conductor. In the second example chosen here, intersections between the columns and rows should again be assumed that the search word consists of two, one diode each, either the column bits and is fed to columns 1 and 2, conductor α (which is a stored "one" corresponds) The search word should, however, have the value 0.1. At or on the column conductor 6 (which corresponds to a stored hand of an examination, similar to the "zero" indicated above) with the relevant row conductor; it can be shown that the memory three is never, however, both column conductors α and 6 contains words corresponding to this search word, namely connected to the row conductor. The diodes Hch carry the words in lines 2, 3 and 5. In addition to symbols showing their position in relation to one, the memory during the time when it denotes the relevant line or column to which the search word is assigned is to be scanned , then 0,1 becomes symbols a, b, where α refers to the left column and 6 in column 3 and 1,1 in columns 4 and 5 are true to the right column. For example, 20 is taken. A 1,1 in at least one column indicates the between the column conductor 1 α and the row that more than one of the stored words denotes the conductor 1 connected diode with Ia-I. Match with search term. In the case of the two memory matrix shown here, the anode is each game there are three such different words,
connected to the line conductor; you swap each- The way in which these three match the "search word."

but the polarity of the operating voltage source, so 25 corresponding words must be taken out of the memory you reverse the polarity of the diodes accordingly. fetched is in the program or command

All line conductors are generally illustrated by means of resistors 10 (program overview A at the end of the bean, a common terminal 12, which is positive spelling). First, voltage is connected. For the content-addressing column furthest to the left, in the 1.1 verified query, the search word is taken via a collective 30, controlled with "zero". The driver stage that takes this lead 14 to a circuit 16, the driver stages, is referred to as "non-original zero" logic stages, Lcscstufcn and SchaltGtufcn cnihäli. In the present case, that is the furthest. The stages mentioned will be explained later in the left column with 1.1 in column 4. In the case of charging, they will be explained individually. You have the task of sending the search word into the memory of this column with a "zero" and a negative voltage from 35 conductor Aa. As a result of the data word or words already in the memory which correspond to the unlocked diodes 4a-2 and 4a-5, the hitherto relevant keywords will be wholly or partially 'positive lines 2 and 5 now negative, so that they can only be read out. The data word or words read out in line 3 remains a positive voltage. These appear on the bus line 18. Positive voltage is applied across the diode 5 6-3 in the

The sequence of the content-addressed control 40 column conductor 5 & coupled, and in column 5 is the memory matrix should be perceived using two examples as a 0.1.

will. In the first example, the search term should be. Since there are now no more columns in which there are 1,1 two bits which appear in columns 1 and 2, it is indicated that the first output word is conducting. Let the two bits correspond to that which can be obtained. The first two bits in the above-mentioned one-bits and .45 output word correspond to the bits of the search word, thus by the representation (1,0); (1.0) marked - namely 0.1. A net appears in columns 3 and 5. The "one" in column 1 unlocks "zero". The same bit appears in column 4, the diodes 16-2, tb-3, 16-4, Ib-S and 16-7, since this is fed in, ie a "zero". The entire column conductor 16 becomes negative while the diode read out word is therefore called 01000, which is locked in the Ia-I and Ia-6, since the column 50 corresponds to row 3 stored word,
head la becomes positive. The next step is that you get into column 2. The next step is that you

"One" unlocks the diodes 26-4, 26-6 and 76-7 furthest right column, the one non-original, and locks the diodes 2ö-1, 2 a-2, 2 a-3 and 2 a-S. "Zero" driver has, with a "one" controls. in the

With locked diodes Ia-I and 2a-1 , this is column 4 in the present case. Driving with row conductor 1 a positive voltage. Lines 2 55 of a "one" are called the relevant column with 1.0 to 7 as a result of the current flow through the gap. As a result, the diode 46-3 is latched, 16-2, 16-3, 16-4, 16-5, 16-7 and 26-4, 26-6, so that row 3 becomes negative. Lines 2 26-7 are negative again, so that lines 2 to 7 together and 5 do not carry negative voltage through diodes with negative columns Hch. The conductor pairs of the ^{v are} coupled so these rows stay positive. Columns 3, 4 and 5 are all connected via a coupling via diodes 56-2 and 5a-5 to the measured impedance in block 16 on a negative result that a 1.1 in column 5 is read.
Tension value brought back, but something the next step will be the furthest left

is less negative than the column in rows 2 to 7, in which a 1; 1 appears (in the present apparent voltage. Column 5 is the only case with columns 3, 4), driven with a "zero". Da- and 5 connected diodes therefore conduct the in row 1, 65 through, the signal .1,1 in column 5 changes to 0.1, ie die.Dioden 36-1, 4b _r l and Sa-I. Positive voltages and, since otherwise no 1.1 appears in any column, voltages occur in the column conductors 36, 46 and 5 a .., “a” - “further answer, in this case 01010” occurs. The reading levels in Bleck 16 take this positive (the word in line 2), recorded.

Next will be the rightmost column. At a practical issue to be discussed later a non-original "zero" driver (column 5) leading form the "switch" is in reality a instead with a "one" through and the part of the driver stage itself. The switch can release Answer .01011 received. Since no non-original neither through the logical levels, such as schematic "Zero" drivers are more present, the 5 is indicated by the dashed line 28, or by Process finished. the incoming search bit, as shown schematically by the

In the query process described above, dashed lines starting from the driver runs 20 were valid

it, three stored words, which are indicated along the search word line 30, are controlled. This will be

speak, grasp. To get these three words from the ter in connection with the driver stages in one

Reading memory is a five-step process. io will be explained individually.

The steps for registering the answer are done In the present case, as explained above, a

Simultaneously with the control steps and the driver stage to which a search bit is applied,

not included, since they are no longer a particular age as the "original driver" who

take vall. It can be shown that the general column continues to drive, with the switch

my case the number of closed for the readout of »5 24 and thus the driver stage to the

m words from the memory required steps corresponding column remains switched on.

2in— 1 is. If the driver stages 20 do not receive a search bit

Bc-i in the example explained above are the conditions, they can be through the manifold 36

Keyword corresponding. Words in the memory in the connected logic levels 34 are controlled

Lines 2, 3 and 5. However, these words are used in the 20th den. The logic stages 34 also deliver over

Sequence 01000 (line 3), 01010 (line 2), 01011 the bus line 38 signals to other logical study

(Line S) read out. The words read out are open and received via the bus 40 Si

ordered according to binary counting, d. i.e., the word gnale from other logical levels. Furthermore received

the lowest value is the first, the word next to the logic level signals from the reading levels

higher value as the second and the word highest 25 42, which in turn is the perceived output word

The third value brought out. It can be shown that via a gate circuit 44 to an external switching

in the interrogation process described, the words processing, for example the buffer level of a memory

regardless of the place where they deliver stored. The gate circuit 44 is through the Iogi- ·

are read out in this predetermined order, see stages 34 controlled via line 45,

will. There is therefore no time-consuming sorting process

gear needed. The words from the memory can be controlled by a timer 46. The timer

rather also in the reverse order, ie in the generated pulses CPl, CPI and CP2>, which over the

Read out the sequence of decreasing numerical values. This bus 48 joins the logic levels 34 of the column

happens by z. B. the order of the An 22 and the logical levels of the other columns of the

Control of the columns or the original to 35 memory,

would take the quantities "zero" and "one" Fi2 4 with regard to this

embodied tensions changed. · .....,. ,, ...

While in the above examples the search word F ¹ S- ⁴ ™ & d * interconnection between the two bits fed to columns 1 and 2 are different logical levels of the storage unit. Instant, the search term can be any number 40?. ^er ^ ¹ '" ^{6 d} , ^er Τψ! is ^{located s} ' ^ch f' ^ne \ ° ^ f ^he . ? ^{on &} of bits up to the maximum number of bits in a memory ^{ "? ^the ' ^S P ^al f ^e '. d- none of the columns of memory. ■ word be composed of existing bits. Furthermore. ^{D. ies6} logic stage is for the logic stages can be the Suchbits any column of the storage ^{dl, e. S} P ^aIten '+ ¹ ^ ¹ T ¹ connected. _> In the same chers forward. This is important because many ^We i ^se E ^{ach S} P ^{Aue D6S, 8} P ⁶ I ⁰ J ^{16 "|.} '° ^{IS.?' He} various criteria by which it allocated to the storage stage _4S The. is switch 24 (F 1 g. 3) the cheri persists for extract desires are possible. in each column are m F1 g. 4 not shown. wah FaIIe a memory which Kraftfahrzeugzulassungs-, ^rend Fig. 4 not in detail explained , saves numbers, it can happen ^{, for example, it can mm} , ^better understanding of F1 g. 5, that only the last two or three or any-
another combination of digits or characters 50 rig.

the approval numbers are known and despite- Fig. 5 shows details of a logic level,

it is desirable to have all these known Zif- z. B. Level 1. The levels / + 1, i - l , etc. are

remote or with the approval number corresponding to level 1 and therefore not subject to

mcrii to read. In the case of a memory, the informa- tion is shown. The heads i _a and i _{b of} the column / er

Actions on insurance policyholder stores, 55 appear at the top right. You are via a switch 24

it may be desirable to communicate information accordingly with the driver stage 20 and also directly with the

linked to the policy numbers or the age of the insurance sense amplifiers 50 and 52,

or the due dates of bonuses etc. The outputs of the sense amplifiers 50 and 52

to read. long via inverters 54 and 56 to AND gate 58

'; .. ·· ..:. Fi ß 3 ' ^{6o and} also directly to the AND gate 60 .. In addition

'The output of the amplifier 52 arrives on the one hand

.Fig. 3 shows the stages of the input block of the AND gate 62 in greater detail.

16 for a column of memory. The AND gate 60 is connected to the control terminal 5 of the

first of all to the driver rstu.fcn 20, which is connected via a 'flip-flops 64'. The 1 output signal X ₁

Switch 24 is connected to column 22. 65 of this flip-flop reaches one input of the Undliönncn. The 'gate. 66 shown here as a mechättificher switch and on the one hand the input of the OR gate

In practice, switches can work fine with transistors, 68. A second input signal £ _; of the AND gate 66

Electronic switches fitted with diodes or the like are derived from the inverter 70. .

The output of the AND gate 66 arrives at the control terminal 5 of the flip-flop 72 via the OR gate 83. The 1 output signal /, · of the flip-flop 72 arrives at the driver stage 20. The signal /, - arrives at one input of the AND gate 74. The output signal of the OR gate 76 arrives at the reset input R of the flip-flop 72, which receives a signal ST from the AND gate 78 (see FIG. 4) and a signal / from the preceding logic level. , · Receives. The signal /, · also reaches an input of the OR gate 80.

The output V _{1 of} the AND gate 66 also arrives at the flip-flop 82 as a reset signal via the OR gate 81. The O output signal of the flip-flop 82 arrives at a second input of the AND gate 74, which is the flip-flop 84 represents.

_{The signal Z 1} - arising at the 1 output of the flip-flop 84 - arrives at one input of the OR gate 86. The signal Zz ₁ - from the previous stage arrives at the second input of this gate. The signal z 1 also arrives at one input of the AND gate 88. The second input of the AND gate 88 receives the signal Ii ₁ from the inverter 90. The third input of the AND gate 88 receives the signal Tc _n ^ ₁ from the inverter -

pg g _n ^ ₁

ter 92 (Fig. 4). The output signal u, of the gate 88 arrives via the OR gate 89 as a control signal to the flip-flop 82. The signal W ₁ also arrives at the second input of the OR gate 80.

In the operation of the circuit according to FIG. 5, the driver stage 20 can perform three possible. /, · And d _t assume certain states. If /, · = 0, the driver stage is locked and switched off by opening the switch 24 from the column conductors. In this case the column conductors only end in the sense amplifiers. If /, = 1, the polarity of the control, ie whether the driver stage feeds its column with a “one” (1.0) or a “zero” (0.1), is given by d; definitely.

The timing of the processes in the circuit according to FIG. 5 is determined by the timer 46 (Fig. 3) controlled. The timer generates three time control pulses CP1, CP 2 and CP 3. The first pulse CPl. controls the resetting of flip-flops 64 and 84. The second pulse CP 2 controls the evaluation process (the sampling) of the sense amplifier. During this time interval the column signals felt or perceived. The third pulse CP'3 goes to AND gates 66 and 88 and in this way controls the switching or setting states the flip-flops 72 and 82.

The input signals F ₁ and D ₁ indicate whether the driver stage is an original driver and. if this is the case, which special binary bit ("zero" or "one") the driver stage should send to its column. These input signals start at the beginning of the query process and remain unchanged until the query process has ended. F ₁ = 1 means an original driver. The value of bit D ₁ - when F ₁ = I indicates the particular bit injected by the driver; if F ₁ = I, D ₁ = I, the driver feeds a 1.0; if F, = 1, D ₁ = O, the driver feeds a 0.1. If F ₁ - = 0, then D ₁ = 0, and the driver stage is either inactive or a "non-original" driver, depending on the status of the various logic stages, as will be explained in more detail later.

If F ₁ = I, the OR gate 83 is actuated and the flip-flop 72 is set. Even if a signal "1" appears briefly at f _tK (as will be shown later, this can only occur during the duration of the pulse CP3), the flip-flop 72 returns to the normal state (/, I) after the end of this pulse . A sufficient time interval is provided between the timing pulses so that / _; has fallen back to "1" by the time the next cycle's pulse CP2 occurs. Furthermore, if F ₁ = I, the AND gate 74 is inhibited or blocked (in that a “0” reaches this gate via the inverter 94) and the flip-flop 84 cannot be set. Consequently r., - "0" remains. Since the flip-flop 84 is reset by CP 1 at the beginning of each cycle, z, · remains "0" during the entire interrogation process.

If D ₁ = I (for this to happen, F, - must be "1"), the OR gate 89 is actuated and thereby the flip-flop 82 is set (c /, = 1). ; /, · Remains »1« during the entire query process. If D ₁ - ■■ · (), while F ₁ - = 1, the AND gate 99 is activated and the flip-flop 82 is thereby reset via the OR gate 81. d _t therefore becomes "0" and hljibt "0" during the query process. In this way, when F ₁ = I, D ₁ - and F ₁ - control the state of the driver stage for the interrogation process regardless of what kind of signals occur during the pulse CP3.

At the beginning of each cycle, the flip-flops 64 and 84 are reset by CP1, so that immediately after CP1 and before CP2 X ₂ = O. During this time, Z ₁ - also "0", except when F ₁ = O, /, = 1 and i /, = i. Under the last-mentioned conditions, which occur when the driver stage 20 is a non-original "0" driver, the AND gate 74 is activated and thereby the flip-flop 84 is set immediately after CP1. Therefore .V ₁ - = 0, z, · = 1 indicate a non-original "0" driver for the column /.

When CP 2 occurs, if the amplifiers 50 and 52 perceive a “1”, “1”, the AND gate 60 is activated and the flip-flop 64 is set as a result. As a result, Jf, - changes to "1". It therefore means .r, = l that a "1", "1" is perceived in the / column. The column conductors are also scanned when being driven through. In this case, however, the perceived signals can only be either "1", "0" or "0", "l". The AND gate60 therefore remains blocked and Jf ₁ - remains "0".

Next, consider the state of the variable for a given cycle during the interval after the occurrence of CP2 and before the occurrence of CP3. The column has been queried while CP2 is present, wordc-n, and /, · and dj are about to be "set up" for the next cycle. Let us first assume that one or more "ones" have been perceived in the various columns. From the logic diagram one can see that Jr ₁ and Ar ₁ - go to the OR gate 68 and there generate the output signal k _lti. Furthermore, A ₁ = 0 if A ', - is the input signal of the logic stages for bit 1 (see FIG. 4). The following Boolean relationships are therefore obtained:

..Λ ,, = Jf, +. Jf.

This means that if one or more 1,1 to the left of column i is perceived, then A, - = 1. Likewise, one can easily see from equation (1) that, if A:, - = 1, all A: to the right of it are also 1 (i.e. A ₁ - + 1 = A _{1 + 2} = ... A _{n + 1} = 1, if A, - = 1). Furthermore, if A ₁ - = 1, the AND gate 66 is blocked, so that v 1 must remain = 0. Likewise, in the case under consideration (ie if one or more 1,1 are perceived) A _n ^ ₁ (from the nth column) must be 1 and A _nM = 0 (FIG. 4). This prevents the output bit B ₁ from being read and also blocks the AND gate 88 so that w i remains = 0.

If A, = 0, then equation (1) indicates that no 1.1 are present in the columns to the left of column ι. If A, - = 0 and -x _t - 1, the column / is the leftmost column in which 1,1 appears. This is clearly evident from FIG. 5. Under these conditions, the AND gate 66 is enabled or activated during CP3, and v i becomes 1. Thus v i = 1 (during CP 3) indicates that the column i is the furthest left column is where 1,1 appears. v _t = 1 reaches the flip-flop 72 as a control signal via the OR gate 83 and as a reset signal to the flip-flop 82 via the OR gate 81. This results in /, · = 1 and d, - = 0. Fj = 0 , /, · = 1, d _t = 0 indicate that the driver stage. 20 has to act as a non-original "O" driver during the next cycle. The .r, - (hence the A ₁ ) are temporarily stored in the flip-flops in order to prevent the immediate switching of the next driver stage for a 1,1-column to an "O" driver. In summary, it can be stated that if one or more, 1, 1 are perceived, the OR gate chain A- (the gates corresponding to gate 68) and the gates ν (the gates corresponding to AND gate 66) supply the logical commands that are necessary to switch the driver level for the leftmost column, in which 1.1 is perceived, to an "O" driver. .

Next, consider the case where no 1.1 is perceived. As mentioned earlier, this indicates that an answer has been reached. In this case, A _n , _t becomes "0" [s. Equation (l)] and A _{n +1} = 1. H _{n + 1} = 1 acts as a pre-sampling or activation signal for the AND gate 62, so that the output bit B _{1 of} the sampling amplifier through this AND gate after a display or Buffer level (not shown) can reach. Since each pair of sense amplifiers produces complementary / outputs under these conditions, only one of these outputs need be used. Jc _{n +1} = 1 also serves as a pre-scanning signal for the AND gate 88. However, since all .t values are equal to “0”, all AND gates 66 are blocked.

The circuit according to FIG. 5 indicates that z, - and ft, - are at the inputs of the or- ^ jatter 86 which produces Λ,. h "- 0 (see Fig. 4). The following Boolean relationships result:

K ι ⁼ Λ =

It has already been shown that Z ₁ - = 1 means the presence of a non-original "0" driver. Therefore, if one or more non-orginal "0" drivers are present to the right of the ι bit, ft, = 1 fs. Equation (2)]. Furthermore, all Λ, inputs to the left are also “1” (ie Λ,., = H _1. , = ... = It ₀ = 1 if It ₁ = 1). If ft, = 0, then there are no non-original "0" drivers to the right of bit i [s. Equation (2)]. Further, when z i = 1, the rightmost non-original "0" driver is the

S driver for column i. If these conditions (Λ, · = 0, Zj '= .I, A _{n + 1} = 1) are met during the occurrence of CP 3, the AND gate 88 is unlocked and Wj becomes 1. It therefore shows w _t = 1 (during CP3) indicates that the rightmost non-original "0" -

io * driver is the driver for the / column. W ₁ = 1 sets the flip-flop 82 via the OR gate 89, so that dj = 1, whereby the driver stage 20 is switched to a "1" driver for the next cycle. "■. '

The signal W ₁ = 1 also reaches the OR gate 80 and causes Z _{1 + 1} to become 1. The OR gate chain / (the gates corresponding to gate 80) ensures that a signal is propagated to the right (see FIG. 4), so that / _{i + 1} = l has the consequence that

These signals in turn ensure that those flip-flops 72 to the right * of the / bit that are currently set are reset. A flip-flop 72 to the right of bit i , which is set, therefore indicates that its driver stage is either an original driver or a non-original "1" driver (the rightmost non-original "0" driver is the driver for the Column i) is. The flip-flops 72 for the original driver are after termination of the signal /. set by their corresponding signals F again. In contrast, the flip-flops 72 for the non-original drivers to the right of column i are reset by the signal /, and their drivers receive F, - = 0, so that they are inactivated. Therefore, if no 1,1 are perceived, the OR gate chain 86 (ie the OR gate chain h) and the w gates 88 provide the logical commands necessary to turn the leftmost non-original "0" driver into one To toggle "1"drivers;"the OR gate chain 80 (ie the OR gate chain T) enables the propagation of a signal that inactivates all non-original" 1 "drivers on the right.

A few additional remarks are in order. First, when the driver for the farthest left column 1, in which 1.1 is perceived, is switched to a "0" driver, so changes.

the relevant Z _{1 changes} from "0" to "1". This change affects the signals that propagate along the OR gate chain Λ (gate 86) (if there are no non-original "0" drivers to the right of column 1). However, since this only happens

if E _{n + 1} = 0, then such changes in the signals A ₁ - do not affect the states of the flip-flops, since all AND gates 88 are blocked. Second, if the rightmost non-original "0" driver is toggled to a "1" driver, the Zj (and hence the ft /) are held by the flip-flops to prevent this change from occurring immediately a second switchover of the next right non-original "0" driver follows.

The outputs y, - do not need in every bit position to be noticed. Rather, it can be more expedient to have an additional one in the diode matrix Column that is connected to all rows with diodes

The. The collector of transistor 126 is connected to column ia and the collector of transistor 126 'is connected to column ib . As explained earlier, it is in the operation of the circuit of FIG. 6 desires that when j _t = 0, both drivers are disabled; if fi = .1 and di = 1, the first driver stage 110 sends a 1 in column ia and the second driver stage 120 sends a 0 in column ib; and if /, · = 1 and d _t = 0, the first driver stage 110 a 0 in the column ia and

coupled is to be provided in order to provide the indication y (no answers).

Before the start of an interrogation process, all logical levels are preceded by a reset or Extinguishing pulse supplied. This happens after the search term has been sent to the original drivers is. The clear pulse resets all of the flip-flops 72, so that any during the previous Bits stored in the query process are deleted.

The flip-flops of the original drivers are of course the second driver stage 120 a 1 in the column ib

loaned to the Stellzu before the start of the first cycle.

was switched back because Fi = 1. It is initially assumed that /, · = (). this

If desired, although not shown, the means J _t = 1, ie a positive voltage is applied

Pulse ST are fed to a memory flip-flop to input terminal 132. This positive voltage den, whose 1-output a two-input AND-15 locks the transistor 122. Likewise, the

Gate is fed. To the second input of this the terminal 132 'supplied positive voltage den

AND gate receives the signal F _f . The output of transistor 122 '. Da- /, = 0, the AND gates 138 are

AND gate takes the place of the signal F ₁ - to and 138 'inactivated, and a "0", ie a negative

an / input of the OR gate 83. The task of this tive voltage appears at the connection points Circuitry is to prevent the ao 146 and 146 '. This negative voltage locks

Flip-flop 72 after completion of SP (SP lasts transistors 126 and 126 ', and the. Points 148

only as long as CP 3) is reset. Will and 148 'of the circuit to which the column conductor

however with total reset or deletion in the lie are practically open. Under these ^ advance

Worked the way discussed above, then these switchings are the subsequent in the driver stages arrangement not required. In cases where the input signals received are such that the

Circuit arrangement is desired, the Ge driver transistors will act as open switches, such

together with the clearing pulse also of the reset terminal of the that through these input signals the column conductor

Memory flip-flops supplied. effectively separated from the driver stages.

The termination of the query process is assumed that it is now /, = 1 and rf, · = I, so

the coincidence of the following conditions is given: 30 the AND gate 138 is locked, and the

E _{n + 1} = 1 ("register response") tie point 146 becomes negative This makes the

I ¹ ..),. ...... "",., Transistor 126 locked. If /.· = 1, then embodied

\ = 1 ("core non-original" 0 "driver _{J ( a negative spanming} . _{Dicse gets to the} terminal

more available «) 132 and unlocks transistor 122.

One can therefore use an AND gate 78 (FIG. 4) with 35 conductors generally connected via an impedance in the sense amplifier to these two input signals and keying through at such a voltage value that below these

The prerequisites for point 148 and thus also the column ladder are generally positive. For example, the column conductor can generally be grounded via an impedance of a certain size.

Wenri'd, = 1 and /, = 1, then the AND gate becomes 138 'activated. The connection point 146 'now becomes positive. This turns transistor 126 ' unlocked. The is under the same conditions

gears are identical, the elements of stage 45 have terminal 132 'negative, and through the voltage 120 each have the same reference numbers, only dividing the resistors 134' and 144 '. The values of resistors 144 'and 134' stage 110.; ^:; . ''".''.'''! f .. ■', ■ '.' -. are chosen so that the voltage at the base 136 '

The driver stage 110 contains a PNP transi- is positive so far that the transistor 122 'is not stör 122 in series with a resistor 124 and 50 conducts appreciably. Under these conditions an NPN transistor 126. The one with the emitter is the collector of the 'transistor 126' as well as the

Spaltcnlciter ib negative .. In summary, it can be stated that if /, · - = 1 and (/, ~ 1, the column generally becomes positive and the column ib negative, which corresponds to a control of the column / with 1.0 ..

Assume that it is now /, - = 1 and </, · 0. In this case, the AND gate 138 is activated and the AND gate 138 'is deactivated. The transistors 126 and 122 'conduct while transistor 126'

is locked via a resistor 140 to the base 142 of the Tran-60. Transistor 122 does not conduct nominal transistor 126. Worth a tension resistor. According to the Spaltenleitcr is ia nei-.ativ 144 is connected between the base 136 of the transistor 122
and the connection point 146 switched.

As already mentioned, the driver stage 120 is designed in the same way as the driver stage 110. It receives an input signal J, · at the terminal 132 '. As another. Inputs, however, the stage receives the signals /, lind (/, instead of /, and <!,.

Use CP 3 to generate a signal that stops the machine. .

Fig. 6

6 shows details of the driver circuit 20 and the switch 24. The arrangement includes a first driver stage 110 and a second driver stage 120. Since the circuits with the exception of the EinTransistor 122 connected terminal 128 is to a positive voltage source, terminal 130 connected to the emitter of transistor 126 on the other hand connected to a negative voltage source.

The input signal -J ₁ goes from the terminal 132 via the resistor 134 to the base 136 of the transistor 122. The input signals /, and 3, - go to the AND gate 138; Dessert output will be

and the column conductor ib positive. This corresponds to activating the column / with 0.1.

■ General Hrlüiitoriiih!

In the case of the inlialtsaihvssiert to be queried shown in FIG Storage with in the manner of tier l'iu. I among each other \ et switched lot'iselv.Mi steps

\ 0u11en

17 18

closed different words in a certain order. A ₄ , Ar ₁ and Z ₁ are on line 166, which is queried. With the help of the described a "0" is fed in, connected.
If you turn the insulating part 160 by 120 ° in the clock search word more than one stored word, the program sequence is clockwise, the interconnection between these words from the memory changes in a predetermined number of different logic levels. The first sound order, namely the word lowest gic levels in the ring, are now read out for the value first. Selected when using bit 2. The second levels are for the same program, but with a different interconnection - bit 3 and the third for bit 1. The definition of the logical levels of the various columns, step k of the logical levels for bit 1, can now be used to store words, in other io read out more about an inverter and the line 164 in order. This is fed back into the unified all logical stages. In similar representations of FIGS. 7a and 7b, the input h of the logic stages is clearly illustrated. for bit 1 and inputs k and 7 of the logical

FIG. 7a shows the stages comparable to FIG. 4 for bit 2 via the grinder 168 and the

logical levels which for a memory with three lines 166 connected to "0" etc. '

Columns would be required. The interconnection of the For the sake of simplicity, only three stages

logical stages is the same as in Fig. 4. One can of course use the same

However, these logical stages can also be applied differently to a ring of very much

interconnect with each other. For example, you can use more («) levels.
k _i and (j connect _{directly to A 1} and I ₁

ten. You can also connect _{/ z 4} directly with / i _0. rig. 0

However, the conductors Ar ₃ , /., And h ₂ can now be opened. 2 has memory matrix shown

will. The output Ay of logic level 2 can each memory column two column conductors - and can each

then one binary bit in each memory line via an In column similar to the inverter 92

.verter fed back to all logical levels 25 save.

will. The output I ₃ of logic level 2 remains. The invention is not only open to the application. The input Λ., Of logic level 2 is made "0" in this special type of memory matrix. Input A:., Which restricts the logic levels, but can also be set to content addresses for bit 3 is made "0". The input Λ., For sized memory matrices of the type generally interpreted in Fig. 8 and the logic levels of bit 3 is used. This memory matrix terminal of a type comparable to gate 78 consists of different groups of column-and-gates The first group 1 has four conductors, the second interconnection of the logic levels results in a group of nine conductors, the third group 3 of four conductors, which is roughly equivalent to a ring circuit - the fourth group (not shown ) nine conductors etc. In cash that can be opened between any pair of lo- 35 a line of the memory information of any level e) a nine-earth circuit according to the above-described group of conductors by means of a code that queries a program, the words stored in the "1" (and eight "zeros") appear in the memory output the coupling element (diode) of a quad in a sequence that deviates from the previously described sequence group of conductors by means of a code stored. For example, when one becomes that contains a "1" (and three "zeros"). This the logical levels for bit 2 effectively to the code is referred to as 4-9 (or "makes one out of four, one out of last levels in the group, that's how the nine") and is commonly used for words from memory in one chronological row punch cards used comparable code. A sequence is fetched, but bit 2 as the 45 such group of four bits plus a nine-bit lowest value and bit 3 as the bit group of bits each represents a character. Highest value is treated. If, for example, the, group of four plus the wise words 101, 001, 100 can be read out, then group of nines (each of which only contains a "1") appear these words in the order 100, 001, permuted in thirty-six different ways 101. With an interconnection of the stages as in 50, so that they are thirty-six different Fig. 7a, however, the words can represent in the row characters. In practice this can be read out in sequence 001, 100, 101. word stored in each memory cell, for example

F i g. 7b shows how the various logical 80 characters are long, making the memory total

Levels can be easily interconnected in this way 1041 column conductors (thirteen for each character plus

can that it contains in the manner just described 55 one for the operating voltage). Naturally

work. The part 160 consists of insulating material, the memory can also be very large if desired

and is rotatable about the central axis 162. Store the three more characters on each line. The number

The arms of the part each have different terminals - the lines naturally depend on the number of im

men, some of which by ladder among each other memory from words to be stored. ::

are connected. In the position shown, this switch- 60 The mode of operation of the memory according to FIG

The outputs of the logic stages for the memory according to FIG. 2 are analogous. With the one shown

the bit 1 of the inputs of the logic levels for the exemplary embodiment stores in the groups 1

bit 2 is passed on. The outputs of the logical and 2 the first line the characters 1000, 10000000,

Steps for bit 2 get to the inputs of the second line the characters 1000, 010000000 and

logical levels for bit 3. The output Έ , the 65 the p-th line the character 0010, 000000100.

Logical stages for bit 3 is over the line The circuit contains certain stages, each

164 to all three other logical levels individually to the individual leaders of a group

fed back. /, belongs to an open circle. These stages, one of which is shown in Fig. 11

and will be described with reference to this figure are indicated generally by blocks 170, 171, etc. indicated. There are also levels that are common to all leaders in a group. These stages are indicated by blocks 172, 173, etc. and will be explained in more detail later.

The way in which multiple words associated with a given search term are retrieved from memory can be found out is analogous to the already irri connection with FIG. 2 described Method. The program or instruction scheme for interrogating the memory of FIG. 8 is shown in FIG Program overview B (end of description) shown. Applying the command scheme to a special memory is illustrated in Figure 12b.

^: ■ Fig. 12:

Fig. 12 shows in its upper part (Fig. 12a) the words stored in nine lines 1 to 9 of memory.

The individual messages each consist of 14 bit groupings. In practice such a Memory have more than nine lines, and each word can contain a lot more than that 14 bit groups exist. The code used here is a 3-4 code instead of a 4-9 code, made up of two Establish. On the one hand the explanation should be simplified and on the other hand it should be shown that the program sequence of the query process to be discussed is general and can be encrypted as required can use content-addressed memory matrices.

First, the search word is sent to the memory matrix. This keyword from which adopted let it be that it is called "100", arrives at the first bit and thus conductor group in the memory. By the way, can too here, as in the memory according to FIG. 2, the search word or the search words of any group of conductors or several groups of leaders. For example, the search word »010«, "100", "0010" and forwarded to column leader groups 3, 5 and 6 respectively.

If the search word “100” is passed to the first column conductor group, the reading circuits of the various columns, the bit groups shown in the first line of FIG. 12b as the result of step 1 perceived. You can see that in the first step in groups 2 to 14 more than one "1" appears. You can also see that the data word "100" in group 1 in all nine lines of the Memory occurs. The search word "100" assigned to group 1 therefore selects all nine stored ones Words. In practice, of course, the search term usually does not match all of the words in the Storage.

The program scheme given in program overview B (at the end of the description) indicates that if more than one "1" is perceived in at least one group of column conductors becomes, in the leftmost group, in which more than one "1" appears, all leaders except of the conductor furthest to the left with a "1" with a "0", the rest of the conductor with a »1« are to be controlled. In the example chosen here, group 2 is the furthest left Group in which more than one "1" appears. The furthest left ladder with a "1" is the first Head of group 2. This head is marked with a "1" controlled, while all other conductors are controlled with a "0". Group 2 will therefore controlled with 1000. The search term is still forwarded to group I. As a scanning result the result in FIG. 12b shown under step 2 Bit group assemblyv During the determination of the scan result, the drivers are the Group 1 and Group 2 activated. These drivers

ίο control their leader groups with KK) or 1000, So now, so to speak, with the search term "100, 1000". The word "100, 1000" is multiple times in the memory, namely stored in groups 1 and 2 in rows 1, 6 and 8.

The words in these lines 1, 6, 8 are therefore now the chosen words. From the bit groups read out (see step 2) some still contain more than one "1". . .

The program scheme according to overview B shows

a ° now that again the furthest left Group in which more than one "1" appears must be controlled with a non-original driver. All Leaders in this group, with the exception of the one furthest left, a "1" leading leader, are included a "0" to control the rest of the conductor with a "1". In this example it is the furthest left group in which more than one "1" appears, group 3. The number scanned is 110. The . Group 3 must therefore be controlled with 100,

as shown in step 3 of Fig. 12b. If this happens, the words stored in lines 6 and 8 are selected.

At this point, the next group that reads more than a "1" is the Group 6. Your reading result is 1100. Group 6 is therefore controlled with 1000. If this has happened, there is no longer a group in which more than one "1" is perceived (see step 4). This means that a word can be read out in memory. And this is that under step 4 appearing word which corresponds to the word written down in line 6 of the memory.

It is now at least one nichtoriginärer drivers available who has not controlled the accompanying conductor group through all the states that are necessary to all _in: a circuit group trigger characters stored. In the following, such a driver is referred to as an incomplete or "incomplete" driver. From the existing

incomplete drivers (the drivers for the Group 2, 3 and 6) is the furthest right of the group 6 drivers. As you can remember, that was originally in, group 6 perceived word 1100. In step 4, group 6 with 1000 steered through. Group 6 must therefore now be controlled with 0100, as indicated in the program diagram in overview B. When this happens is, there is no longer a group in which more than one "1" is perceived. It can therefore use the second answer to be registered. This second answer corresponds to that in line 8 of the memory written word. . "

The above-described procedure can be continued in the manner indicated in FIG. 12b get the rest of the stored words. It can be seen that in this particular case only It takes 15 steps to find nine words written in memory.

21 22

Fig. 9 to 11 original driver. If F ₁ - = 0, then D ₁ - = 0 and

the driver concerned is either inactive or a -

The circuits required for the implementation of the above-described non-original driver, depending on the states of the program schemes, are different logic stages, as shown below in FIGS. 9 to 11. The number of ladder 5 will be discussed in more detail. In the present group in the storage plant, n. Corresponding to Case ₁ WeHnF ₁ = O, η are groups of logical [levels, namely one £> each. = j). ... = ß. = Q

for each group of leaders. The group / u. . «2

logical levels belonging to the ladder groups. If F ₁ = 1, then only one of D ₁₁ to D _{1 is} “same in FIG. If F ₁ = I, it is interpreted. The group / got in leaders. The first conductor flip-flop 72 (Fig. 9) is set (via the OR gate is Z ₁ , the second i., Etc. up to the last conductor i _m . 83) and remains set, as explained earlier. Furthermore, certain circuit stages are drawn to each conductor - the AND gate 74 remains inactivated because it is blocked. The steps for the ladder / are generally input 94 a "1" is fed to 186 and those for the ladder / ,,, generally at 15 If F ₁ = 1, one of the D ₁₁ to D ₁ - _{m is} a "1", 188, both in FIG. 11, indicated. The different and the OR gate 198 supplies an output signal to the lines and letter _{symbols in Fig. 11 C 1} - = 1. C ₁₁ reaches the blocking input 200 of the andvcranschaulichen the paths on which the signals of the gate 202 (Fig. 10). The flip-flop can therefore run different blocks between them. A detailed illustration of the stages 184, which is only then provided via the OR gate 204, is shown in FIG. 9 20. when D _1, D = 1. If _n = 1 (and F, - = 1), and a more detailed representation of the steps is provided for the flip-flop 180 and will remain for the conductor / of / is in head of the group in Fig. 10 the total duration of the query process is given. Those circuit elements in FIG. 9 state. In fact, it cannot be reset via the unduiid 10, the structure and function of gate 206, since J ,. = 0. Likewise the corresponding circuit elements in FIG. 5 25 it cannot be reset analog via the AND gate 208, each have the same reference numerals. because u, = 0 (W ₁ -O, because if F = I, the In 'of the circuits of Fig. 5 has each column AND gate74 is blocked, Z ₁ - = 0, and z, - = 0 the two conductors. The flip-flop 64 gets into the setting and gate 88 blocks). If, therefore, for the group / state, if both conductors have a "1". In which an original driver is present and the conductor / the circuit according to FIG. 9 has a column ladder group m 3 ° group / is to be steered through with a »1«, then the ladder becomes. The signal flip-flop 180 perceived in the first conductor for the conductor / set and remains q _{tv is} the perceived in the second conductor during the entire interrogation process in the set signal q _h , etc. These signals arrive at a state. The flip-flop 180 is only returned • "Threshold 2" circuit 190, in which it arises when the target or stop pulse ST reaches, for example, by a corresponding pre-OR gate 216. The flip-flops 180 for all voltage normally locked transistor lend the remaining conductors of the group / remain reset, can act stronger, the two for its unlocking. If the flip-flop 180 is set and g _r , equal to "0"

or more input signals are required. If this is the task, the AND gate 212 is actuated. It is switched off to generate a "1" when it receives a input signal d _u to the driver stage 20 /, which receives one or more "ones". The exit 4 ° sends the leader / the group / a »1«. The trip signal of the threshold value circuit 190 sets the flip-over stage 20 / consists of only one of the flop 64 shown in FIG. 6. The set state of the flip-flop 64 shows transistor circuits and works in the shows. that in the m-conductors of the group / more already explained in connection with FIG.

word corresponds. . 45 marriage continues on the perception of bits in the

The signals q _ix to q _{im also} arrive via different groups, are an OR gate 192 to an inverter 194. A few general remarks are appropriate. If the / «heads of the group / no» ones «stored memory is controlled with a search word, then the inverter 194 supplies at its output so one or more of the memory can match the search with a» 1 «. It therefore indicates y, - = 1 that there are corresponding words in the ladder word. Entgruppe / no bit corresponding to the search word speaks more than one saved word in which the search grouping is saved. . · ... ^: "% word, then appear in at least one ladder group. The AND gates 62, up to 62 _m, have the task of several" ones ". If this is the case, a bit grouping should be read out in the following constricting appropriate by the perception of a "mixture" keyword array of bits, are spoken of 55 groups present. in order to have the character read out Gruppierungß ,, .. dissolve _in .B grouping mixture can be the consisting of a "1" and in-1 " Zeros «.. Mixture leading groups of conductors in the additional feature explained in relation to the circuit according to FIG.

the 0110, with 0100 you can

to the AND gate 74. '. '■' "" control the group with 0010. The first state

As in the case of the earlier discussed embodiment of the driver stage in question, in the following it is intended to indicate F, - and /), whether the driver stage 65 in question is referred to as an "incomplete" driver. The F.nclwn original driver is. and, if so, the state of the driver stage. that is, the state that precedes the sign with which the driver is the dazimelinrijje haiidcn. when the driver all Gruppieniii- (iruppc hai to feed. F ₁ I means a μοη in a Gruppe'aufgelöst has. by ien to lci /

rightmost incomplete driver. If W ₁ -I, then the flip-flop 180 furthest left in this group is _reset to "0" via the AND gate 208 and the OR gate 216, with its d u corresponding to 5 being reset. If this flip-flop 180 is reset, the blocking signal g _{i (l + v located} at the AND gate 212 immediately on the right is switched to "0" so that the d _{rj of} this gate can switch to "1". If li il

Once a mixture has been perceived in the relevant group, it is referred to in the following as a "complete" driver. The incomplete and complete drivers are all non-original drivers.
In the case of the storage unit according to FIG
a non-original "O" driver as incomplete
and view a non-original "1" driver as a full driver.

It is now assumed that the heads of the _j

Group / not with an original driver through- i.o. an incomplete driver on its next approach

. being controlled. In this case, F ₁ = O and if the status is switched over, the in this

all D ₁ = O. Located in the leader / group / group is the leftmost flip-flop 180

(Fig. 10) a "1", the sampling amplifier is reset, so that the d _u that goes to the next

52 / a "1" is true and q _u = 1. At the same time, C ₁ = 0, ■ put flip-flop 180 to the right of it, to "1"

since all D, are equal to "0". The AND gate 202 15 can switch. CP 3 (the activating time control

is therefore activated, and a "1" is passed through the pulse for the AND gate 88) is so narrow or

OR gate 204 to the control input of the flip-flop briefly that w, - disappears before the next d-, f

180. e _u therefore becomes "1". e _u gets to the OR gate on the left becomes "1". This will make the instant

210, so that all g _{l (! + V} - become "1". This resets the flip-flop belonging to this d _u

means that all g _t / inputs for ladder 20 180 are prevented.

of the group / to the right of the leftmost The disconnection of the complete drivers from the Head /, in which a "1" is perceived, "1" belonging groups is gated by the OR. As a result, the AND gates 212 for the chain / (the OR gates corresponding to 80) become bewerk conductors to the right of the leftmost conductor /, digit. These gates have the effect that all flip in which a "1" is detected, blocked. There- 25 Flops 72 to the right of the next left incomplete against is the AND gate 212 for the furthest driver to be reset.

left ladder /, in which a "1" is perceived,. If y, - = 1, this indicates that there are no "ones"

not locked so that d _r can become "1". perceived in the group concerned.

It is now assumed that the outputs B which go to the buffer memory or Dar- 'group / perceived bits in the conductors of the next contain more than one "1" 30 digit (not shown), ie that a mixture of perceived "zeros." «To all m leaders of the group. This will. If the conductor of group i of the furthest "zeros" are scanned out by k _{n + i} , which is the gates 62, ... on the left, in which a "1" is perceived, so 62 "is fed, is / , · Via the chain of & -Or-gates 68 (Fig. 9) the instruction or program scheme converted into a "1". That is, this OR-35 provides shows in generalized form as a beGatter ensures that all subsequent k undesirables associative memory matrix z. B. are one with "1". On the other hand, &, == 0 and consequently, since χ = 1, the content of a read-only memory matrix made up of diodes, the AND gate 66 is actuated and ν, · = 1. v, - arrived addressed can be queried. With the OR gate 83 for the control input of the flip, for example, it can be applied to the memory according to FIG. 8 as flops 82. ν, · = 1 means the leftmost 40, also to the memory according to FIG. The perceived mixture. So if a mixture drawing is more or less self-evident, is perceived and which contains the mixture - however, certain details should be explained here somewhat to the group, the furthest left group with more detailed.

is a mixture, then the leftmost conductor of this group, which has a "1" in the content-addressed line according to the invention, will be asked a diode-fixed-value-od. Similar memory matrix "1", other heads of this group, however, with one, it is generally desirable to control the given "0". . Search word corresponding words in a pre-In the case of the storage unit according to FIG. 2 means correct, for example the numerical value of the words Z ₁ - = 1 a non-original "0" driver. In the memory corresponding sequence from the memory matrix plant according to Fi g. 8 means Zj = 1 to read out an incomplete 50. This is why the column drivers. The circuitry effecting this contains the ladder of the memory in a predetermined row threshold level 196. It senses whether more sequence is queried. In the first described Speicherais an e ₍ '£ p = 1 is present in the group. If, for example, the columns are set in the way this is the case, «, - becomes» 1 «, and the AND gate asks that the column with the furthest 74 is excited. (As you can remember, F ₁ - = 1 and /, == 0.) 55 starting from the left column and proceeding to the right and then begin, after going through a number of groups, ending with the rightmost one a "(!" driver in which more than one "1" appears, finally a leading column and advancing to the left. State is reached in which there are no more groups than with "ones". However, this does not have to contain a "1". At this point in time the first 60 is conditionally done in this way, since it is read under the l'm-word , the saved Invon an incomplete driver through-controlled te formation in a group other than this order can instead be controlled by a new group from the driver. or even in some arbitrary distribution or grouping. To get this arrangement out. Also, all columns chain / 1, which are scanned similarly to the context of the memory, do not have to be conditioned by the OR gates 86 in the logic 65, as previously described. Sometimes inteieswith the memory of FIG. 2, only misses part of the content contained in a word. In the present case, '', 1 denotes the formation. For example, it can be that. " at. one

Memory that stores information about insurance policies, only the premium due dates are of interest for a particular query. In this case, instead of all Column ladder only those column ladder scanned, soft the entering information to save.

According to the program scheme explained in overview B , only those conductor groups that are of interest are scanned. The ladder groups are each split conductor. In the memory according to FIG. 2, a ladder group consists of two column ladders. In the memory according to FIG. 8, the ladder groups each consist of four or nine column ladders. In the memory which contains the information according to FIG. 12a, the conductor groups each consist of three or four column conductors. In any case, a group of m conductors has a "1" and m - 1 "zeros".

If more than one »1« is read in one or more leader groups, a leader group is in which several "ones" appear, controlled with a certain bit grouping, to all Eliminate "I" bits except for one. In the generalized In the drawing, the special group of leaders to be controlled is not specially marked. However, this can be any group if the groups are not in a specific one 'Sequence are controlled, in which case the words or messages in no particular Sequence can be read from the memory. It is also not absolutely necessary that the am Farthest left leader in the group in which there is more than one "1", first with a. "1" .and all other conductors are controlled with a "0" and then the next right conductor with a "1" and all other conductors can be controlled with a "0", and so on. Rather, any of the Ladders in which the last time more than one "1" was read in a group a "1" appeared, can be controlled with a »1«.

Program overview A

a) Feeding of the search bit or bits to one or more columns of the memory element matrix by activating the corresponding column

- '. driver;

b) Query all columns of interest.

Case bi :

No »1.1« (signal »A '«) or »0.1« (signal »y«) or »1.0« (signal »Z«) is detected.

Result: The memory does not contain a word with a search word consisting of the search bits.

Case b2: ■

* "1.1" is found in at least one column.

c) The leftmost column in which »1,1« appears is controlled with »0,1«, and Step b) is repeated.

Case el:

No "1.1" is found.

Case c2:

"1.1" is found in at least one column,
c ') Step c) [which includes step b)] is repeated until the query no longer results in "1,1" in any column;

d) The relevant word or the relevant word part is read from the memory.
Case dl:

'There is no longer a driver that emits the signal »0.1«.

Result: There are no more words in the memory containing the search term.
Cased2:

There is still an interrogation conductor that emits the »0.1« signal.

e) Following step d), this driver is switched to "1.0" and the query according to step b) in addition to the reading according to step d). is repeated, with accordingly the query result of step b) before step d) if necessary steps c) or c ') be performed.

e ') Step e) is repeated until no query driver emitting the signal "0,1" more is available, and then the drivers set to "1.0" are switched off.

Program overview B

a) Supply of the search bit or bits that contain the search word form, to one or more columns of the memory element matrix by activating the corresponding column driver;

b) Query the column head of all columns.
Case bl:

. There is no "1" in any column leader group.

Result: There is no search word in memory.

containing word present.
Case.b2:

In no group is more than a "1" determined - - . 1

Case b3: ·.

More than one "1" is found in at least one group.

c) In the leftmost group in which more than one "1" appears, all Ladder with the exception of the one furthest to the left, which has a "1" leading to it a "0" and the remaining conductors are controlled with a "1" conductor, and step b) is repeated.

Case el:

No more than a "1" was found in any group.

Casec2:

More than one "1" is found in at least one group. . ■

c ') repetition of step c) until no more than a "1" is found in any group; .

d) The relevant word or the relevant word part is read from the memory.

Program overview C

a) Feeding of the search bit or bits that form the search word to one or more columns of the Memory element matrix by activating the corresponding column drivers;

b) Query the column head of all columns.
Fallbl:.

There is no "1" in any column leader group. Result: There is no search word in memory containing word present.

Case b 2:

No more than a "1" was found in any group.

Case b3:

More than one »1« is determined in at least one group of leaders.

c) The ladder group in which more than one "1" appears is assigned a bit grouping that includes all "1" bits except for one contains, activated, and then step b) is repeated;

d) The relevant word or the relevant word part is read from the memory.

Case dl:

After the word has been extracted, there is still at least one "incomplete" driver.

e ') One of the conductor groups controlled by an incomplete driver with a new bit grouping and switch off any existing complete drivers.

f) Repeat step b) and continue until case b 1 occurs.

Claims (3)

Claims:, 1. Method for the sequential reading of several unequal words or parts of words, which one or multiple search bits containing bits corresponding to, from an associative memory with a Bit memory element matrix laid out in rows and columns, the rows of which each have a number able to store word containing bits and their columns in each case several to the Contain bit storage elements of the same significance in all rows leading column conductors, whereby a) the search bit or the search bits are supplied to one or more columns and b) all columns of interest are queried, characterized in that in the event that the query according to step b) results in a signal X in at least one column c) a signal Y is fed to one of these columns and step b) is repeated, c ') this step c) is repeated until the query no longer results in a signal X in any column, in the event that the query according to b) or c) or c ') does not result in a signal X in any column, d) the relevant word or the relevant part of the word is read from the memory, e) that, following step d), in the event that a query driver that emits signal Y is still present, this driver is switched to signal Z and the query according to step b) is repeated along with the readout according to step d), whereby, in accordance with the query result of step b), steps c) or c ') may be carried out before step d), e ') that this step e) is repeated until there is no longer a query driver that emits the signal Y. and then the switched on Z-Siynaltreiber are switched off, where Signal »λ" «indicates the presence of two or more unequal, the search bit or Words or parts of words having bits corresponding to the safety bits Signal (in the case of two conductors per column, a signal that consists of a bit “1” in both column conductors consists), Signal »V« is a signal corresponding to one bit of one value (e.g. »0«) (in the case of two conductors per column, a signal that consists of a bit "0" in the first and a bit "1" in the second conductor), and Signal "Z" the opposite of signal "V", one bit of the other Value (e.g. »1«) (in the case of two conductors per column, a signal that consists of a bit »1« in the first and from a bit "0" in the second. Ladder) means. 2. The method according to claim 1 for reading out the words or parts of words in a sequence corresponding to their numerical value from a Memory in which the place values of the bit memory elements in a row from left to decrease on the right, characterized in that the columns, starting with the furthest column on the left in which a signal »Λ '« was previously detected, one signal after the other "Υ" is added and that the columns starting with the rightmost one Columns to which a "Y" signal was applied in the previous step, one after the other the signal »Z« is supplied. 3. Circuit arrangement for carrying out the method according to claim 1 or 2, characterized in that with each column a read and interrogation circuit (Fig. 5) is coupled to a driver stage (20) connectable to the column conductor, which, if the column in question with a search bit is to be controlled for the entire duration of the readout process in the active state that emits the search bit (e.g. by the flip-flop 72), while when the column in question is a column to be queried ₍ and by the reading stage (50, 52) connected to the column conductor, signals during the presence of the search bit or bits, which in this column the storage of both at least one bit of the one and at least one bit of the other value in the search bit or bits display corresponding words or parts of words, can be determined under control by a logic stage (60, 64, 72, 82) the column with signals "Κ" and "Z" according to the respective query program. For this purpose 4 sheets of drawings