DE1225421B - Circuit arrangement for converting a number encoded in any code into a number encoded in any other code - Google Patents

Description

FEDERAL REPUBLIC OF GERMANY

GERMAN

PATENT OFFICE

EDITORIAL

Int. CL:

Number:
File number:
Registration date:
Display day:

G06f

4M34e-

German class: 42 m-]

. 31. γ »

1225 42.1 ^ :,
S67766IXc / 42m
March 28, 1960
September 22, 1966

The invention relates to a circuit arrangement for converting one to a first code with any Base coded number into a number coded in a second code with any other base. One such implementation is in modern communication technology often required. For example, calculating machines and other facilities who work in the binary number system, the implementation of the ones to be entered, mostly in the decimal system encoded information in purely binary numerical values.

Several methods are known for performing such code conversions. With one kind Implementation networks are used by procedures. Used when implementing a decimal digit If a pulse is fed to one of the ten input lines in a binary number, then according to the assignment condition receive a certain pulse combination on the four output lines. This method requires a considerable amount of circuitry for larger numbers.

In another known method, for each decimal digit the corresponding Binary number determined. Should z. B. the decimal number 132 are converted into a pure binary number, so will First, the individual digits 1, 3 and 2 were converted into 0001, 0011 and 0010. The first of these implemented Digits (hundreds) are then converted to the binary equivalent of 100, i.e. H. with 1100100, the second digit (tens place) the binary equivalent of 10, i.e. H. with 1010, and the third digit (ones place) with the binary equivalent of 1, i.e. H. multiplied by 1. As a result of these multiplications is obtained man 1100100, 11110 and 0010. These binary numbers are added. You then get the binary number 10000100, which is the binary equivalent of the decimal number 132.

In another known method, the binary equivalent of each digit is also determined. Should z. If, for example, the decimal number 132 is converted into a pure binary number again, the individual digits I ₁ 3 and 2 are converted into 0001.0011 and 0010 first. The first digit (hundreds place) is then multiplied by the binary equivalent of 10, i.e. 1010.

The binary number 1010 is then obtained. For this purpose, the binary equivalent of the second digit 3, i.e. H. 0011 added. This gives 1101. Then it is multiplied again by 1010, which results in the binary number 10 000 010 arises. For this purpose, the units digit, i.e. H. 0010 added; you get the binary number 10000100, that of the Decimal number corresponds to 132.

Circuit arrangement for implementing a

number encoded in any code into an in

any other code encoded

Applicant:

Siemens & Halske Aktiengesellschaft,

Berlin and Munich,

Munich 2, Wittelsbacherplatz 2

Named as inventor:
Dr. Werner Krägeloh,
Dipl.-Ing. Friedrich-Carl Kroos, Munich

The invention provides a simple circuit arrangement for performing the code conversion. Included However, not only can decimal numbers, but also numbers encoded in a code with a correctable base are converted into numbers encoded in another code. In some cases it is necessary that the number that is obtained at the end of the conversion process depends on the number to be converted deviates by a constant value. Such a deviation is z. B. required if an in number encoded with a first code with correctable base and obtained from a first coordinate system into a number encoded in a second code with any other arbitrary base in a second coordinate system should be implemented.

A pulse counting circuit has become known, which counts the number of the supplied and to be counted Reproduces impulses in an arbitrary and adjustable code. That task is the present one Invention not based. Rather, both the entered and the output numbers should be in Code form appear. If we are talking about converting numbers encoded in arbitrary codes, then this is not to say that starting and End code without changing the specific circuit structure can be changed.

So-called down counters are known. Down counters offer the possibility of certain number of steps to be able to preselect, after which the arrangement sends a pulse or another control signal gives away. Other counting units have the option of preselecting certain number of steps,

609 667/347

■ 3 4

after they have been reached, the counting device stops the corresponding levels of the coefficients of the counter set to the and possibly also to another process code c . When this triggers. It is not known that such counting devices will be used as part of a code conversion device. Transfer speed achieved, for example at

It is also known to have a counting device for the implementation of a decimal number for its tens display of the number of counting pulses that only place one tenth and for its hundreds only one hundredth of the previously determined number of reference pulses flow to a pulse counter while a place occurs , counting pulses are required,
controlled by a gate circuit. This arrangement In certain cases, the digits of the number to be converted do not represent a code converter, nor is it known to have the number nib) in series. In this case, this arrangement can be used as part of a code converter in an advantageous embodiment for all. Place values of this number only one down counter

For the further explanations, the following are seen, in each of the relevant coefficients

Abbreviations used: set and that of the set coefficient

15 corresponding number of clock pulses supplied

b = base of any code, _w i _r d, which also has a gate circuit each

n (b) = the one to be implemented, in the code with any of the control inputs of the value of the

biger base coded number; provided coefficients corresponding levels of the

-,. - Code c of the turned off counter is present.

the number η (b) can therefore be as follows: 20 For the case that c = 2 and a = 2 ^m , we get

represent: an essential circuit simplification. In this

In this case, the binary counter is advantageous as an up counter

n (b) = a ₀ ■ έΉ-βχ b ¹ + ^ ■ b ² + and has m levels with the basic

a ₀ , Ct ₁ , a ₂ . ■. = Coefficients, · position »1.1 ... 1.1« and a most significant, dem

b °, ö ¹ , Z> ² ... = place values, ^a 5 value α assigned level with the basic position »0«

. on. If the number η (U) has a positive sign, becomes

analogously applies: 0; £ a ₀ , O ₁ , a ₂ ... <b; the lowest count input of the binary counter

additional pulse supplied. After completed

n (c) = the corresponding equivalent of the number n (b), implementation is the number in the binary counter

a - constant value; The conversion conditions apply directly to 30 positive signs and to negative signs

tion: n (b) -> a + n (c), characters read complementarily.

.n (2) = binary equivalent of ZaMnQ)). Further details of the invention are given

the drawing explained.

The mentioned task, namely the implementation F i g. 1 shows the block diagram of an embodiment of an example according to the invention encoding in an arbitrary code with the base b , on the basis of whose number n (b) the basic mode of operation explained in another arbitrary code is coded with the base c, if necessary to be one. At the input E the constant value α to be converted is fed to the number η (6) which differs from the number «(c) + α. For the further embodiments according to the invention with a circuit arrangement, it is assumed that this number is to be solved as a decimal number, which is characterized by the combination of the value 423 and converted into a binary number that is known and can be preset . Of course, however , the counters set aside for the code b could be coded as an input memory, the number to be converted or the converted number in a further known, presettable and arbitrary code. This number is set in the counter set to the code c as an output down counter Zl. The down counter memory and a control circuit, the clock 45 Zl can for example be constructed so that the pulse source is set depending on a start signal each digit of the decimal in its own, tetra and one of the dic counter based on the code b . As soon as the stop signal supplied to the counter inputs of the decimal number is set, the counter is set via the control line S1 or is disconnected from it. A start pulse is supplied to the bistable flip-flop Kl. Code c turned off counter is here advantageously designed as 50 This tilts into the working position "1" and de-up-down counter and in blocking the gate circuit Eq. At the output of this dependence on the sign of the number (δ) as a forward gate circuit then appear those operated by the clock or as a down counter. It is purpose generator TG delivered clock pulses. These are moderate to the individual counting input groups for the place values 55 assigned to the counter set to the code c in the down counter Zl and the binary counter Zl. After 423 clock pulses, the downward (Z) ⁰ , b \ b ² ) of the code b is broken down and each counting counter Zl has the count value “0”. The count of the input line group pulse delay elements to the down counter Zl is assigned by the gate circuit Gl . supervised. This gate circuit gives when it occurs

In an advantageous embodiment, "0" is used for the count value in the down counter Z1, i. H.

each place value (b °, b ¹ , b ^z ) of the 60 to 423 supplied clock pulses supplied in parallel, one pulse

ZaMn (F) a partial down counter is provided, in which the flip-flop Kl and leads it into the idle

the coefficient assigned to this place value (a ₀ , C ₁ , was "0" behind. As a result, the gate circuit Eq

C ₂ ) is set. The respectively set impermeable to the clock pulses of the clock generator

Coefficient corresponding number of clock pulses TG. If in the binary counter Zl at the beginning of the

if the count value »0« was set one after the other at the individual partial downward 65 conversion, stands

count and depending on the values of the now after 423 clock pulses and in the

individual partial down counters stored coefficients position of the contact Ic in the binary counter

at the control inputs of the binary equivalent of the decimal number 423 and can be sent to

5 6

the outputs A of the individual counter stages, ie 2, in the tetrad counter Z12 and via the

be taken. Receipt £ 13 the hundred digit, i.e. H. 4, in the

As already mentioned, it can e.g. B. set with the conversion tetrad counter Z13. The algebraic sign will be necessary for coordinate systems to be fed to the line marked with "+". If the binary equivalent of the number n (b) 5 to be converted is positive, a constant value α is added via this line. This value pulse at the input of the first binary counter stage is given via terminals B of the binary counter Zl . As a result, all stages of the binary start of the conversion process in the binary counter Zl counter Zl change their position, ie the counting stage with the off, so that the counter Zl from this basic A 11 is now in the "1" position counting out begins. The binary counter is OK and all other counting levels are in the "O" position. Now this case advantageously used as forward and backward is formed by the sequence control circuit ASS on the counter for converting numbers and with positive control line Sl, the coincidence gate G14 vorbereinegativen sign. Killed them. At the same time, the setting number η ψ) is given a negative sign via the control line S1 , so a pulse is fed to the bistable flip-flop Kl , which switches the contact & to the "-" position, and thereby toggles the 15 to the "1" position and the coincidence counter Zl operates from that prepared by the constant gate Gl . The clock pulses of the clock value α from the basic position defined as the backward generator TG can now be used by the coincidence counters. If the sign of the gates to be converted is positive, Gl and G 14 happen. They will be where the number η (έ) is the contact fc in the drawn units place of the decimal number assigned tetrad "+" position, and the binary counter Zl works as an advance counter Z 11 and the first counting stage of the binary counter Zl up counter. At the output terminals A is then fed. When the count value "0" occurs in the first case the binary number a- "(2), in the second case the tetrad counter ZIl, the binary number a + n (2) occurs at the output of the gate. In order to have a multiple circuit GIl a pulse that avoids the bistable tilt ambiguity, a> | 77 (2) | be. stage Kl transferred to the "O" position and thus that

F i g. 2 shows another embodiment of ^a coincidence gate Gl 5 locks for further clock pulses in accordance with the invention, some, the execution will now be via the control line S3, the Koinzibeispielnach Fig. 1 avoids adhering disadvantages. denzgatter G15 prepared and at the same time via the So it is, for example, in the embodiment control line S1, the bistable flip-flop Kl back in according to FIG. 1 sometimes unfavorable that the binary moves the "1" position and thus prepares the coincidence counter Z2 designed as an up / down counter 3 ° gate Gl . The clock pulse of the is because it is expensive due to internal reversals- clock generator TG now pass the coincidence digits as a simple counter. It also follows in gate Gl and G15 and that of the tens digit of the embodiment of Fig. 1 in particular the decimal number 423 associated Tetradenzähler Z12 in large numbers a considerable slowing down of, and at the same time the second and fourth stage of the Umsetzvorganges characterized in that the integer η 35 Binary counter Z2 supplied. The delay scarf must be counted out. These disadvantages are in device V before the input of the fourth binary counter stage of the embodiment according to FIG. 2 avoided. ensures that the carryovers from the addition to the conversion process cannot be significantly accelerated with the addition to the conversion process by coinciding instead of the fourth binary counter level. With ten impulses on the input of the first binary counter- 4 ° occurrence of the count value "0" in the tetrad counter stage one impulse each on the input of the second and Z12, ie after two clock pulses, occurs at the output of the fourth count stage. As a result of the coincidence gate G12, this is a pulse that is completely equivalent, because the addition of a binary 1 bistable flip-flop Kl resets to the "O" position and the value at the second or fourth binary digit that simultaneously blocks the gate Gl. Now the control line 5 * 4, the coincidence gate G16, is pre-increased via a binary number by 2 or 8, ie a total of 10 45. Of course, these two having to prepare and the pulses have the same via the control line 51 a small time interval, flip-flop class back into the "" - location not going through so that any transfers from the additions and prepared the coincidence gate Gl. That get lost. In a corresponding manner, clock pulses from the clock generator TG can pass through the sixth and seventh flip-flops assigned to the third, hundredth place of the decimal number 423, instead of 100 pulses at the counting input of the 5 ° coincidence gates Gl and G16 , which corresponds to the tetrad counter Z13 and at the same time the inputs addition of 4, 32 and 64, ie a total of 100 of the third, sixth and seventh binary counter level. A further simplification of the circuit results in supplied. Correspondingly, there are also in front of you when the constant value α is a power of 55 the input of the sixth binary counter is a Ver-2, that is, when a = 2 ^m , where again a> \ n \ delay circuit V and in front of the entrance that must be. In the embodiment according to FIG. 2 seventh binary counting stage two delay circuits V , such a case is assumed. It should be: provided so that the various additions a = 2 ¹⁰ = 1024 and n (b) = 423. Initially, they will not overlap. When the count value 0 occurs, eleven binary counter steps of the forward binary counter Zl 60 in the tetrad counter Z13, ie after four clocks via the reset line RL into a defined basic pulse, the position is transferred at the output of the coincidence gate G13. In this basic position there is a pulse that resets the bistable flip-flop Kl , the counting step with the outputs A 11 in the "0" position and thus the coincidence "0" position and all other flip-flops in the "1.""-Location. Gate G2 blocks again. The conversion process is then at the inputs Eil, Eil and £ 13, the 65 is now ended, and the decimal number 423 is supplied to the binary counter Z2. The number ^{2 becomes 10} +423 (2). The number 2 ¹⁰ is the ones place in the inputs £ 11, ie the value 3, in the eleventh binary counting stage with the outputs A 11, the tetrad counter ZIl, via the input £ 12 the tens, which are entered into the by the positive sign

7 8

"1" position was redirected. At the other left, independent control inputs of the third ,,

Outputs of the binary counter levels can therefore (connected by the sixth and seventh binary counter level,

seen from left to right) the binary number 10110100111 These further control inputs are connected to the.

= 2 ¹⁰ +423 can be read. triangles connected to the corresponding steps.

It is now assumed that the 5 to be converted indicates. When the counter value "0" occurs in the decimal number423 it has a negative sign. Via the tetrad counter TZ, ie after four clock pulses, the reset line RL , the binary counter Z2 occurs at the output of the coincidence gate Gl, a pulse returned to the basic position, in which the bistable flip-flop Kl in the »0 <t position. Counting stage with the outputs A 11 in the "0 <r position and resets and the coincidence gate Gl again all other counting stages are in the" 1 "position. Locks in the io. Now the tetrad counters ZIl, ZIl and Z13 are scanned and described by the punched tape scanner, as previously the second decimal place, ie the number 2, the units, tens or hundreds via the code converter CU "in the tetrad counter TZ place the decimal number 423 At the input terminal marked "+" are now stored in the control line S3-, the coincidence gates GIl and G23 but no pulse is supplied, since the sign 15 prepares and the bistable is supposed to be negative via the control line, S1 Therefore, in this case, the flip-flop Kl begins to be transferred back to the "1" position. The binary counter Z2 from the clock pulses of the clock generator TG through the reset line RL are counted from the basic setting. Total tetrad counter TZ and the monostable toggle the binary counter Zl compared to the preceding JSTMl and KM1 and the coincidence gate G21 example, in which the sign p positive ao and G 23 according to the tens of the decimal. was, one pulse less at the first binary counter number fed to the other inputs of the second or fourth. The individual counting stages of the binary counter stage are fed to the binary counter. After two counters Z2 then have the following states (from left to right clock pulses appear in the tetrad counter TZ the counting): 10110100110. An value "0", and via the coincidence gate Gl, the respective right outputs of the binary stages can 25 the trigger stage JsTl transferred to the "0" position and the binary number (again blocked from left to coincidence gate Gl . Now the right is read) 01001011001 are read. This one point, that is the number 3, the binary number of the decimal number Lochstreifenabtaster 2 ¹⁰ -423 = 601 .. via the transcoder CU corresponds to the Tetradenzähler TZ

A further exemplary embodiment is set in FIG. 3. Via the control line Sl is now shown, which is prepared with respect to the embodiment 30, the coincidence gate G20 and slightly modified over that of Fig. 2 and supplemented by certain control line Sl and the bistable multivibrator JVI the auxiliary equipment. In this case, the coincidence gate G2 is again prepared. The clock control example is assumed that the re-pulses of the clock generator TG are stored digit-by-digit in a 5-digit code counter TZ and on a punched tape via the monostable flip-flop JsTMl and the coincidence gate G 20 corresponding to the one. Value 2 ¹⁰ different binary number on magnetic tape place the decimal number to the other input that is to be transmitted. After three bar

The counter value "0" occurs in the tetrad counter TZ via a reset line (not shown).

all stages of the binary counter Z 2 in the "1" position on ,, and via the coincidence gate Gl and the

and the bistable flip-flop JsT2 in the "0" position above the 40 histable flip-flop Kl becomes the coincidence gate G2

guided. Then the sign of the im is blocked first. Now is the actual transfer process

The number saved with the punched tape is terminated by means of the punch. In the bistable multivibrator J5T2 and in the

Stripe scanner LA scanned. First of all, the individual steps of the binary counter are again, from left to right

assume that the sign is positive. Seen in right, the binary number 10110100111. This one

In this case, the number marked "+" is 45 binary number corresponds to the decimal number 2 ¹⁰ H-423. she

output of the code converter CU a pulse of the bistable is now to be transferred to the magnetic tape MJJ

Flip-flop Jv2 is supplied and these are thereby converted into the, but only in the example chosen

"!" - Situation transferred. The one at the right exit. should have six parallel tracks. To transfer

The pulse generated by the flip-flop Jv2 is transferred to the two buffers on the magnetic tape

Input of the first stage of the binary counter Z2 zzüge- 50 ZSl and ZSl with six binary storage stages each

leads. This will make all the levels of binary. intended. The control line 5 * 5 will now

Counter Z2 transferred to the "O '" position. Then there is a storage pulse for the two buffers

From the paper tape scanner. L.4 the third decimal, i.e. H. given. The memory contents of the

at the decimal number 423 the number 4, sampled, in the bistable flip-flop Kl and the five left binary

Code converter CU implemented and in the tetrad 55 counter stages from the buffer ZSl and

counter TZ set. From the sequence control circuit the content of the five right binary counter stages of the

ASS are now the five right binary storage stages of the buffer via the control line S4

Coincidence gates G22, G24 and G25 prepared. ZSl taken over. The left memory level of the

At the same time via the control line Sl the. Intermediate memory ZSl. is always set to "0"

bistable flip-flop JsTl transferred to the "1" position 60 is placed. The two coincidence gates G26 and G27

and thus unlocked the coincidence gate G2. They are taken from the outputs of the storage level of the

Clock pulses of the clock generator TG are sent to the buffer ZSl , which the state

Tetrad counter TZ and has taken over as a delay of the bistable flip-flop Kl . There

members acting monostable flip-flops JfMl, this flip-flop JsT2 was in the "1" position

JSTM2 and KM3 one after the other. Has inputs 65, the coincidence gate G 26 is prepared. So-

the coincidence gates G22, G24 and G25 supplied. more is written via the control line S7

The outputs of these coincidence gates are given an impulse for the buffer ZSi. There.

speaking of the hundredth place of the decimal number with the coincidence gate G26 is permeable, the

the left outputs of the stages of the buffer ZSl associated coincidence gates G 29, G31, G33, G3S and G37 are permeable and the content of these stages is transferred to the magnetic tape MB via the mixing gates Ml to M5. A shift pulse is now given via the control line S6. As a result, the memory content of the intermediate memory ZSl is taken over by the intermediate memory ZSl without the content of the intermediate memory ZSl being deleted. In the subsequent write pulse on the control line SL again, the left outputs of the memory stages of the latch ZSL associated coincidence gates G29, G31, G33, G35 and G31, as well as the left output of the left stage of the latch ZSL associated coincidence gate G38 permeable and the contents on the Mixing gate Ml to MS or transferred directly to magnetic tape. The binary digits 000111 corresponding to the states of the five binary counter stages on the right are now stored on the six parallel tracks of the magnetic tape MB (viewed from left to right). Then follow (again seen from left to right) the binary numbers 101101 according to the states of the flip-flop Kl and the five left binary counter stages.

While the binary numbers stored in the buffers ZSl and ZSl are being transferred to the magnetic tape, the next decimal number can already be converted.

It is now assumed that the decimal number --423 is to be converted. Via the reset line RL , the flip-flop Kl and the individual stages of the binary counter Zl are first transferred back to the starting position (viewed from left to right) Olli ... 11. Since the sign should now be negative, the flip-flop Kl remains in the "0" position. Now the individual decimals are converted as described above. The binary counter Zl is thus fed a total of one counting pulse less at the input of the first binary counter stage. As a result, the flip-flop Kl and the binary counter stages (viewed from left to right) now have the following states: 00110100110. As previously described, the binary number is transferred to the buffers ZSl and ZSl . Since the flip-flop Kl is in the "0" position, the coincidence gate G27 is now controlled to be transparent. With the following write pulse via the control line S6 , the coincidence gates G28, G30, G32, G34 and G36 are prepared and the right memory outputs of the buffer ZSl are connected to the write heads for the parallel tracks of the magnetic tape MB via the mixing gates Ml to M5 . As a result, the binary number 011001 is on the magnetic tape in the first row according to the memory content of the five right binary counter stages and the binary number 010010 in the following row corresponding to the memory content of the flip-flop Kl and the five left binary counter stages.

Of course, the illustrated embodiments described can be used within the framework of Invention can be modified and supplemented accordingly. In particular, not only decimal numbers, but numbers that are coded in a code with any base are converted. Also can The code to be implemented in is different from the binary code.

Claims (9)

Patent claims: 1. Circuit arrangement for converting a number n (b) encoded in any code with the base b into a number n (c) + a encoded in any other code with the base c, possibly deviating by a constant value α , characterized by the interaction of a known, presettable counter (down counter Zl) set to the code b as input memory, another known counter (Z2), which can be preset to the value α and set to the code c, as an output memory and a control circuit which a clock pulse source (TG) in response to a start signal and a signal supplied by the code b on the parked counter (down counter Zl) stop signal to the counting inputs of the counters (Zl, Z2) inserted or separated therefrom. 2. Circuit arrangement according to claim 1, characterized in that the counter (Z2) set to the code c is designed as an up-down counter and is operated as a forward or downward counter depending on the sign of the number «(Z)). 3. Circuit arrangement according to claim 1 or 2, characterized in that the counter (Z2) set to the code c each has a counter input group for place values (b °, b \ b ² ) of the code b . 4. Circuit arrangement according to claim 3, characterized in that each counting input line group Has pulse delay members. 5. Circuit arrangement according to claim 4, characterized in that a partial down counter (ZIl, Z12, Z13, Fig. 2) is provided for each place value (£> °, b \ b ² ) of the number n (b) supplied in parallel, in the the coefficient (a ",%, O ₂ ) assigned to this value is set, and that the number of clock pulses corresponding to the coefficient (a ₀ , O ₁ , a ₂ ) in succession at the individual partial down counters (ZIl, Z12, Z13) and are present via the corresponding counting input line groups of the counter (Z2) set to code c. 6. Circuit arrangement according to claim 4, characterized in that a common down counter (TZ in Fig. 3) is provided for all place values (b °, b \ b ² ) of the arbitrarily coded and numerically supplied number n (b) in series the respective coefficient (a ₀ , a _x , O ₂ ) is set and to which the number of clock pulses corresponding to the set coefficient is fed, which are also applied via a gate circuit to the counting input line groups of the counter (Z2) set to the code c. 7. Circuit arrangement according to one of claims 1 to 6, for c = 2 and a = 2 ^m , characterized in that the binary counter (Z2) designed as an up counter has m stages with the basic position "1.1 ... 1.1" and has a most significant step assigned to the value a = 2 ^m with the basic position "0", that an additional pulse is fed to the lowest counting input of the binary counter with a positive sign of the number n (b) 609 667/347 and that the number in the binary counter after the conversion has been completed has a positive sign is read directly, with a negative sign, complementary. 8. Circuit arrangement according to one of the claims 1 to 6 for c = 2 and a = 2 ^m , characterized in that the binary counter designed as an up counter has m stages with the basic position "11 ... 11" and another, the value a = 2 ^m associated flip-flop (K) with the basic position "0" is provided, which with a positive sign of the number n (b) flips into the "1" position and thereby feeds an additional pulse to the lowest counting input of the binary counter, and that the number in the binary counter and the other flip-flop stage after the conversion is complete, if the sign is positive, directly, if the sign is negative tive sign is read complementarily from the binary counter. 9. Circuit arrangement according to claim 7 or 8 for transferring the number stored in the binary counter and optionally in the further flip-flop to a magnetic tape, the number of tracks of which is smaller than the number of digits of the binary number to be transferred, characterized in that several intermediate memories (SpI, SpT) are provided , in which a part of the number in the binary counter and possibly the further flip-flop is stored at the same time and from which they are successively transferred to magnetic tape. Considered publications:
German Auslegeschriften No. 1 020 200, 1 051 039, 078 355. 1 sheet of drawings 609 667/347 9.66 © Bundesdruckerei Berlin