DE1214791B - Surface transistor with base and emitter zone on the same surface side of the semiconductor body and method for manufacturing - Google Patents

Description

FEDERAL REPUBLIC OF GERMANY

GERMAN

PATENT OFFICE

EDITORIAL

Int. Cl .:

HOIl

German KL: 21g-11/02

Number: 1214791

File number: T18836 VIII c / 21 g

Filing date: August 12, 1960

Opening day: April 21, 1966

The invention relates to a planar transistor with an emitter, a base and a collector zone, whose base electrode is attached to the same surface side of the semiconductor body as the emitter zone is.

In a known tetrode arrangement, the semiconductor body consists of n-conductive silicon. In Two diffusion layers are diffused into this semiconductor body of the n-conductivity type, although one η-layer and a p-layer upstream of this η-layer. The diffused η-layer represents the emitter zone the tetrode, while the p-conductivity type zone upstream of the n-layer represents the base zone the tetrode forms. The Störstellenkonzenträtiori the The η-layer is chosen to be larger than that of the p-layer. For making the auxiliary base and control base electrodes p-doping strip-shaped electrodes are alloyed through through both diffusion layers, while insert the emitter zone flat into the emitter zone through a flat between the two base electrodes Electrode is contacted.

By applying a suitable direct voltage between the auxiliary base = and the control base electrode in this known tetrode arrangement along the base zone, an electric field can be generated which the emission of the tetrode is limited to a narrow area of the emitter zone, which is the control base electrode is immediately adjacent. The known arrangement has the advantage that the external base resistance, that between the alloyed control base electrode and the beginning of the immediately adjacent one Emitter zone occurs, is negligibly small. Since the effective in the area of the emitting zone increasing internal base resistance can also be kept small with the known arrangement, by correspondingly reducing the width of the emitting zone rMt HiKe of the longitudinal field in the base zone, has the known arrangement with appropriate dimensioning and doping of the Base zone has the lowest base resistance of all known transistor arrangements.

However, the high-frequency behavior of this known Te trodenahordnung is generally no better than that of the other known high-frequency transistor arrangements. This disadvantage of the known, mesa-shaped tetrode arrangement is primarily due to the fact that, in contrast to known transistor arrangements, three electrodes are arranged on the emitter side. In addition, in order to achieve small collector capacitances, even in arrangements which are intended for an operating frequency of a few hundred MHz, flat transistor with base and emitter zone
on the same side of the surface of the
Semiconductor body and method for
Produce

Applicant:
Telefunken

Patentverwertungsgesellschaft mb Hj
Ulm / Danube, Elisabethenstr. 3

Named as inventor:

Dr. Ernst Frosehle ^ Ulm / Danube

are, the mesa structure or mesa surface is not essential may be wider than 1Ö0 μ, so that the mutual distance between the lead wires in the known Tetrode arrangement cannot be made larger than 25 to 30 μ. As for higher frequencies If correspondingly smaller distances are required, the contacting becomes with increasing cutoff frequency the electrodes arranged on the emitter side are becoming more and more difficult. The small gap between the electrodes also has the consequence that only very thin wires are used as electrode leads which, however, have relatively high lead resistances and lead inductances which are very annoying, especially at high frequencies.

A planar transistor is used to avoid these disadvantages with an emitter, base-collector zone, whose base electrode is attached to the same side of the semiconductor body as the emitter zone, according to the invention designed so that on the same surface side of the semiconductor body one the Emission current leading electrode is attached, which is ohmic with the base zone and with the Emitter zone connected to the ear or via a pn junction with a very low breakdown voltage is.

The planar transistor according to the invention, which is shown in various embodiments in FIGS. 1 to 5 is shown, will be described in more detail using the example of a transistor with pnp zone sequence, although Of course, analog embodiments with npn zone sequences are also possible. It should be pointed out here it should be pointed out that a special embodiment of the invention according to FIGS. 3 to 5 one

609 559/311

3 4

The transistor provides, in which between the base and the visible frequency limit, so does the

Collector zone a weakly doped or intrinsic resistance in the emitter zone 3 between the

conductive intermediate zone is provided. It turns out alloy electrode 2 and the emitting point 13

even as advantageous, such a pnip or annoying noticeable. It is therefore advantageous, as shown in

npin transistor arrangement with tetrode properties 5 Fig. 2 shown, on the emitter zone 3 a metallic

according to a development of the invention to apply mesa-shaped coating 14, which is connected to the electrode 2,

to train. but not with the electrode 1 metallic contact

Which, as already stated above, has to in the following. The metallic coating 14 is advantageously so far viewed transistor with pnp zone sequence is to be expanded that only a safety distance example of a semiconductor body made of germanium io between the metallic coating 14 and the electrode 1 is explained, although others are of course also allowed to avoid a short circuit, Semiconductor materials, such as silicon or that is, for the HF behavior of the AmBv connections according to the invention, can be used. It is advantageous if the emitter zone 3 (see FIG. 1) of such a pnp transistor is as largely as possible, except for a certain techno transistor, is very heavily doped with p-type impurities, 15 logically determined safety distance from the transistor While the relatively thin base zone 4 is heavily covered with trode 1 with metal.
n-type impurities is offset, but only so strongly that the impurity density in the base zone is smaller than that of the emitter zone, despite the tetrode character, only two electrode-to-impurity density. The collector zone 5 adjacent to the base lines on the emitter side allows the electrode leads to be more heavily doped than a p-conduction type such as the emitter zone with p-interference in the case of three electrode sites on the emitter side. To train supply lines and consequently lower

In the emitter-side surface this pnp-Tran- ohmig and low induction run. F i g. 2 shows

In contrast to the known tetrodes, sistors are now, for example, an arrangement with a strip shape

arrangement not three, but two electrodes 25 formed electrode leads 11 and 12, the

alloyed. The alloy material for these two widths perpendicular to the plane of the drawing roughly equal to that

Alloy electrodes are selected in such a way that the corresponding length of the electrode strips 1 and 2

Alloy heavily η-doped, the alloy can be chosen.

Electrodes 1 and 2 belonging semiconductor zones 6 and 7 The electrode 2 can also, as in FIG. 5 shown develop. These and the following considerations 30 are carried out in such a way that they apply to the electrode 1 completely naturally also in an analogous manner for tran- stead, for example enclosing in a ring. Except sistors with reversed order of layers. the advantage that with this arrangement there is no upper

The arrangement according to the invention is now switched like a surface leakage current from the collector to the electrode 1, a normal transistor and how can the electrode leads of these only a total of three electrode leads, 35, 10, 11 and 12 according to FIG. 5 run so, namely the collector electrode 9 contacting that the transistor is easily placed in a coaxial line collector electrode lead 10, which the alloy can be installed and the emitter lead 12 electrode 1 contacting electrode lead 11 and is placed on the outer conductor,
the electrode lead 12, which is connected to the alloy It has been found that above all the electrode 2 is connected. In the operating state of the collector series resistor of the known tetrode transistor now flows through the electrode lead 12 arrangement significantly contributes to the fact that the known apart from the emission current still another current arrangement for very high frequencies is unusable from the alloy electrode 2 to the alloy electrode. Incoming calculations have shown that, through the base zone, which, like a tetrode, produces the main contribution to the real part of the in the base zone at very high frequencies, the losses in the longitudinal field 45 collector zone 5 required to narrow the emission. The essential advantage of the output conductance of such a tetrode and the invention is thus that the tetrode effect greatly reduces the oscillation limit. To be achieved by a three-electrode arrangement. Avoiding these losses is called continuing education

Proposed by a heavy doping of the emitter zone 3 of the invention, the collector zone 5 and the adjoining, to the alloy electrode2 50 to be doped very highly, for example with 10 ¹⁷ to 10 ²⁰ belonging semiconductor zone 7 can be achieved that defects per cubic centimeter, and according to F i G. 3 to provide an intrinsically conductive zone 8 for the pn junction formed in the transition area by this semiconductor zone and the emitter zone between the base zone 4 and the collector zone 5,
very low Zener breakdown voltage, which is smaller. This intermediate zone 8 can also be weakly n- or than 0.5 volts, or the characteristic of a so-called 55 p-conductive in the event that such a "backward diode" is present. In the case of such a weak n- or p-doping, it is easier to implement technologically teristics through the emitter zone 3 and through the. However, any n-doping of the semiconductor zone 7 of the alloy electrode 2 formed in the zone 8 may only be so high that at least in the pn junction, as in the case of the arrangement of the emission region 13, the space charge zone of the collector can be seen in FIG. 1 the current to the emitter via this gate-side pn-junction is supplied over the entire pn-junction, so that for the emitter width of the high-resistance zone 8 extends, if zone 3 none with the alloy electrode 2 ohmically between collector and base the lowest pre-bonded metal cover is required. Trans- seen operating voltage is applied,
Transistors of this type are relatively easy to manufacture. The lowest losses and, at the same time, voltage and amplification properties are satisfactory at a few hundred MHz. is obtained when the transition between the strong

However, if one sets the described semiconductor-doped collector zone 5 and the high-resistance zone

arrangement higher requirements, especially towards Zone 8 is as steep as possible and the high-resistance

5 6

Intermediate zone 8 is so little doped that the collector run time το is proportional to the KoI space charge zone of the collector barrier layer through the lector barrier layer thickness wsc and inversely proportio the entire zone 8, i.e. from the highly doped area to the mean drift speed of the minority of the base zone 4 to the highly doped area of the charge carriers. Since the output conductance of the Tran collector zone 5 extends. 5 sistors very strongly from the collector capacitance

For many purposes it is desirable that hanging, it is advantageous to keep wsc as large as possible

not only the real parts of the output and return make, so that / _x is essentially determined by το

Effect conductors are small, what will be after the above. Accordingly, it should
Suggestion by a uniform, ie equally wide

Intrinsic intermediate zone 8 is reached, but also io Jü £. ;> _XE _j_ _{% B} _ | _ _Tr

their blind shares. This can be achieved by 2 ~

that according to a further development of the invention be the.

Distance between base and collector zone, d. H. As with tetrodes and also with the invention so the width of the intrinsic zone at the point of small arrangement, the emitting zone is very narrow is made than in the other areas of the In- 15 and directly adjoins the electrode 1, it is necessary, trinsic zone, at which the emission essentially does not insert the electrode 1 too deeply, so not he follows. This means that the width of the intrinsic at the emitting point 13 by the above zone vary and in the area of the preferably emitting semiconductor zone 6 of the electrode 1, the field strength of the point 13 must be smaller than in the other collector fields due to shielding effects, if the blind shares are reduced 20 is reduced. The electrode 1 should therefore, also at should. Arrangements without high-resistance or intrinsic conductive

According to FIG. 4 one intermediate layer, not deeper than half the collector

realize that the base zone is not alloyed with a barrier layer thickness in the semiconductor body

changing width of the collector zone in the emission process.

Area 13 is set lower than in the other areas. 25 The defect electrons reach one field strength

are sufficient. Another possibility is that of E _n , = IO ⁴ V / cm or greater in germanium

Collector zone 5 according to FIG. 5 not uniform, a limit speed of about 5 x 10 ⁶ cm / sec.

but to be of different widths, namely in such a way that for ν = v _m with a collector running time that is the distance between the base and collector zone

at the emission points 13 is less than in the 30 _{% Q} _ ^Wsc 2 ■ K) - ¹¹ seconds,

other areas. In other words, the v _ro
Intrinsiczone 8 in this special case to the

Emission sites be made thinner than in their When dimensioning the transistor according to the remaining areas. A closed ring-shaped formation must be ensured that the field strength in the formation of the electrode 2 is prevented in such a collector barrier layer greater than or at least the same arrangement in which the intermediate zone 8 is in the outer of this field strength E _m . So if the area is not yet thicker than in the inner area, the risk of emission current starting must be the voltage U ₀ in that of a surface breakdown. Collector barrier layer greater than 1 V per 1 μ collector

In this context it should be the barrier layer thickness. If, on the other hand, it is shown that the collector barrier layer just described generates an emission current, measures, namely the insertion of an intrinsic zone, create a space charge between the collector and base zone and differently in the collector barrier layer, which is given by the ratio of the current-like dimensioning of the Width of this intrinsic zone is dense / g to drift speed. This space charge, even on normal transistor arrangements without tetro- but requires an additional collector voltage, the effect can also be applied and the size of which results from the consideration that a given space charge density and barrier layer of the oscillation limit a substantial improvement of these arrangements by reducing the initial thickness specific voltage is assigned.
conductance result. To achieve a high current density depending on and thus

The last-described measures concerned a small te , it is therefore advantageous to

the avoidance of HF losses. To operate with a maximum of 50 sistors at the highest possible voltages,

Frequency transistors, however, must also be paid attention to, e.g. B. with a third to half of the breakthrough

that the current gain β in emitter-base circuit voltage Ub, which in pnip transistors made of germanium

is as large as possible. If one denotes with / _{x the} one with 1 μ barrier layer thickness is about 20 V. At a

Frequency at which the current gain β on the collector voltage of 10 V can

The following relationship applies, as is well known: 55 corresponding arrangement for current densities of up to

to 8000 A / cm ^{2 can be} operated without a

- 7Zf ₁ = - + τ β + τR + te reduction of the drift speed of the defect

2 2 electron or space-charge-limited emission occurs.

το is the transit time of the minority charge carriers 60. It is clear that such high current densities through the collector barrier layer, Tb, their transit time with regard to the heat generated thereby through the base zone. The other sizes te and Tr can only be achieved in arrangements in which we represent the time constants of the parallel connection of the emitting zone in the case of the arrangement according to the invention and also the emission resistance with the static emitter of the tetrode. capacitance (te) or the edge capacitance (tr) . Even with steep pn junctions between the emitter edge capacitance, te is then relatively small compared to the emitter zone 3 and the semiconductor zone 6 of the electrode το. So z. B. with a base doping of trode 1. 10 ¹⁸ imperfections per cubic centimeter and one

Potential drop Veb of 0.1 V across this emitter-base barrier layer, the barrier layer thickness is about 1.4 x 10 ^-6 cm and the specific static Emitterkapäzität ces = 1 x 10 ^-6 F / cm ² are, while the emitter time constant te is 3 · Accepts 10 ~ ¹² seconds. From these considerations it can be seen that in transistor arrangements which work with such high current densities, a flat doping curve between the emitter and base zones gives little gain

brings. Such Dotierungsverläüf even affects Bäsisschicht ₁₀ and emitter lying high frequency negative, as already decreases sharply at about twice the thickness of the alternating voltage with increasing distance from the junction between emitter and base zone at Basisansschlüß. As an effective emitter of this high current densities congestion of defect wide Bew can be 0.7 times of that Abelektronen on both sides of the barrier layer occur denote article from the edge of the emitter, in which a large increase in Erriittef-Basiskäpazität i ₅ wherein between the base and emitter lying _ ^ _i_,. _, * .. n _-. T_i _; _, - _: .-M.xt-. .. ■. ": - ■■., .. t, ^.". I! - i .... voltage to the 2.7th part of the input voltage

has fallen off. Bew is at the same time the width of a transistor with Rb = 0 - but with the same te, Tc, tb - which, with the same current density, each unä

However, the specific sheet resistance R _{B of} the base zone is relatively high. The specific surface resistance is the resistance of a square of the conductive base layer with which contact is made at the end faces. In addition, the emitter current densities jü take on considerable values at high cut-off frequencies h f _x and thus result in a high specific capacitive transverse conductance between emitter and base. This has the consequence that the between

has the consequence. In addition, results in the same base thickness a concentration curve in which near the barrier layer to the emitter a lower concentration of impurities predominates than in the middle of the base

. - _ ".— ig, Tc ₃ tb - -, which with the same current density each and

zone, a significantly larger base duration than a ₂ o same frequency / same amount of steepness continuity with constant or from dd Eiidtd fi ii

Concentration progression with a constant base substance or a base substance that falls from the emitter to the collector.

It is therefore unfavorable, in the case of semiconductor arrangements, which are intended to amplify extremely high frequencies, the emitter and base zones using the Dößpeldiffusion process to produce, as is the case, for example, with the known Tetrodenänordnüng is because there is always a weakly doped transition zone between the emitter and base zone, roughly the width of the base zone.

It is therefore advantageous according to a development of the invention to cut the pn junction between the emitter and base zone to be steep. Such a steep ρη-Übergaiig can z. B., as detailed below

Is carried out by diffusion from an alloy Emitter zone are produced, which in low density more rapidly diffusing impurities of the The conduction type of the emitter zone does not contain a determining conduction type, e.g. B. in a Germaniüm semiconductor body by adding Sb in the gallium-doped emitter. With this alloy-diffused process Under certain circumstances, the defects that determine the conductivity type of the base zone can be located directly on the Enrich the emitter boundary very strongly, so that extremely high static emitter-base capacitances occur.

However, this effect can be prevented if the emitter zone is not doped higher than the hardening density at room temperature T ₂ (at Ge about 10 ¹⁹ impurities per cubic centimeter) and if the and the input resistance has like a much wider transistor with finite Rb.

Since the / ₁₀ limit frequency is the specific transverse conductance of the static and dynamic capacitance

between emitter and base about the same —- is, receives

Urj \

one according to the known formulas for a homogeneous electrical conduction at the frequency / the relationship

whereby

Bε Wd -

and / _{10 is} the frequency at which the current gain has dropped to the value one without taking into account the marginal zone influence.

The speed frequency without edge zone (tr -s- 0) is for the arrangement used as a numerical example equal to 9.5 ■ 10 ^s Hz. At this limit frequency, the effective emitter width Bew is equal to 0.61 μ and at / = 3000 MHz about 1.1 μ.

The _{Grenzfreqüenz / fto is now greatly reduced} by the capacitance of the edge barrier layer between the emitter zone 3 and the semiconductor zone 6 of the electrode 1

set. Assuming a thickness Wr of ί μ for the emitter zone 3 and a maximum maximum basic doping N _Sm equal to or less than 5 ° doping ^ = 4JVi = 4 · 10 * ^ defects per cubic

is ~ - times the intrinsic conduction density m

that temperature Tn at which the base zone is produced by diffusion. Tz and Tp are measured in Kelving degrees. Then it should be cooled down as quickly as possible. At a temperature Td of 973 ^° K equal to 700 ^° G, the intrinsic conduction density n <approximately equal to 3.4 · 10 ¹⁸ disturbance points per cubic centimeter in germanium, so that a maximum basic doping of about 1
Centimeter is possible.

^{Assuming an approximately linearly sloping profile with 10 18} imperfections per cubic centimeter of maximum doping and a base layer thickness wb of 1.5 x 10 ~ ^B cm as an example for the course of the base layer, this results in a base transit time tb equal to 3.8 It based on known relationships ) - ¹² seconds.

g p

Centimeters, if Nb is the basic doping, _{XR is} approximately the same

W _R Bew

The _{Grenzfreqüenz} f ßl including the edge zone is therefore significantly lower than / _Ao j, namely 6000 MHz for the given calculation example. It is

¹⁸ imperfections per cubic ^6o are advantageous in this way to reduce the marginal capacitance

reduce that the emitter zone is made thin, so that the interface between the first electrode and the emitter region is equal to or smaller than that emitting area is.

Furthermore, it is favorable between the HäMeiterzoneö the electrode !, and the emitter zone3 to produce gradually extending pn junction. The best way to do this is to use the

9 10

Emitter zone 3 only about three to ten times as high as the base material and form an η-conductive base doped like the base zone 4 and zone 6 at least zone,
twice as high as the emitter zone. The metal layer is now in a suitable

If one now sets the final thickness Wb of the base acid, detached and divided into slices of about 1 · 1 · zone 4 only after the electrodes 1 5 0.5 mm in size have been alloyed. Then you alloy and 2 by brief annealing at a temperature in the usual way two alloy pills from about ratur her, which only slightly below the maximum 80 μ diameter z. B. from an In-Sb-Ag alloy alloy temperature, the slightly diffuse at a distance of about 130 μ on and annealed donors of the semiconductor zone 6 in the closing afterwards at a slightly lower temperature. After the emitter zone 3 and result in a flat, brief etching, it is covered after the photoresist pn junction. move along the connecting line between the

It should be noted, however, that the two alloy pills are about 70μ wide

Above relationships for a transistor with stripes and carries out a mesa etch. To

very broad emitting surface. Detaching the photoresist coating can cause the semiconductor

Only emits a narrow strip of the emitter, like i ₅ plates soldered onto a transistor base and with

With the arrangement according to the invention, the two silver ribbons will be contacted.

Current gain smaller. For transistors according to FIG. 2 is re-steamed

If one designates with bee the distance from the detachment of the photoresist coating z. B. zinc on the

Semiconductor zone 6 of the electrode 1, in which the surface of the transistor element on. On it covers

Emission of the emitter zone 3 on the 2.7th part ao one again by means of the photoresist process those

has fallen, in the worst case, namely places on the emitter surface, which have a metal

when the cut-off frequency should only be obtained from the static coating. On the uncovered

Emitter or edge capacitance is determined by brief etching in the zinc

diluted nitric acid removed and the semiconductor

. j £ c_. \ 25 component with base and assembly as above.

τ ε -t- Tu> - TbJ, jj _{m auc} j _{1 m} - _t spherical alloy pills

coaxial arrangements similar to those of FIG. 5

,,. ". ,. . j _ΛΤ , .. ,,. to be able to produce, it is advisable to use a

in vector notation the ratio: _TT ,,, .., .. ^. , _Λ '. / , ™ '. ,

Semiconductor chip after three or more transistors

ß I r. Bew \ ³ ° ° bi§ ^em process and this star-

- Equal to 1 / (1 + yj J, to be arranged in the form. Such a construction allows

Po V " Bee J _eSj all external electrodes of these transistors

with a perforated metal disc like the elec-

if β is the current gain of the tetrode, ß _{0 is} the trode 2 in F i g. 5 to contact and all internal current amplification of a transistor with relatively wide 35 electrodes together through a cylindrical or emission zone and j to contact the imaginary unit vector conical inner conductor, similarly represent. For Bee = B _E w , β becomes 0.54 · ß ₀ . as with electrode 1 in FIG. 5. You can also arrange the large-signal amplification and Schwingungser- transistors so that instead of several inner generation, it is advantageous to make Bee less than or equal to B _E w electrodes only one inner electrode is used, since then the entire emitter current 40 which all transistor arrangements in common is. can be controlled. Is for a reinforcement In the mesa-like pnip arrangement according to FIG. 3

small signals desired a high β, it can be produced Bee semiconductor wafers, which are advantageous in the interior to about 3 B _E w enlarged. At very heavily p-doped and is a uniformly thin, a strip-shaped transistor arrangement in accordance with the transistor depending on the type of about 1 to 10 μ strong, weak Fig. 4 Ibis constant base sheet resistance Rb 45 η-doped surface layer having,
is The easiest way to get such discs is when

η -η. ^{Se is au} ^ thicker slices of the desired

EE - τ Tj ' after weak η-doping of the surface layer

the conditions used for power rectifiers

Be is the width of the emitter zone 3 between 50 and an electrode 1 and 2 extending almost over the entire pane, Ut is equal to 25 mV and Ueb is alloyed with a large-area electrode (e.g. with In),
the operating voltage between emitter and base, the alloying and cooling conditions are like this

for arrangements made of germanium is about 0.5 V. to choose that the alloy front against the base-Thus with a linear arrangement Bee is approximately material as flat as possible and the monocrystalline and *** #. Depending oh _n the ^ nsehte ,, Betriebst- "

Thus, for the arrangement according to the invention, the alloy front is close below the opposite one

an emitter width of 10 to 100 μ is favorable. Disk surface.

To produce a transistor according to FIG. 1 goes at the edge of the disc becomes an n-doping

one z. B. of p-doped semiconductor wafers with 60 auxiliary contacts (base) and just like the

about 0.3 to 1Ω · cm in resistivity. In-electrode provided with lead wires and with

First, a p-doped coating with a suitable insulating varnish is evaporated in a high vacuum. They don't

of the metal, for example In with a little Ga, under the covered front side of the prepared disc

Addition of a small percentage η-doping is after a self-limiting electrolytic

Material (As or Sb) is etched in a thin layer on the 65 etching process. During the etching lies there

Semiconductor wafer and provides the emitter zone through between the rear electrode and the auxiliary contact

Alloy here. During post-annealing, the negative voltage diffuses, so that the contact on the back

movable n-type impurities across the alloy zone in a barrier layer, the thickness of which depends on the

Doping of the η material and the voltage at the back contact depends. Between electrolyte and A voltage is applied to the auxiliary contact, which is also negative, but the amount is less than must be the voltage between the rear electrode and the auxiliary contact.

With a strong light source, the pane to be etched becomes about 100 μ wider across the whole Slice of light streak projected through the electrolyte, which slowly, perpendicular to its longitudinal extent, is moved over the disc.

The germanium is quickly etched off in the illuminated areas. However, the etching stops by itself, if at one point the backside barrier layer, more precisely the barrier layer, which of the voltage difference Back side electrode electrolyte is reached.

In this way, you can produce highly p-doped disks which have a weakly η-doped thin layer precisely predeterminable ao Own thickness. After removing the cover and the metal layer on the back, they can Slices, as already stated, are provided with an emitter and base layer.

In the case of semiconductor arrangements according to FIG. 4, the Intrinsic zone 8 be thicker at the non-emitting points than at the emitting points. This can can easily be achieved according to the above process by first applying the one corresponding to the lower layer thickness Adjusts bias and exposed only those places on the semiconductor wafer where later the layer thickness of the intrinsic zone should be less than in the other places. Subsequently increased the bias is applied and the remaining surface is etched in strips in the manner described up to desired layer thickness of the intrinsic zone.

The in F i g. The course of the layers shown in FIG. 5 can be achieved, for example, by the following method. First, alloy in a disc of weakly η-doped semiconductor material at those points which should later result in a thinner high-resistance zone 8, about 10 to 15 μ. deep p-doping electrodes a. Then a thin layer of p-doping substance, for example In, is placed on this surface. applied in such a way that it covers the entire surface. On top of this layer is a second Pressed semiconductor wafer and this structure heated to alloy temperature so that the second Semiconductor wafer assumes a higher temperature than the starting wafer. This is how you get one Semiconductor body with a heavily p-doped and an η-doped half. Then the n-doped Surface removed by the method described so far that the previously alloyed areas are straight become visible as elevations. If this is the case, then 55, the etching process is ended.

The. The arrangement according to the invention can of course also be based on the double diffusion method or on other way to be made. The dashed line 15 indicates the boundary of the emitter zone 3 in each case before the two electrodes 1 and 2 are alloyed in. In particular, one can use the double diffusion method the base connections 6 and 7 produce by making these points before the emitter diffusion z. B. covers with a quartz layer. If you bring it up Then remove the quartz layer from the disks in a suitable metal salt solution, as it is e.g. B. to Making pn junctions visible is often used, so you can see the metal contacts on zones 6 and 7 1 and 2 separate.

The annular arrangement according to FIG. 5 can by vapor deposition of the alloy materials using suitable screens or by galvanic Deposition can be produced after covering the remaining semiconductor surface with photoresist.

In the embodiment according to FIG. 5, the electrode 2 surrounds the electrode 1. However, it is also one Embodiment possible in which the electrode 1 surrounds the electrode 2, in particular in an annular manner. Experiments have shown that such arrangements, in which one electrode the other perfectly encloses, allow the use of particularly thin base layers 4. This is because that the thin base zone 4 does not appear anywhere on the surface in these arrangements and therefore none Surface breakthrough through the thin base layer is possible.

Claims (38)

Patent claims: 1. Flat transistor with an emitter, a base and a collector zone, its base electrode attached to the same surface side of the semiconductor body as the emitter zone is, characterized in that on the same surface side of the semiconductor body an electrode carrying the emission current is attached, which is ohmic with the base zone and with the emitter zone ohmically or via a pn junction with a very low breakdown voltage connected is. 2. junction transistor according to claim 1, characterized in that between the base zone and the collector zone is provided with a weakly doped or intrinsically conductive zone. 3. junction transistor according to one of the preceding claims, characterized in that the transition between the collector zone and the high-resistance or intrinsically conductive zone runs as steeply as possible. 4. Surface transistor according to one of the preceding claims, characterized in that the high-resistance or intrinsically conductive zone has different thicknesses over its surface. 5. junction transistor according to one of the preceding claims 3 or 4, characterized in that that'die thickness of the high-resistance or intrinsically conductive zone between the base and collector zones is selected to be smaller in the area of the emitting part of the emitter zone than in the rest . Area of the semiconductor body. 6. Surface transistor according to one of the preceding claims, characterized in that the collector ^{zone is very heavily doped to achieve a low collector series resistance, for example with 10 18} to 10 ²⁰ impurities per cubic centimeter, and that in the operating state at least in the emission range the space charge zone of the collector-side pn junction extends over the entire width of the high-resistance or intrinsically conductive zone. 7. junction transistor according to one of the preceding claims, characterized in that the semiconductor body is mesa-shaped and, as a result of the mesa structure, the surface of the Base zone is less than or at most equal to the area of the collector zone. 8. junction transistor according to one of the preceding claims, characterized in that the interface between the first zone and the emitter zone is equal to or smaller than the emitting zone Area is. 9. junction transistor according to one of the preceding claims, characterized in that the thickness of the collector barrier layer is chosen such that the current gain in the emitter-base circuit at high frequencies, half or more is determined by the collector run time. 10. Surface transistor according to one of the preceding claims, characterized in that the collector voltage is chosen so that it is greater than a third of the breakdown voltage is the collector-to-base line. 11. Surface transistor according to one of the preceding claims, characterized in that the emitter current density is selected so high that the space charge of the drifting charge carriers in so the collector junction at the lowest operating voltage is just not disturbing makes noticeable. 12. Surface transistor according to one of the preceding claims, characterized in that the emitting surface is chosen so that it is 0.5 to 3 times as wide as the high frequency effective area at the operating frequency. 13. Surface transistor according to one of the preceding claims, characterized in that the pn junction between the emitter and base zones is steep. 14. Surface transistor according to one of the preceding claims, characterized in that the impurity concentration curve is chosen such that between the first of the two Zones and the emitter zone to achieve a low junction capacitance a flat one pn junction arises. 15. Surface transistor according to one of the preceding claims, characterized in that the alloy depth of the first of the alloyed into the weakly doped base or collector zone both zones is less than or equal to half the collector barrier layer thickness. 16. Surface transistor according to one of the preceding claims, characterized in that the first of the two zones is more heavily doped than the base zone. 17. A junction transistor according to one of the preceding claims, characterized in that the base zone ^{is offset by the order of magnitude of 10 18} imperfections per cubic centimeter. 18. Surface transistor according to one of the preceding claims, characterized in that the emitter zone is doped three to ten times as high as the base zone. 19. Surface transistor according to one of the preceding claims, characterized in that the width of the emitter zone between the two zones is 10 to 100 μ. 20. Surface transistor according to one of the preceding claims, characterized in that the first of the two zones surrounds the second zone, for example in a ring shape. 21. Surface transistor according to one of the preceding claims, characterized in that the emitter zone and the second of the two zones are connected by a metallic surface covering are connected. 22. A junction transistor according to claim 21, characterized in that the metallic coating is at least on part of the emitter zone and on the alloy surface belonging to the second zone rests. 23. Surface transistor according to one of the preceding claims, characterized in that the emitter zone is covered so far with the metallic coating that only the required Safety distance to avoid a short circuit between the metallic covering and the one attached to the first of the two zones ..- electrode is preserved. 24. The method for producing a junction transistor according to one of the preceding claims, characterized in that a semiconductor plate initially with an emitter zone and an underlying thin base zone and then the first of the two Zones through the emitter zone is alloyed. 25. Method of manufacturing a junction transistor according to one of the preceding claims, characterized in that the first and second zone can be produced by alloying. 26. Method of manufacturing a junction transistor according to one of the preceding claims, characterized in that the emitter zone by alloying using an additional counter-doping to produce the base zone Substance-containing alloy substance is produced and that then the base zone generated by diffusion from this emitter zone or from the liquid emitter alloy will. 27. Method of manufacturing a junction transistor according to one of the preceding claims, characterized in that the emitter and base zone through simultaneous or successive diffusion from the gas phase or produced by diffusion from a non-alloy substance applied to the semiconductor surface will. 28. A method for producing a planar transistor -according to one of the preceding claims, characterized in that the diffusion depth in the manufacture of the base zone by Diffusion is chosen smaller than the final thickness of the base zone and that after alloying the emitter-side electrode of the semiconductor body at slightly below the alloy temperature lying temperature is annealed until the final thickness of the base zone is produced. 29. The method for producing a junction transistor according to one of the preceding claims, characterized in that the absolute minimum temperature for establishing the base zone by diffusion is related to the absolute room temperature like the intrinsic concentration at the diffusion temperature to the desired maximum concentration of the basic doping. 30. The method according to any one of the preceding claims, characterized in that the Semiconductor body cooled rapidly after the production of the base zone by diffusion and in the further treatment is no longer heated so much that noticeable diffusion occurs. 31. A method for producing a junction transistor according to one of the preceding claims, characterized in that the base zone initially diffuses into a semiconductor wafer and that before the diffusion of the emitter zone those points of the semiconductor surface be covered with a suitable substance preventing the diffusion of the imperfections, on which the two emitter-side electrodes are provided. 32. A method for producing a junction transistor according to one of the preceding claims, characterized in that the covered areas after detachment of the covering material be chemically or galvanically coated with metal. 33. A method for producing a junction transistor according to one of the preceding claims, characterized in that a heavily doped platelet is used as the starting material which has a lightly doped layer under one surface. 34. A method for producing a junction transistor according to claim 33, characterized in that that when producing a pnip arrangement, the desired thickness of the high resistance Layer is produced by an electrochemical etching process in such a way that the heavily p-doped Zone is biased more negatively against the weakly n-doped layer than the electrolyte. 35. A method for producing a junction transistor according to claim 34, characterized in that that to achieve a high-resistance layer with thinner areas through electrolytic etching, the bias voltage corresponding to the thinner areas is set first and only these thinner areas are strongly exposed and that the bias is then applied and the remaining surface is etched down to the desired layer thickness. 36. A method for producing junction transistors according to one of the preceding claims, characterized in that three or more semiconductor systems simultaneously from one Semiconductor wafers are produced and arranged in a star shape to one another, that all External electrodes through a metal disk provided with a bore and all internal electrodes be contacted together by a cylindrical or conical inner conductor. 37. A method for producing junction transistors according to one of the preceding claims, characterized in that several junction transistors from a semiconductor wafer simultaneously produced and arranged to one another in such a way that instead of several internal electrodes only one common inner electrode is required. 38. Surface transistor according to one of the preceding claims with the exception of the claim 20, characterized in that the electrode of the second of the two zones is the electrode of the enclosing the first of the two zones, for example, in a ring shape. Considered publications: Belgian Patent No. 553 173; U.S. Patent Nos. 2,924,760, 2,657,360; Swiss Patent No. 335 368;
■ Journ. of appl. Physics, Vol. 30, 1959, No. 11, pp. 1819-1824; J. D ο s s e, Der Transistor, 1959, p. 51. For this ! Sheet of drawings 609 559/311 4.66 © Bundesdruckerei Berlin