DE1202310B - Synchronization method and arrangement for digital data transmission - Google Patents

Description

FEDERAL REPUBLIC OF GERMANY

GERMAN

PATENT OFFICE

EDITORIAL

Int. α .:

H04b

H04j; H041

German class: 21 al - 7/03

Number:
File number:
Registration date:
Display day:

St 21871 VIII a / 21 al
March 21, 1964
October 7, 1965

The invention relates to synchronization in digital data transmission with error detection and Correction.

It is known from data transmission to divide the information into individual blocks, each of which additional bits are added. These bits are used for error detection and correction and the bits appended to the individual information blocks subsequently become check bits called. Since the check bits are derived from the information, the transmitted blocks are redundant.

On the receiving side, you can also create the check bits from the data blocks and use the Compare transmitted check bits. If the two check bit groups are the same, then the relevant Transfer the data block correctly. But you can also do a mathematical operation with the received Block and the received check bit group. Results in this mathematical Operation got a predetermined result, then the block was transferred correctly. In the first case are the the two test bit groups are unequal or the predetermined result does not result in the second case, then there are one or more errors. The disturbed block is then usually repeated.

The invention now relates to a synchronization method for such known data transmission systems. There will be a method of synchronization in block-wise digital data transmission, in which the blocks each consist of an information bit group and one of these assigned test bit groups, each with the same number of bits, consist of the assigned Information bit group can be obtained and a cyclic one to form the test bit group Shift register is used, indicated, which is characterized in that at the beginning of a transfer on the transmit side, a predetermined code combination is first stored in the cyclic shift register which is processed with a predetermined information bit group in the shift register, so that a certain test bit group results, which together with the specified information bit group as Synchronization block is sent and that this block is recognized on the receiving side and used for synchronization is used. You can now either use the entire synchronization block or just the Transfer check bit group of synchronization block.

The invention will now be explained with reference to the figures, for example. It shows F i g. 1 an arrangement for data transmission,
2 shows a data or synchronization block,

Synchronization method and arrangement for
digital data transmission

Applicant:

Standard Elektrik Lorenz Aktiengesellschaft,

Stuttgart-Zuffenhausen, Hellmuth-Hirth-Str. 42

Named as inventor:

William Francis Sydney Chittleburgh,

Orpington, Kent;

Cyril Etienne Bloch, London (Great Britain)

Claimed priority:

Great Britain of March 29, 1963 (12 582) -

F i g. 3 shows a circuit arrangement for generating a synchronization block,

F i g. 4 shows another circuit arrangement for generating a synchronizing block.

The arrangement according to FIG. 1 contains a transmitter TX which is connected to a receiver RX via a forward channel FC and a reverse channel RC . The information is sent by the sender as blocks consisting of individual bits, each of which can be either 1 or 0, and a check bit group is assigned to each data block. In the arrangement described here, each data block has 244 bits followed by 12 check bits. The information and check bits are considered together so that the total block length is 256 bits.

When each block is received, a check is made, either by forming the check bit group from the information bits and then comparing it with the received check bit group, or by means of a mathematical operation which must provide a certain result as to whether the block was transmitted correctly. If no error is found in the test, it is assumed that the block has been transmitted correctly, while in the event of an error a repeat signal is given from the receiver to the transmitter via the transmission link RC . One of the many known possibilities of giving such a repetition signal to the transmitter is that if the transmission is correct, a signal is sent and if the transmission is incorrect, no signal is sent, in which case no signal means that the block must be repeated.

509 690/312

As in FIG. As shown in FIG. 2, the synchronization block on the transmission side consists of a data block which alternately contains 1 and 0 bits and the subsequent test bit group PE. The check bit group PE is examined for synchronization, and the recognition of this group in the receiver RX effects the correct synchronization. The synchronization itself can take place according to any known method and it is therefore not described in detail.

In the method according to the invention, the check bit group is derived from the information bits in a known manner of a block obtained by means of a cyclic shift register.

A cyclic shift register is a shift register that is divided into two or more sections, which are interconnected in a closed loop and each section with the next connected via a half adder. The information bits arrive at the second input of a half adder and the output of this half adder is with the second inputs of all other half adders tied together. The output signal can be taken at a suitable point in the circuit will. In the present case this is the output of the last stage of the shift register.

Such a circuit ensures that the information block is divided by a function, which depends on both the number of stages in the shift register and the division of the register into Sections depends. As known from information theory, one can use the check bit groups that are located at result in certain information blocks. One obtains with such a circuit arrangement a very good, secure data transmission without unnecessary redundancy being required.

In the present arrangement, the cyclic shift register has twelve stages and it is in two sections divided into five levels and a section divided into two levels. The check bit group therefore has twelve Bits belonging to 244 information bits.

The in FIG. The cyclic shift register shown in Figure 3 has three sections 1, 2 and 3 which, as mentioned above, have five, five and two levels. The sections 1 and 2 are with a half adder 4, the Sections 2 and 3 are connected to a half adder S and sections 3 and 1 are connected to a half adder 6. The output of the half adder 6 is also connected to the second inputs of the other two Half adder connected and the second input 7 of the half adder 6 is the information input. Of the Output 8 at the end of section 3 is used to accept the test bit group.

Before the transmission of an information block with 244 bits, the sections 1, 2 and 3 of the cyclic Shift register empty, d. i.e. all levels are at zero. The information bits are entered via the input 7 of the half adder 6 and arrive from there to section 1 and the half adders 4 and 5. If the information bits arrive one after the other, eventually all half adders work and a pattern is generated that is in a predetermined relationship to the information block entered. The check bit group generated in this way is immediately after the information bits of the block.

To generate the synchronization block, a certain code combination is first entered in the shift register which is called the start function. This is done in the same way as with normal information blocks the "information" part of the synchronization block, consisting of 244 bits alternating between 1 and 0 are entered into the shift register. The start function is parallel to the shift register from a memory 9, as in FIG. 3 is entered. The start function In the present case, the 12-bit group is 01111 00010 11. It is therefore section 1 of the Register is set to 01111, section 2 to 00010 and section 3 to 11. The storage takes place in the shift register when a start pulse reaches the memory 9, which at the same time the Initiates data transfer.

After entering the start function, as already described above, the 244 bits that form the "information" part of the synchronization block are entered into the shift register. The shift register is incremented in a known manner, the bits from the last stage of each part of the register reaching the half adder connected to it, where they are added without a carry to the information bits which reach the second input of the half adder. The bits in the three half adders are processed in this way and the result is that the shift register contains eleven 1-bits and one 0-bit at the end of the operation, ie it is set to 111111111110. This check bit group is sent to the receiver via the FC channel sent and recognized there as a synchronization code and used accordingly. It is also possible to transmit not only the synchronization check bit group to the receiver alone, but the entire synchronization block.

The circuit according to FIG. 4 largely corresponds to the circuit according to FIG. 3 with the difference that the start function arrives in series from a memory 10 to an additional input of the half adder 6. The arrangement is designed so that the start function of memory 10 is stored in the shift register is before the "information" part of the sync block to half adder 6 via its input 8 arrives.

The processing of the following information blocks takes place in a manner known per se.

The method or the arrangement was specified for a specific block length, for a specific start code, for a specific shift register. Of course, all modifications of the invention are also possible which are within the scope of the expert Action lie. The individual process steps are briefly summarized again:

a) the cyclic shift register is marked with a certain code combination;

b) the "information" part of a synchronization block, which is the same length as the information part a normal information block is placed on the shift register;

c) the marking that results after entering the "information" part of the synchronization block of the shift register is transmitted as a synchronization code over the line and on used according to the receiving side.

Claims (5)

_ Patent claims: 1. Method for synchronization in block-wise digital data transmission, in which the blocks each from an information bit group and a check bit group assigned to it consist of the same number of bits, -. which consist of the assigned Neten information bit group can be obtained and in which to form the test bit group cyclic shift register is used, characterized in that at the beginning a transmission in the cyclic shift register on the transmit side first a predefined code combination is stored with a predetermined information bit group in the shift register is processed, so that a certain test bit group results, which together with the predetermined information bit group is sent as a synchronization block, and that on the receiving end recognizes this block and uses it for synchronization. 2. The method according to claim 1, characterized in that only the test bit group of the synchronization block is sent. 3. The method according to claim 1 and 2, characterized in that at a block length of 244 plus 12 bits as a predefined code combination 01111 00010 11 and as a predefined information bit group an alternating sequence of 0 and 1 bits is used. 4. Arrangement for performing the method according to claims 1 to 3, characterized in that that as a read-only memory for the given code combination a non-destructive queryable memory (9) is provided, from which the code combination at the start pulse parallel is transferred to the assigned stages (1, 2, 3) of the shift register. 5. Arrangement for performing the method according to claims 1 to 3, characterized in that that as a read-only memory for the given code combination a non-destructive queryable memory (10) is provided, from which the code combination before entering the specified Information bit group in series in the assigned stages (1, 2, 3) of the shift register is transmitted. 1 sheet of drawings 509 690/312 9.65 © Bundesdruckerei Berlin