DE1283278B - Error detection and correction device for digital messages - Google Patents

Description

FEDERAL REPUBLIC OF GERMANY GERMAN WDWWl PATENT OFFICE

EDITORIAL

Int. CL:

German KL:

Number:
File number:
Registration date:
Display day:

H03k

G06f

21 al -36/26
42 h3 \ - 11/10

P 12 83 278.9-53 (W 23880)

August 9, 1958

November 21, 1968

The invention relates to an error detection and correction device for digital messages, the are to be transmitted via a noisy channel giving rise to error bundles, wherein which the message in redundant form, d. H. in the form of information and check bits to the channel delivering encoder has a multi-stage shift register, which is connected to the output stage to the channel is coupled and applied to the input stage with the information bits to be coded, and a decoder being provided which takes the redundant message from the channel again.

Errors can be detected when digit signals are transmitted over a disturbed channel or corrected that the transmission carried out with the system is redundant he follows. For example, errors can be detected by sending each digit twice. Likewise, errors can be made on a probability basis by selecting two of the same from three binary Digits are corrected when each binary digit is transmitted three times. The following are the binary Signals that are usually represented by the binary digits "0" and "L" as "bits" are designated.

A range of systems that enable refined error detection and correction, work according to the parity control principle. A parity control bit is a bit which is a Group of bits is fed to the checksum of the same bits of a bit group, even or odd close. Error correction systems which use multiple parity bits to match incorrect digits identify are known in the art. Some of them are in that among others Article "Coding for Noisy Channels" by Peter Elias explains which in the journal Institute of Radio Engineers Convention Record, Part 4, Section 14, pp. 37-46.

The prior art error correction systems have generally been developed on the basis that the likelihood of errors occurring in consecutive bits is unrelated to the occurrence of errors in the immediately preceding bit sequences. However, it has been lately found that in transmission systems the errors actually often occur in bundles. if thus z. B. the average frequency of errors in a given transmission system is 1: 100,000, can be the probability that the next symbol, which is an incorrectly transmitted symbol follows, is also incorrect, up to 1: 100 or

Error detection and correction device for digital messages

Applicant:

Western Electric Company Inc., New York, N.Y.

(V. St. A.)

Representative:

Dipl.-Ing. Hermann Fecht, patent attorney,

6200 Wiesbaden

Named as inventor:
David William Hagelbarger,
Morris Township, NJ (V. St. A.)

Claimed priority:

V. St. v. America August 15, 1957

(678 343),

dated May 1, 1958 (732 385) - -

even increase 1:10. Most of the improved Error correction systems are not able to correct errors that occur in a cluster.

The main object of the present invention, on the other hand, is to make the correction more bundled Allow mistakes.

In the few previously known systems which have a circuit for correcting multiple errors included, the overall circuit is in most cases so intricate that it can hardly be used in practice is. It is accordingly a further essential object of the invention to provide the circuits for the correction to simplify errors that occur in a cluster.

According to the invention, these goals are achieved through the use of coding and decoding devices, which work together with shift registers, for example with tapped delay lines and which handle the binary information continuously. Successive Parity control bits are formed and these parity bits are placed between the information bits a place inserted which of each information bit included in the parity check one Distance. While the received bits are shifted in the shift register of the decoder

809 638/1253

3 4

den, the valence of two different Pa- F i g. 14 is a circuit diagram showing the relationship between

rity control bits, both of which are specific bits, are used by the decoding control circuits and the traversal, checked, and corresponding parity control bits in the system according to FIG. 12 indicates output signals generated. That in both control group Fig. 15a, 15b and 15c statements, which the

pen can then be used in accordance with their other parity control bits for the data transmission system given parity output signals are corrected according to Fig. 16 specify,

the. An additional error correction and er- Fig. 16 a data transmission system with error

Averaging information can be provided by the rectification, with one control bit for each successive control output signals from two information bits is transmitted, and in be directed. io Fig. 17 and 18 working diagrams for the coding

The invention is characterized in that in the and decoding arrangement according to FIG. Encoders which check bits according to a pre- The F i g. 1 shows an embodiment of the continuous

given parity rule generating circuit with detailed error correction or error detection at least two non-adjacent positioning systems. According to FIG. 1, a binary Infordes Shift register is connected, so a check bit 15 mation from a source 22 to the shift register 24 the parity relation of the respectively created in these positions. The successive sliding positions are saved Represents bits of information and each denotes in the shift register 24 are denoted by 1 to 7 Information bit indicated in the formation of at least two designated blocks. The designation Check bits are received, as well as toggle switches in the encoder in front of the "shift register" in the sense of the present inspection are; the each check bit in the write to be transmitted includes circuitry, e.g. Insert the message train at one point, the lines that do not follow one another in sections the points in time can be sampled adjacent to those information bits, is put, from which this test bit is determined. In the shift register 24 with the help of the

has been, and that in the decoder shift register parity control bit encryption circuit 26 con and parity check circuits are provided, which are formed by 25 troll bits of some of the information bits, The control bits are activated with the aid of switch 28 mation bits and the corresponding check bit of a pa- inserted between the information bits; the so erity group Compare and the correctness of a held message is about a noise two Information bits shared by parity groups were attached to a transmission channel or a number line as well as transferring correction circles in the decoder. As can be seen, the parity convention has are that respond to signals from the parity check circuits troUbit-Bildungskreis 26 inputs that are received by the Poim Mismatch cases of the correct new versions 1 and 4 come in the shift register 24; averaged information bits with the actual in- the parity bit is used in the transmitted message formation bit, the corresponding information bit is inserted at a point that changes from position 4 correct. 35 several additional information and control bits

Further developments of the invention are removed in the sub-section. This distance is characterized in each parity claim. Bits contained in the control group enables

Embodiments of the invention are notification of errors that occur in a cluster, which explained below with reference to the drawings. Which are equal to or less than six bit periods, Drawings show in FIG. 40 as will be described in more detail below.

Fig. 1 is a block diagram of an example of the use of parity controls for error

Error correction system, detection or correction of errors is in itself

F i g. 2 shows a diagram to explain the work. A parity check bit can be summed up of the system of FIG. 1, tion of a group of bits can be formed. With loading

Fig. 3 is a more detailed circuit diagram of the system according to 45 train to Fig. 1 can thus the relationship between Fig. 1, each control bit and the information bits

Fig. 4 is a block diagram of an error detection which control is performed by the follow circuit given in conjunction with the circuit according to the following equation. Fig. 1 can be used, D + D = C (Mod 2) (T)

5 shows a more detailed circuit diagram of the error determination 50 14 ν > · \>

management district according to Fig. 4, where D ₁ and D ₄ mean the bits in the position

F i g. 6 is a state diagram for fault detectors 1 and 4 of the shift register, and C is the resetting circuit according to FIG. 5, animal control bits. So if, for example, both

Fig. 7 schematically shows the coding device of a further information bit in positions 1 and 4 binary implementation example, ^^ - ^ - ^ '55 are "ones" or if both information bits are bi-

Fig. 8 shows a decoder which is in connection with secondary "zeros", so the control bit is a zero, according to FIG. 7 should be used, but if only one of the two information bits

Fig. 9 is another embodiment of a deco an "L", then the parity control bit is leveling device, in connection with the coding device if there is an »L«. according to FIG. 7 can also be used, 60 The decryption device is in Fig. 1

Figures 10 and 11 are diagrams showing the mind right. Those of the noisy nis the operation of the system with a coding transmission channel 30 coming bit sequences device according to Figure 7 and a decoding device according to separated by means of the circuit 32; the Infor-F i g. 8 or 9 should facilitate, mation sections are added to the shift register 34.

Fig. 12 is a block diagram of another system 65 routed during the test sections to the slide to Error detection and correction, register 36.

Fi g. 13 is a diagram showing the operation. It has already been pointed out that the

of the system according to Fig. 12, parity control groups each have two information

Sections and a test section included and are formed on the encryption device. It It should also be noted that each information bit is only then included in a parity check group if it is in position 1 in the shift register 24 of the encryption device, and that it is then included in another parity check group if it is in position 4 located in the shift register. At the decryption device, the valence of these two Parity check groups simultaneously through the "i?" - parity check circle 38 and the "SV parity check circle 40 checked. Thus, the parity check circuit 38 routes signals from positions 1 and 4 of the information bit shift register 34 and from position 7 of the check bit shift register 36. In a similar way the parity check circuit 40 passes signals from positions 4 and 7 of the shift register 34 and from the Position 10 of the shift register 36. The only one common to both parity check circles 38 and 40 Input leads to position 4 of the shift register 34. Therefore, if both parity check circuits 38 and 40 one Indicate errors, the bit in position 4 is most likely incorrect. Accordingly the AND circuit 42 is energized to the reporting switch 44 to operate.

It should also be noted that an error indication from the parity check circuit 40, which is not from accompanied by an error indication by the parity check circuit 38 clearly indicates that the check section 10 is faulty. This finding is the result of an elimination process. The parity check circle 40 is provided with two further inputs, which come from positions 4 and 7 of register 34 come. If the information bit in position 4 were incorrect, an error signal would be sent to the Output of the two parity check circuits 38 and 40 occur; this possibility is thus with the above Acceptance switched off. The information bit of position 7 is not incorrect, since all Information bits between positions 4 and 5 in the shift register 34 are corrected. Accordingly only check bit 10 can be faulty. If the circuit shown as a decryption circuit has a Relay station used for further transmission over additional noisy channels should be, a correction circuit could be provided that the state of the test section in the position 10 of the register 36 changes when an error indication from the parity check circuit 40, but was not assumed by the parity check circuit 38.

It should be noted that the receiver evaluation circuit 46 with the output of position 5 of the shift register 34 is connected for the information sections. Position 5 has been chosen to avoid delays as small as possible, since position 5 is the first position at which the corrected information bits Are available. When the receiver evaluation circuit 46 at position 7 of the shift register 34 were coupled, a delay of two additional shift register intervals would be introduced will.

The diagram according to FIG. 2 gives the mode of operation of the circle according to FIG. 1 in more detail. It a sequence of information bits is assumed, and it is the resulting control bits and the transmitted code shown. The successive lines of the diagram of FIG. 2 give the successive shift intervals in the shift register 24 of FIG. In the initial state the one in the top row of the diagram in FIG. 2 includes the positions 1 and 4 are 0. Accordingly, the control digit which is in a on the right side of the shift register column C is shown, also a 0. In the next shift period, which in the second row of the diagram according to FIG. 2 is specified, the control bit and the information bit which was in position 7 is transmitted. It should be noted that a control bit is generated during this shift interval and that both an information bit and a control bit can also be transmitted during each shift interval of the register 24.

In order in the diagram according to FIG. 2 the migration of the two parity control groups in one In a simple way to indicate, the three bits which form a parity control group are by means of marked by a square. A second parity control group is identified by the appearance of a diamond crown which holds each bit within the control group encloses. It should be noted that the information bits, which are initially in position 1 of the shift register in the top row of the diagram according to FIG. 2 found in position 4 in the fourth row of the diagram according to FIG. 2 is moved. It is thus in the parity control group included, which is surrounded by squares; however, it is also included in the control group, which uses diamond crowns is marked. In the decryption device, this bit is the one in the two parity control groups is included, possibly moved to position 4 of the shift register 34. At this point in time, the parity control circuits 38 and 40 determine the value of the parity control groups, which by means of diamond crowns and squares according to FIG. 2 are marked, and correct the common bit if necessary.

3 depicts a more detailed circuit diagram of a relay arrangement of the system F i g. 1. To simplify the circuit and to avoid cross-connections, the relay windings are and relay contacts shown separately from each other. With this type of representation, a Relay denoted by a capital letter with an index; the assigned contacts receive the same name. The working contacts of a relay are indicated by a cross in the corresponding line and the normally closed contacts by a dash.

In order to identify parts of the circuit according to FIG. 3 with the corresponding circuit F i g. 1 are shown in FIG. 3 the larger units are marked with the same reference numbers, which is also shown in FIG. 1 have been used. The only difference is that the reference numbers in FIG. 3 are provided with an index line. For example, digit information source 22 'with encryption shift register 24' is in FIG F i g. 3 coupled in the same way as the «5 source 22 to the shift register 24 in FIG. Other components of FIG. 3, which have corresponding circuits in Fig. 1, are the parity control circuit 26 'the circuits 28' and 32 ',

g 8

the receiver shift registers 34 'and 36', the paris shifted the same way as above

ity group control circles 38 'and 40', which was correct- specified. The excitation of the relay Z ₂ and

turkreis 44 'and the recipient user group 46'. It is the opening of the normally closed contacts Z ₂ takes place at the same time

can also be seen that the circuit 44 'of the de-energization of the relay A ₁ , in preparation for the

F i g. 3 the tasks of both the AND circuit 42 S receiving additional input information

as well as the correction circuit 44 according to FIG. 1 fulfilled. from the source 22 '. Similarly, the in-

With the arrangement of the error correction system formation from a ^ 4 relay set to a B-Ren In the real embodiment .4 relay set, over the entire shift according to FIG. 3, it has been assumed that synchro-io registers 24 'and the remaining shift registers 34' and msiersignale both at the transmitter and at the 36 'in the circuit according to FIG. 3.
Recipients are available. To the use of the parity check circuit 26 'is a simple special channel for synchronizing to comparable contact network which Normally open and avoid, usual normally closed contact sets may contain at the decryption device, the relays A ₁ and A _t Liehe circuit means for the restoration of 15 assigned. The circuit 26 'contains a work synchronizing signals are used, iontakt ^ in series with a break contact A ₁ and

In Fig. 3, at the bottom left, there are three clock generator circuits or a further series circuit parallel thereto, which illustrates a synchronization circuit. These three circles normally closed contact A _t and a _{normally open contact A 1} distort simple frequency division circles as they hold. The parity control circuit 26 'is therefore described in the specialist literature. For this purpose, one state is on when the two relays have the same states of excitation, for example in William Keister's book, and the other state in "The Design of Switching Circuits," D. van No, when only one of the two relays is excited Strand Company Inc., New York, 1951. will.

The relays IfF ₁ and Z ₁ work with half the speed. The changeover switch 28 'alternates between the off

speed of relay Y; they work with opposite inputs of the last relay B ₇ in the shift register 24 '

tiger temporal staggering. Work in a similar manner and the parity control circuits 26 '; when the time

is the relay PF ₂ and Z ₂ are energized with half the velocity measurement relays Z ₂ and energized. The Re-

speed of the relay W ₁ and Z ₁ ; they too are in their table Z ₁ , which works at greater speed.

activity staggered in relation to each other. This time bed as the relay Z ₂ , carries out a scanning function,

measurement relays are designated with W ₁ , Z ₁ , W ₂ and Z ₂ to generate pulses of suitable length that are sent to the

net, taking into account that the Kon transmission channel 30 'are created,

clocks this timing relay at different The switch 32 'in the input of the receiver

Points of the circuit of Fig. 3 occur, which also contains a pair of work and break contacts

are removed from the clock circuit. th, which are assigned to the clock relay Z ₂ .

The time sequence of the information signals from 35 The output signals from the changeover switch 32 'are the source 22' is controlled by means of the isolating contacts W _2, the information section register 34 'and the cone. The shift register 24 'comprises seven control section registers 36' supplied. A buffer relay with BF belaispaare, which is marked with the capital letter A , is used to synchronize the input signals or B and the associated index 1 to 7, which are sent to the two shift registers. Each of the relays contains two windings, which is 40 ster applied. Each of the shift registers 34 'by division into an upper and lower section and 36' is provided with circuitry which has been indicated by the section. The information relay Z _{2 can be} set as described above in connection transmissions through the shift register are controlled by the pair of working and normally closed contacts described with the encryption register 24 '. The correction circuit 44 'is assigned to relay Z ₂ in the middle. This relay is switched on 45 of the shift register 34 '. The parity is shown in the representation of the shift register 24 '. Group control circuits 38' and 40 'control the Errel links below. The relay Z ₂ is activated during a movement of the relay J? and S, which in turn energizes the correct time periods which control the energization correction circuit 44 '.

time of the relay W ₂ overlaps, but the relay The parity of the first and fourth information W ₂ before the relay Z _{2 is} de-energized. After the ab- 50 bits and the seventh control bit, both relays for an activity group control circuit 38 'are checked _{in the parrying excitation of relay Z 2.} This is unexcited by a short period of time before the relay W ₂ becomes aware of the presence of contacts, which excites _{the relay ^ 1.} and A _{4 of} the shift register SR _{2 are} assigned, and

The information is received by the relay A ₁ through the presence of contacts that match when the normally closed contacts W _{2 are} closed. 55 relay A _{7 of} the shift register SR _{9 are} assigned. At this point in time, the working contacts of relay _{Z 2,} which is recognizable in the excitation circuit of relay R , are still closed. When the relay Z _{2 is} open. · In the same way, the excitation circuit changes state, its normally closed contacts are closed for the relay 5 in the test circuit 40 'contact / I ₄ before its normally open contacts open. That and A ₇ , which are assigned to the shift register SR ₂ , relay ^ remains in the state it was assigned to before the 60 and a contact A ₁₀ -, which had the control shift de-energization of the relay Z ₂ , as a result of the - register SA _{3 is} assigned.

Make contact A ₁ , which has a hold circuit for * It has already been pointed out that it

the relay A ₁ produces via the normally closed contact Z _2. is desired, the information bit between the posi-

If, in addition, the normally closed contacts of the "relay functions 4 and 5 in the shift register 34 reverse

Z _{2 are} closed, the ReIaIsB _{1 takes} the er-6g ren, if both parity group control circles on the

state of the relay A ₁ . Decryption device provides an error display

• If the ReMsZ _{2 is} energized again, the remote will be. In the circuit of FIG. 3, this is the case

Information from relay B ₁ to relay A ₂ in due to the excitation of the two relays R and S

9 10

shows. When examining the in the correction group according to the counting by the district 52. The

44 'lying contacts, it can be seen that work con- error bundles are in advance as information bits or

clocks of the relays R and S in series with break contacts classified as control bit errors. After the other

of the relay A ₁ in the excitation circuit for the relay B ₄ catchy classification of the output signals from

lie. If relay A _{1 is} de-energized, then the control circuits come, carried out once

If the excitation of the two relays R and S has been activated, deviations from the reported

Reversal of the state in the relay B ₄ can easily be determined according to code sequences capable of transmission.

Occurrence of a shift signal. In the same way, if such a discrepancy occurs, the

the normally closed contacts of the relays R and S are operated in series with alarm circuit 56. After the final treatment

Normally open contacts of relay A _t connected to the io of a fully identified correctable

Exclude excitation of relay B ₄ , if the error bundle is activated the circulation circuit 58,

Relay A ^ has been energized. However, if only one and the components of the error correction circuit

the relay R and S is energized, the state will be restored to its original state.

of relay A ^ to relay B ₄ . On the other hand.

Then and only then, the information bits are measured. FIG. 5 illustrates a relay circuit for

corrected when the two relays R and S energize the fault detection circuit according to FIG. 4. The in

will. F i g. 3 designations used are also in F i g. 5

Receiver utility circuit 46 'receives signals from used. The relays R, S and Z ₂ are also in the relay B ₄ , which is the first digit in FIG. 3 provided. In contrast, the relay contacts, shift register 34 'are formed, at which the corrected ao which the parity group control relays R and S information bits are available. The working contacts and the _{timing relay Z 2 are} assigned, in which the switching act W ₁ and the normally closed contacts Z ₂ practice timing according to FIG. 5 additionally shown
solution functions and leave a time-accurate An essential component of the circuit according to the measured output signal pulse to the useful circuit Fig. 5 is a step switch. The step switch has passed 46 '. 25, a switching coil 60, a reset coil 62, and three

The system according to FIG. 1 works in matching contact banks, each of which has a "switch-off mode such that it has error bundles of up to six faults" and ten contacts that learn to be corrected in this way. If longer error bundles occur, it is advisable that an alarm circuit is actuated one after the other with the movable console. The clocks of the switch come into contact. The majority of these long burst errors can DA 30 step switch also includes normally open are determined by, that the sequence of the initial head contact, which checks at two locations in the scarf transition signals from the parity circuits to RS. The exercise diagram in Fig. 5 appears. The types of errors that are consistent with the head, for example, the clocks are closed when the step switch, the original message in another message, leaves its idle position. After an initial change, which information and control bits 35 pulse that is sent to the stepping coil 60 when closing, which are arranged so that they correspond to the relay R according to FIG. 3 assigned Arbeitsgen message correspond, of course, no contact is created, thus enable the head to be established. In addition, if two control bits contact the continuous advance of the step at a distance of exactly six bits in the over-switch by means of the _{message coming from the normally open contact Z 2} , 40 results in the shift pulse. The circuit according to FIG. 5 this error combination, the reverse of a rieh- classifies the errors essentially in two main information bits. categories. After this preliminary classification, the

The large error bundles that are longer than six activities are checked by the parity control circuits R and S; Bits, however, can with the help of a relative cause the error bundle, which the area simple circle are determined, which exceed the capacity of the circle in the form of a block diagram in FIG. 4 is shown. F i g. 4 activation of the alarm relay AL according to FIG. 5.
shows the receiver and error correction circuit. The operation of the circuit according to FIG. 5 can be seen in FIG. 1 and also an additional error - best in connection with the status slide detection circuit. The in F i g. 4 shown error detection program according to FIG. 6 describe. The general circuit consists of the time pulse source 48, a start 5 °, the errors are initially classified into those, circuit 50, a counting or incrementing circuit 52, one that is possibly correctable and either a classification circuit 54 for error bundles, one with an erroneous check bit or with an error alarm circuit 56 and a reset circuit 58. When information bits begin to stick. According to FIG. 6, an output signal of which this determination occurs after the sequence status parity group R occurs during operation, the control 55 is carried out, which is indicated by the start of the counting circuit 52. The letter D is indicated by the circle encircled by 38. In detail, circle 54 compares the output signals from the pari- in F i g. 6 the rest position of the circle 5 is indicated by an activity group control circles 38 and 40 during a large block, which in the representation of successive time segments with the output right above with the signals surrounded by a circle, which is indicated during correctable error 60 letters A. In this state, bundles of errors, which can be handled by means of the error correction switch, the step switch in its rest position, can occur. For the with all movable contacts of each contact-purposes of this comparison implementation the bank in the in F i g. 5 are in the positions shown, correctable error bundle with the help of the circle and all relays AL, M, N and T have dropped out.
ses 54 classified. The signals from the parity control 65 If, according to the determination of the i? Parity control circles 38 and 40, there will be no parity errors in the classification circle 38 of FIG. 5 applied in this rest position, subsequent shift intervals, - namely when an error occurs in the jR parity circle

11 12

the tap changer is advanced to level 1. In the case of the R 'signal, the transition from the state!) To the additional state, which is indicated in FIG. 6 by the state with an E according to FIG. 6.

Circle surrounded by letter, with regard to the state E in Fig. 6 is to be noted-

the relays M and N are still unexcited. It should be noted that the step switch is in step 4, each arrow direction indicated in Fig. 6, which 5 det and that the relays M and N are de-energized. The transition from one state to the other indicates, with regard to the state L according to FIG. 6, however, one or more of the letter designations indicate that the step switch is identified in its rest gene R, R ', S or 5'. The designation is and that the relays // and M are energized. R indicates a parity error, which is of the. The step-by-step correspondence between the λ parity circle 38 of FIGS. 4 is determined. The absence of the state diagram in FIG. 6 and the circuit of an R-O parity loop error is indicated by the designation order of FIG. 5 should now nungi in detail? ' indicated .-- In a similar manner give the be considered. As already mentioned, in the case of the letter designations 5 or S 'it is indicated that a par actuation of the .R closing contacts the switching coil is present (5) or absent (S'), 60 excited, whereupon the step switch is in its rest position namely according to the determination of the S parity 15 leaves. The head circle 40. of FIG. 4. Contacts belonging to the i? -Ärbeitskontakten parallel lie-Each operating cycle of the ZeitrelaisZ ₂ of FIG. Gen 5, the H-contacts to bridge short, and that is, during each cycle by a change in the arrow state in Z ₂ -Arbeitskontakte 6 shows / during such work cycles, energized in stepping coil 60, until the step switch is not reset by the R parity circle. Accordingly, if the progress is reported, the state of the circuit follows after the step switch has been moved to stages 1, 2 and 3 to F i g. 5 the arrow labeled Ä '·, which is attached to the states B, C and D according to FIG. 6 to produce, status in Fig. 6 is connected. Although this is after stage 4, the branching state of the circuit according to FIG. 5 does not actually change the presence of the state diagram, but it can, on the basis of the circuit arrangements according to FIG. 5 required state diagram can be viewed as if it were borrowed. When leaving state D , the arrow R ' switches from the stand oil back to the same step switch, always to step 4. If A follows below this state. The state A with the state B circumstances the relay R is energized, the relay T is connected, arrow is denoted by R and indicates, energized, over the path that the line 63, that the parity error caused by a .R parity signal 30 a normally closed contact M, a normally closed contact N, one is shown, causes this transition. The normally open contact R, a step designed as a working contact to the state C and to the state D the head contact of the step switch, the line are connected to a step switch in on the top and right side of the diagram to the steps 2 and 3 respectively, and although it includes independently of FIG. 5, and through the closing _{contacts Z 2} , whether or not Pari 35 returns the negative potential point during these incremental intervals. As a result ity input signals occur, the excitation of the relay T will be the working con-From the state!) The circuit is after clock T in series with the normally closed contact Z ₂ and the Fi g. 5 closed depending on the reset coil 62 from the equality check circuit. The step switch supplied signals in the "the state" or "to the state" is accordingly set during the second half of the ArstandL. If no output signal is reset by the 40 work cycle.

R-parity circle arrives, as indicated by the symbol R '. It has already been stated that during the transfer

If the error is made from state D to state L, it appears that the relay is excited about a correctable check bit error to read N and M. The ones in series with the act. In this case, the circuit after relay M and that to the contact bank 2 of step-Fig. 5. To state E according to FIG. 6, the connected negative potential point is switched 45. If, however, the parity circle 38 causes a normally open contact T lying on parity, the excitation indicates errors, then the circuit according to FIG. 5 of the relay M. In addition, the relay M has Kon-ZU the status! / Advanced. This means that the cycle in which the contact closure of the Kon error is presumably preceded by a correctable information separation is the excitation of the remation bit error. 50 lais M via the normally closed contacts M to enable.

The practical meaning of this error classification- In addition, the relay N is excited immediately after the failure results from a check of the de-excitation of the relay T. The way for the and lower shift registers according to Fig. 4 and the excitation of the relay N begins at the negative connection to the i? -Parity circle 38. After the on potential point below the contact bank 1 and represent the initial i? -Parity error signal, which runs via the push-button break contacts PB, the Ches the transition from the state A to the state B normally closed contact Γ and the normally open contact M, the reverse, can either be the information bit in the relay winding M and the resistor 64. The parallel first position of the upper shift register or that to the normally open contacts M and the normally closed contact test bit In the seventh stage of the lower slide Γ - the N / O contacts close a register may be faulty. If the information bit 60th holding circuit for the relay N. is faulty, a second jR parity circle error, jm-above, the branching of the first three shift processes would occur. The resulting signal from the state!> To the end of the line, labeled R , causes the change in state E or L considered. The state E can be over be of the state! " to the state L, as / esTin K lead to the additional state f, and is indicated in FIG. If; However, the check bit in the state L can lead via X to the states M, N seventh position 'of the lower register is incorrect, or O and lead to the state P. These two are no further output indications of the jR-Pari-way should now be expected in connection with the circle of activity. Accordingly, the circuit of Fig. 5 can be identified in detail.

13 14

If the relay R is not energized, as shown in FIG. 6 moreover, when leaving the state L in, through the transition from the state D to the state Y , in which the alarm relay is indicated, the step switch 60 AL remains energized. The alarm relay will switch to its normal switching operation upon response to FIG. These occur with an S-signal and in the absence of an R- step circuit, the state ^ to the 5 signal can be excited. From the physical point of view, continue state K , in which the step switch corresponds to that in FIG. 4 reached level 10. If the relay 22 is in operation for which it was initially determined while the step switch was from level 4 to, that the information section in the shift switches to level 10, which the transition from register level 4 is faulty. Thereafter, the Kon state produces E to state K in FIG. 6 corresponds to, io trollbit, which is from position 9 to position 10 ■ so the alarm circuit is energized. According to Fig.5 has been moved, an error. It is the connection to the alarm relay AL by this clearly to the part of an overmeasured faulty connection with the levels 5 to 10 at lerbündels, so that the excitation of the alarm relay is realized geder contact bank 1 of the step switch. is messenger.

This circle is at a point close to stage 5. The three states M, N and O correspond to closed and run via a normally open contact R cases in which a control bit error has not yet occurred and a closed head contact has occurred along one. After the occurrence of a control seal and a bit error recognizable on the right in the circuit diagram, the status according to FIG. 5 shifted from L or line and via the contact Z ₂ to the negative M or N in the state P. In all fall potential point. Since the working contacts R in this ao len are in connection with the state O of the over-circle, the alarm relay is energized every time, transition to state P. The states L, M, N and O if after the transition from the stages !? to K are characterized in that both the pure error occurs in the ^ parity check. relay N and relay M are energized. After this

According to FIG. 5, the progression of the step transition to the state? However, the relay M switch falls into the tenth stage with the result that the fort as is from, while the relay N remains energized,
circuit during the second part of the timed The transition from the states L, M and N to the stepped cycle is automatically reset. This state P presupposes that the relay R is energized is brought about by the negative potential, which and the relay S is de-energized. Under these circumstances at the contacts in step 10 of the contact the normally open contacts R and the rest contact 3 of the step switch are connected. From the 30 bars S both closed. Now the source of this negative potential is from the Re- F i g. 5 the stages 1, 2 and 3 of the contact bank 3 connected to lais T during the first half of the stepping cycle, the negative potential point, and while the second half of the cycle is energized via the normally open contacts M, the rune after closing the normally closed contact Z ₂ the reset - Clocks 5, the normally open contacts R, the head contacts of the coil 62 of the tap changer energized. It should be noted, 35 step switch and the normally closed contact Z ₂ . Therefore, this process becomes similar to the process after the relay T is energized. When the relay T is energized, transition from state D to state L according to the normally open contacts T close the circuit between F i g. 6 discussed above. The contacts 1 to 4 of the contact bank 2, the relay N and M , however, in the event of a return, the working contacts N to the positive side of the coil position of the tenth stage of the step switch 40 of the relay M leads. As can be seen, a negative one is not energized, because of the lack of the potential point on the movable contact of the circuits of the excitation circuits of the relays N contact bank 2 of the step switch, and M connected to the stage 10 of the contact bank 2 of the step- If accordingly the normally open contacts T close, so switch. As in the previous case, in which both sides of the winding of the relay M chem are the energization of the relay T was explained, 45 is at the same negative potential, and the relay, the relay T is reset to the de-energized state, is de-energized. The resistor 65 is provided in order to open the head contacts in its holding circuit to short-circuit the power supply when the step switch is reset. to the.

Incidentally, it should be noted that the number of stages in When the circle of FIG. 5 takes position 0,

of the step chain from state E to state K 50 so the next following step of the step

is determined by long error bundles with a switch, which briefly reaches level 4, a

a control bit error can begin. Transition to state P, in which the

In the foregoing, the possible error consequences are the step switch is in the rest position. this will

have been considered, which begin with an error, by connecting to contact 4 on the contact

which, as a correctable control bit error er 55 bank 3 of the step switch, which

seemed. The classes of clustered faults that relay T energizes when both relays M and N are energized

due to the transition from state D to state L and make contacts M and N are closed

are those where the will be. In this case, a similar sequence of

Initial error a correctable data bit error contact actuations to the above-mentioned result

seems to be. It is now shown in Fig. 5 superiors 60 NIS, ie the _relay} N remains energized and the relay M

The circuit shown will be considered, which is to be checked.

function of the following error bits and for determining the status L and status M

is used to determine whether error bundles in this class are reported. The excitation of relay S without simultaneous excitation

are able to work. excitation of the relay R the displacement of the circle S in

As FIG. 6 shows, state 65 branches off into state Y, in which the alarm relay is energized

diagram from state L to states M. This process is accomplished by connecting to

and P. In the case of the continuing from the rest position, the contacts 1 and 2 in the contact bank 1 of the

The circuit sequence can be accomplished by the circuit according to Fig. 5 step switch. You are over the

15 16

moving contact of the step switch. one side is. The reset process is connected via the contacts in of the alarm relay AL and is also carried out at the seventh stage, which is assigned a negative potential via the working contacts M to the contact banks 2 and 3. In detail, the normally closed contacts R, the normally open contacts S, the head as follows. The contact assigned to stage 7 of the contact bank 3 contacts of the step switch and the working contact 5 energizes the relay T to the cycle Z ₂ . After the occurrence of a 5-signal to initiate the usual reset cycle, and the Aale-leaving the state test, the excitation of the negative potential at the contact 7 of the alarm relay circuit is accomplished by means of the circuit- contact bank 2 makes the relay N ineffective. The ligt, which is located at the contact of the contact bank 1 of the circle according to FIG. 5, is accordingly again coupled to the step switch. The negative potential io in its normal or idle state, whereby the is switched to the alarm relay via the normally open contacts N, the step switch assumes its normal position, and M and S, the normally open contacts of the step switch and the relays N, M and T are de-energized,
the working contacts of the ReMsZ _{2 are} created. Once the alarm relay AL is energized, it is The reaching of the state P means that little need to press the release button, at least a data error has occurred; In addition, 15 whose contacts are designated PB in FIG. 5, thus making it clear that the circle only allows two additional control bit errors can. The correctness of this critical relay and the relays N and M are interrupted. The rien results from a consideration of the status of the push button also contains contacts which reset the decryption device according to FIG. 4 in the on 20 step switch. Two signal lamps are provided to indicate the addition of a data bit error, as is known from the status of the error detection circuit according to FIG. 5 (transition from state!) To state L. The yellow alarm is made. Under these circumstances, the lamp lights up during the actuation of the circle transition from the state P or from the connection according to FIG the Zudes relay S. Following the state Q are the status in Fig. 6 corresponds. The red alarm lamp does not allow any further new errors. Accordingly, when the alarm relay is activated,
the failure of the parity circle R causes the Erre- FIGS. 7 to 11 relate to an error movement of the alarm signal. rich actuation system, which the system of FIG. I ₅ The separation distance between successive 30 2 and 3 is very similar, but the magnitude of error bursts is determined by the steps, which is the additional signal transmission substantially smaller by the states of T to X of the state diagram. In the case of the system according to FIGS. 7 to 11, it is indicated in each case according to FIG. 6. Any additional check bit for every three additional information errors that were added to the decryption pre-bits, while in the circuit according to the direction according to FIG. 4 arrive, one check bit is first detected by 35 FIG. The aggravation for this continued the shifting of the circle according to FIG. 5 in the reduction of the additional signal transmission in alarm state Y. It can be seen that the state W must be purchased, is that the and the state X the above The circles explained above are expanded somewhat and that F and the state G corresponded fairly precisely to 40 longer groups of correction bits. This means that the step switches are required in error bundles,
The fifth and sixth stage is located and step- Fig. 7 shows an encryption arrangement with wise to switch further, if the relay R does not enter three information bits shift registers 66, 68 and 70. Activity, on the other hand, actuate the alarm relay, the coming from the line 72 Information when relay R is energized. As mentioned above, the 45 bits are distributed to the three shift registers 66, 68 and, the excitation circuit for the alarm 70, through the switching circuit 74 and relay AL , comprises the movable contact in the contact, the input buffer circuit 76. The used Buffer bank 1 and the one at the contacts 5 and 6 of the circles are relatively simple and need taktbankl coupled circle that save the working contacts only a few sections, namely estate / ?, the head contacts of the step switch and 50 speaking the number of used Sliding the normally open contact Z ₂ contains. For the state T register. The buffer circuit 76 is required to receive the input and the status! / From which the step bits from the input conductor 72 with a high switch reach the contacts 3 and 4, the beta speed and the distribution of the feedback circuit for the Alarm relay AL essentially bits on the three slower working shifters of the same. If thus the step switch from the 55 register 66, 68 and 70 synchronize. When this state T reaches contact 3, the actuating arrangement contains a third of the input bits to supply circuit for the alarm relay, the normally open contacts N, for each of the three shift registers. The normally closed contacts M and T and the work con parity control circuit 78 takes signals from the takte7 ?, in addition to the work contacts, - positions 1, 3 and 5 of the shift register 66, from the incremental relay and the relay Z ₂ . The connection from positions 7 and U of the shift register 68 and clock 4 is connected to the same aUggmeinen circuit via the opening contacts of the relay T from positions 13 and 15 of the shift register 70. After there are individual connections from each of these attainment of the state X without the occurrence of one to seven positions to the parity control circuit 78. In additional errors, the circuit is in its rest - the schematic representation according to FIG. 7, however, is postponed, which is only a single one. Head-provided, who sprayed the pose. This means that a sufficient protection department and the parity control circuit are connected, that the status has been run through and that the circuit is actually made up of numerous individual conductors prepared for the correction of further error bundles. The outputs from the shift registers

17 18

66, 68 and 70 and from the parity control circuit 78 The bits in the shift register 90 are between

positions 17 and 18 are corrected via the buffer circuit 80 with the circuit 82. The posi-

coupled. The circuit 82 samples the outputs of the tion 17 located in the parity groups indicated by

three shift registers and then adds a parity to the circles S and T are checked, but not

bit in the transmitted message. 5 in the parity group controlled by circle R

8 shows a decryption arrangement that is being transmitted. Accordingly, the correction circuit which is in connection with the encryption circuit 106 by the output from the AND circuit 108 of FIG. 7 can be used. The input controlled, which has the inputs R ', S and T. It is circuit 84 to the output circuit according to it is also to be taken into account that an error in the FIG. 7 synchronizes and distributes the incoming io position 23 of the shift register 92 an output pulse signal to the four shift registers 86, 88, 90 signal from the parity group control circuit T and 92. The buffer circuit 94 is between the circuit, but not from the circuits R or S. Under circuit 84 and connected to the shift registers, to these circumstances the control bit can be synchronized between the input pulses, which are corrected at positions 23 and 24 at the shift registers when attaches. In the lower 15 this process is desirable. The corrected informational right corner of FIG. 8 are three parity grouping bits are shown connected to the output circuit 110, which are marked with R, S and P , specifically by means of the buffer circuit 112 and. Each of the three parity group controls of the output circuit 114.
circles is connected in such a way that it has a bit group F i g. 9 shows a decryption circuit which controls, specifically in accordance with the parity ao, instead of the decryption arrangement in accordance with the control group pattern, which is defined in the locks in FIG. 8 in connection with the encryption arrangement according to FIG. Thus the order of Fig. 7 can be used. Many of the probes, for example, the parity group control according to FIG. 9 circuit components used circle R bits from positions 1, 3 and 5 of the match with those of FIG. 8 match. Accordingly, gisters 86, from positions 7 and 11 of register 25, the reference numerals according to FIG. 8 are also used in 88, from positions 13 and 15 of register 90, FIG. 9 is used, with a prime, for those and those circles from position 19 of the parity shift register, which have comparable functions 92. This grouping is exactly the same as exercising. The basic difference between them is shown in Fig. 7. The parity group control of the decryption arrangement of FIG. 9 and the circle S checks a similar group of positions, arrangement according to FIG. 8 consists in the use which, with respect to the signals sampled by the parity group con- of only one parity control circuit 120 and one trolling circuit R , are shifted to the right by two positions of parity shift register 122 instead of the three. Similarly, separated parity check circuits R, S and T are the controlled from the circle T positions bezug- Fig. 8. The komlich from the parity control circuit 120 of the scanned by the control circuit S posi- 35 Menden signals are applied to the five positions functions to two more places to the right equipped parity shift register 122 shifted connected. sen, and the parity group bits are specified by the

As can be seen, the error correction process finds shift register 12 shifted, and in fact synchronously

between positions 5 and 6 in the sliding with the shifting of the information through the

register 86 instead. It can also be seen that the 40 shift registers 86 'to 92'.

Position 5 is the only position which is in the It is easy to show the signals in the first

Parity control groups of all three control circles R, S third and fifth position of the shift register 122

and T is included. Accordingly, if an erroneous F i g. 9 with comparable input signal conditions

bit reaches position 5, occurs on the lines of the signals in the parity control circles R,

tungen.jR, S and T each have a signal that corresponds to 45 S and T. It should first be noted that

Indicates deviation from parity through all of the inputs to the parity control circuit 12 _{0 of} the

three parity group control circles is determined. The F i g. 9 the inputs to the parity control circuit R

Correction circuit 96 is actuated to correct the bit between FIG. 8 corresponds. Furthermore, they correspond to

see the positions 5 and 6 of the shift register 86 adjoining spaces consisting of two bits

to reverse when all three input signals R, S 50 of the parity circles S and T at the parity control

and T at the input of AND circuit 98 on circuit R of FIG. 8 each comprising one bit

step. Intervals in the parity control shift register

The errors contained in the bits in the shift register 122 labeled S and T in FIG. The 88 occurring are corrected between positions 11 and remaining circuit illustrated in FIG. 9. The position 11 in the shift register 55 operates essentially in the same way as 88 is contained in the parity groups which are controlled by the comparable circuit in the decryption circuits R and T , but not in the arrangement shown in FIG.

the parity group which is controlled by circuit 5 The circuit for correcting the control. Accordingly, the error correction digit is not shown in FIG. A suitable circuit can of course be provided in circuit 102 through the inputs R, 5 "and T in passage 60, which circuit is set according to which is applied to the AND circuit 104. The pattern of FIG. 8 is implemented signal S 'is the in the Boolean algebra off door of the check is desirable in relay stations, pushed symbol for the antioclenten value whereas in terminating stations, where the Inforbinären size S. thus, when the line S that is the mation directly recycled, If such a basketinary symbol "0" is de-energized, the 65 correction is generally not required.
Line S "energized to represent a" 1 "; and Fig. 10 tabulates the operation of when line S is energized, line S 'will represent the circuits of Figs. 8 or 9. Not in the table 10 is the excitation of the conductors R, S or T

8 or 9 with a "1" and the excitation of the conductors R ', S' or T ' with the symbol "0". As indicated in the first four lines of the listing of Figure 10, no rectification operation is required when conductor T is energized; the combination of signals on the conductors R and S can be arbitrary. When all three conductors R ₁ S and T are energized, the bit in position 5 of the shift register 92 or 92 'is set up in the parity control information according to FIG. 10 can be converted by omitting the zeros which appear in the second and third intercepts of each error characteristic. In the decryption arrangement according to FIG. 8, the connection of the parity control circuits with the positions which are separated from one another by one position serves to eliminate the zeros in the error characteristic which are present at the output of the

correct if it is transferred to position 6. io parity control circles R, S and T occur. When only the conductors R and T are energized, the decryption arrangement according to FIG. 9 is the

same function through the use of two additional positions in the parity control shift register 122 reached through which a distance

will. As an aside, it should be noted that the second, third and fourth test displays of FIG the displays after lines 5 to 8 may be of the same figure.

. From F ig, 9 it can be seen that the reset 126 is connected to the line Γ. The digits R, S and T of the shift register 122 are therefore reset to "0" each time the

the bit in position 11 of shift register 88
or 88 'corrected when transferred to position 12. Similarly, the bit in the
Position 17 of the shift register 90 or 90 'can be corrected between the positions labeled R ₁ S and T when it is transferred to position 18. Overviews according to the type of FIG. 11, specifically for the case that only the conductors and setups according to the type of FIG. 10 and the and T are excited. If, finally, the conductor T is excited to facilitate the analysis and the conductors R and 5 are de-excited, then the possibilities that are available when the control bit between positions 23 and 20 coding schemes are proposed can be used. The list after 24 of the control shift register 92 or 92 'corrected FIG. 10 gives all possible combinations of

Outputs to the three ParitätsgruppenkontroUkreise, and the last four rows indicate the four combinations, which represent the berichtiguhgsf ähigen error in the four shift registers.

The error characteristic according to the list above illustrates the output during successive time intervals of a parity control circuit depending on individual errors

Line T is energized. The delay circuit 128 is 30 of bits in one of the four shift registers. The second in series with the line 126 is provided to ensure a and fourth column in the fault characteristics are suitable pulse output from the circles R ₁ S insulating columns and affect after the and T before the resetting it starts. The purpose of the reset process is to prevent parity control signals. This distance between the interaction of an error correction group in Fig. 35 see the effective error correction bits enables the shift register 122 with the next successive light the independent correction of error correction groups is avoided. two consecutive faulty bits in any

The list according to FIG. 11 shows the error in one of the shift registers.

Characteristics of the possible errors in each of Fig. 11 gives the relative time position of the error

Shift registers 86 'to 92' of FIG. 9. The sequence of 40 characteristics according to the above table for output bits from parity control circuit 120 of the four consecutive incorrect message bits, FIG. 9 in the form 10101, thus shows an error
in the shift register 86 '. In a similar way
an error in the shift register 88 'is caused by a
Sequence of output signals displayed by the 45
Parity control circle 120 in the form 10001. An error in the shift register 90 is detected
indicated by a sequence of output signals 00101. Finally, there is a sequence of output signals from the parity group control circuit 120 to be shifted to the right or to the left without an error in the form of 00001 in the control that a fault is occurring. An error section register 92 'is thus displayed. Avoid the information relating to a bit that is applied to a given one of the error characteristics for the shift registers 86 ', shift registers, when an error is introduced in an 88', 90 'and 92' in the following table 1 other bit that is on the same

Shift register is applied, and the original

starting with the to the shift register 86 'of FIG. 9 applied bit. The bottom row in Fig. 11 gives the superposition of the graded Defect characteristics of the first four rows. As can be seen, each characteristic is fully identifiable, there is no interaction between the error characteristics. In addition, can each individual defect characteristic by one position

specified.

Fault characteristics Specified register
according to Fig. 8 or 9 10101
10001
00101
00001 Shift register 86 or: .86 '
Shift register 88 ^ or 88 '
• Shift register 90 or 90 '
- shift register 92 or 92 '

When comparing the above list and the list of Fig. 10 it can be seen that the error characteristics according to the above

Bit ahead or behind by one place. In general However, it should be noted that error bundles which.-exceed more than eight bits are not reported.

'"can cause malfunctions.

With reference to Fig. 11, it should also be noted that that an additional faulty neighbor bit can also be identified in each shift register, without adversely affecting other error characteristics. Accordingly, any eight consecutive faulty message bits or from a group of eight consecutive Message bits selected bits are corrected with HiLEe of the circuits of FIG. 8 or 9.

21 22

As was mentioned above in the comparison of the above register 146 and control bits to the shift register from the transmission channel 142 to the shift register and the list according to FIG. 10, the second and 148 are concerned. Three parity group control circuits 150, 152 fourth column of the error characteristics after the and 154 are connected to positions in the shift registers around isolation columns, which 5 146 and 148, which correspond to the parity the independent correction of two control groups, the erroneous bits in the lock following in are fixed to any of the sliding arrangements. So receive example registers according to FIGS. 8 and 9 enable. In this way, the parity group control circuit 150 input arrangement can correct eight successive error signals received from positions 1, 4 and 7 of the bits that are not being pushed. The mentioned registers 146 for the information bits and the protection bits can be omitted. That would mean positions 10 and 13 of shift register 148 for the above listing to be identical to parity control. The parity group control circles are with the last four entries in Fig. 10. 152 and 154 are connected to additional sets of five bits are shifted with respect to the bits, which are marked by means of the arrows, are omitted. The result of parity group control circuit 150 are checked,
As can be seen, all three error bundles capable of parity group convergence are trolling circles 150, 152 and 154 at position 7 in from eight bits to four bits. On the other hand, this change would have the benefit of being coupled to shift register 146. If, accordingly, the length of the output signals in the encryption 20 all three circles, which shift and decryption circuits used indicate an error with regard to parity, then register becomes shorter and that the guard distance, the bit in position 7, is reversed, if it has to be in which position 8 of the shift register 146 between successive error bundles is transferred, it turns out to be smaller. The system according to this function is operated by the AND circuit 156. 7, 8 and 9 could be modified in a similar manner, which controls the correction circuit 15, 158 by adding additional guard bits between the.

in Fig. 10 specified codes of the parity control It should also be noted that both parity specifications are inserted. Longer group control circuits 150 and 152 input signals error bundles could then be corrected, but with the purchase of position 13 of the parity control circuit, the disadvantages would decrease that longer shift registers lead and that both parity control circuits 152 and 152 are required and that between the error bundles 154 input signals from position 16 of the parity, longer guard distances are required. Derive the choice of control shift register 148. If, therefore, one or the other arrangement depends largely on the control bits in positions 13 or 16 erroneous on the type of transmission system. In the are, the parity control circles R and 5 are cases where individual errors occur very rarely and the 35 or S and T are excited. In the existing circles, errors occur very strongly bundled, but should not be provided that errors in the control of the bits of the parity control information intervals of bits are corrected. Accordingly, outputs of one or more isolation bits remain to be provided. signals of the type indicated above, which are erroneous In cases, however, where the frequency of error parity check bits indicate, ignored,
bundle is only slightly greater than the frequency of 40. The mode of operation of the circuit according to FIG. 12 is individual errors, if the isolation of the parity bits were given in table form in FIG. 13. The first may not be wanted. Row in Fig. 13 indicates the condition in which

The circuit of FIG. 12 illustrates a none of the parity group control circuits 150, 152

Error correction and detection circuit, or 154 is energized and illustrates the situation in

which of the circles discussed so far have some 45 which no errors. The next four

deviates. The circuit of Fig. 12 comprises circles, rows of the table of Fig. 13 represent others

for correcting short error bundles and for determining parity group control signal combinations, in

long error bundle. In addition, those which do not require any action. the

Control bits transmitted through noisy channels rows 2 and 4 form signals which either have a

are transmitted, by means of a parity control circuit 50 faulty individual information section or a

formed, which the parity of a group of bits incorrect individual parity check at a point in

checks the at least one additional control bit to the decryption shift register 146 or 148

contains. In the following explanation of FIG. 12, illustrate. If all three parity control circles 150,

these points should be dealt with in more detail. 152 and 154 are excited, as in the sixth

The encryption circuit 55 shown in FIG. 12 row of the table of FIG. 13 is specified so

contains a first shift register 134 in which only the bit in position 7 is corrected when it is used

Information bits are included, and another position 8 is transmitted. This process continues

Shift register 136 which contains only parity bits. has been dealt with above.

In the case of other combinations of output, the register 134 for the information bits contains thirteen positions. The shift register 136 for the 60 signals of the parity group control circuits R, S and T control bits contains only four positions, which are designated with 10 (or 150, 152 and 154), one to 13, if desired. The parity control circuit 138 provide an alarm circuit which indicates that the received input signals from positions 1, 4 and 7 errors are not within the scope of the correction possibilities of the shift register 134 as well as from position 13 of the deciphering circuit. The two parid shift registers 136. The information and status group control sequences, which are set in the two control bits by means of the circuit 140 in the last rows of the table according to FIG. 13 are a noisy transmission channel, are used to display errors and are used 142. Circuit 144 applies bits of information to trigger an alarm circuit.

23 24

The Alann circuit 162 is in the circuit diagram of the transmission possibilities in an economic Fig. 12 indicated at the top right. The excitation circuit uses more lighter way than the system of FIG. 1 for the Alann circuit 162 consists of the OR to 3.

Element 164 and the two AND elements 166 and The control pattern diagram according to FIGS

168. The input to AND gate 166 becomes the starting point for the system from FIG. In this diagram a combination of R ', S and T is formed, which are the gram unambiguous pattern, which corresponds to errors in the parity group sequence 010, which are represented in the last digits A, B and C, appear in the mutual line of FIG. The excitation circuits for a staggered arrangement are defined. These patterns, the AND element 168 contain the conductors R, S ' and T, determine the connections between the sliding gate of the parity group sequence 101 in the penultimate 10 registers and the parity control circles in the series of F ig. 13 corresponds. Encryption and decryption arrangement.

In the described circuit according to FIG. 12, the characterization of an erroneous bit A has been systematically ascertained that no error 101, an erroneous bit B 110 and those clusters with a length of thirteen bit intervals of an erroneous bit C, ie a test bit error , 100. or less remain undetected or undefected. It is to be noted that the use of a circle required by means of an identification code of three bits as shown in FIG. changes. This follows from the fact that code groups, which are also all error bundles, which are formed only by numbers and are intended to indicate that six consecutive erroneous bits in the 20 is no error, are not available, as well as from the transmitted message (or selected ones of the impossibility, distinguish between the two error bits within a group of six display code groups 01 and 10, following message bits) completely corrected; which both consist of two bits. Since now some error bundles, which exist more than the need to have code groups three to six bits long, are corrected. Using the physical 25 bits for error identification is the reason for the ability of the circle according to FIG. 12 to avoid the code group 111, since it results in error bundles of six bits or less in the system requiring a somewhat greater circuit outlay from the. The following would be considered groups that only contain one or two ones from FIg, 14.-.

The diagram of Fig. 14 provides a series of 30 The above-discussed grouping of Prtif data and control bits represent which along an affected with signs of FIG. 15, A is in a coding and noise transmission channel 142 exceeds decoding apparatus with parallel Shift registers should be tolerated. In Fig. 14, each of the data is reversible. The decryption arrangement can also be designated bits with the capital letter D and in the form of a single long shift register from each of the control bits can be carried out with the letter C. Die 35. In this case, the control pattern line 170 is a group of five arrows in the form shown in FIG. 15, B. It can be seen that arranges the spacing of three pieces of information - that the pattern shown in Fig. 15, B indicates only one and two control bits, which are in a single repetition. of the consecutive columns parity control group are included. When viewing Fig. 15, A illustrates when they are in line with the data bit 172, which is written in the form by the 40th. In the case of Fig. 15, A illustrate line 170 and the associated arrows and B make it contain the three clear parity control groups discussed above, it shows digits consisting of error correction codes that require this bit also in the two additional ones that the error detection pattern three times parity control groups is included, which is repeated by. One embodiment of the decipher lines 174 and 176 and the associated arrows 45 pattern of Fig. 15, B is illustrated in the decipherments. From the diagram according to the arrangement according to FIG. 16 and FIG. 14 it can be seen that errors in the control bits will be explained in more detail below. The pattern in the data bits and is between those bits through to Fig. 15, C are formed directly from that of which the parity check groups derived FIGS. 15 B, through omission of correction of information bits, such. B. the one with 50 of the control section information. Accordingly, 172 corresponds to designated bits which, in all three parity groups, do not impair the pattern according to FIG. 15, C that of the desired control groups. th inputs for the parity circle in the coding device. With regard to the fact that successive bits, according to Fig. 16, the input information to the

which are contained in a parity control group, shift register 200 applied via line 202, a distance of at least five bits from one another 55 The circle 204 forming the parity bit is attached to the which are not in the parity check group ent. Stages of the shift register 200 in this way stopped, it is clear that error clusters of six closed, as shown in the diagram of FIG. 15, C Bits or less with hooves of the circle according to-.Fig. 12 is illustrated. One control bit is always corrected can be. . . ^ see two data bits ^ 4 and ß inserted and on

Another embodiment of the invention is to apply 60 the data line 206. The resulting signals appearing on the data line 206 in connection with FIG. 15 (A, B, C) have been explained through 18 of the drawing. This from the parity relationship, which differs in the diagram of the management form from the above-treated Fig. 15, B is indicated.

16 by shifting registers used at each of the two ends 65 handles the only long shift register 208 which is will. In addition, the system according to FIG. 15 three points 210,212 and 214 is interrupted to • to enable errors to be corrected up to 18 in the case of excess bit transmission. There are a third a relatively simple circuit, -which three parity control circles 216/218 and 220 before-

seen which provide the three bits of the error correction code group mentioned above. The three parity control circuits 216, 218 and 220 are also labeled R, S and T. As can be seen, the connections from the shift register 208 to the 2? Parity control circuit 216 correspond to the pattern indicated in FIG. 15, B. Similarly, the S and T control circuits 218 and 220 have the same pattern of connections; but they will

and 4 in Fig. 17 designated intervals shifted. The control circuit of the shift register assigned to each stage of the register 200 is indicated schematically in the form of the block 234. The time signals labeled CP ₁ and CP ₁ are applied to the circuit 234 via an OR circuit 236. A signal is taken from the output of the parity circuit 204 via the AND element 238 by means of a time pulse CP ₂ which occurs in the second time interval.

by successive blocks of three bits along io. The parity bit C is shifted in the single bit register 240 of the register 208. stored and via the AND circuit 242 by means of

Incorrect bits that occur in the A position of the bit groups are corrected between positions 7 and 8 of the shift register 208. This is accomplished by means of AND circuit 222 which energizes the circuit. The AND circuit 222 has as inputs the code pattern R, S ', T and a suitable clock pulse CP 4. If the code pattern R, S', T corresponds to the original error correction code 101

emes time pulse CP ₄ ^ between data bits B and A allowed through. The buffer circuit lying between the shift register 200 and the data line 206 contains the two OR circuits 244 and 246 and the AND circuit 248. The time pulses CP ₂ and CP ₆ are connected to the AND gate 248 in order to pass data bits from the register 200 through the OR circuit 246 to the data line 206 through

corresponds to that which is required to leave an error in ao. The relative exit timing of the

the positional, then the bit is inverted at the transition from shift register position 7 to shift register position 8. Similarly, the B and C bits are corrected

Data bits A and B and control bit C on data line 206 is in the last row of FIG. 17 indicated.
The timing of the processes at the

the AND gates 224 and 226 are controlled. If the decryption device is shown in the diagram applied to these AND gates, the error of FIG. 18 is indicated. The shift register 208 to correction codes according to the table in F1 g. 15, A
correspond to the bits in the transmission

from one shift register position to the next

the decryption device is operated at a higher speed than the shift register 200 of the encryption arrangement. Accordingly, they are inverted. 30 time pulses CP ₂ , CP ₁ and CP ₆ via the OR

At the output of the last shift register stage 228 angedes circuit 250 to the shift control circuit 252 the shift register 208, the information bits are included, associated with the shift register 208th Both types have been corrected, and the check bits of all three parity control circuits have also been corrected. Under certain circumstances 216, 218 and 220 may be desired during the third time that code groups including the 35 interval are sampled. This is made evident by the ge control bits to a remote decision that the input CP _{3 is} to be transmitted to each of the ANDing devices. However, a simple element 254, 256 and 258 is provided with the outputs of the buffer circuit, in order to connect the corrected control and corresponding parity control circuits. bits to be removed if the information bits are to be evaluated immediately. These parity control signals are briefly evaluated in the. In a practically designed registers 260, 262 and managed system, either the 264 would of course be stored, which is also marked with R, S and T correction circle for the control bits or the circle. The signals not stored in the single bit registers for the removal of two control bits will be removed by means of the time pulses CP ₁ . keyed, which is connected to each of the AND circles 222, 224

The timing of the processes for switching 45 and 226 to be created.

The device according to FIG. 16 is somewhat more involved than that, as was already mentioned briefly above

corresponding processes of the above-explained three-phase output from the shift register stage circuits in which parallel shift registers are converted to a two-phase output at the 228, wel decryption device. In which rather only the bits A and B on the output line 226 circle according to FIG. 16 the time division is passed on by means of a 50. The required buffer circuits include the timing circuit 230 is controlled, which is synchronized via the line the AND gates 268, 270 and 272, namely to-232 with the incoming bit signals on the managerial additionally to the single bit 274 and the OR-processing 202nd The time circuit 230 supplies circuit 276. The output of the shift register stage 228 output signals at six evenly spaced is sampled during the time interval 3 of the AND-spaced time intervals for two at 55 member 270 and in the single bit register 274 the conductor 202 incoming bits. Saved for the purpose. As indicated in the last of the circuit of Fig. 16, it is assumed that in the series of the timing diagram of Fig. 18, the timing signals from circuit 230 become more readily available on both the receive output data bits, labeled A , and at the transmitter are. At the end of time interval 4 to output line 266, in practice a separate 60 would be transmitted at the receiver. This process will be used by means of the AND timing signal, and an appropriate one

Synchronizing device of a known type would be provided to keep the timing circuits at both ends to synchronize.

Fig. 17 shows a timing diagram for the encryption arrangement which is in the upper part
16 is illustrated. The digits are
along the shift register 200 during the 1

Gates 272 , which has an input terminal from the single bit register 274 . the
Time pulses CP ₁ are sent to the other input
of AND gate 272 applied to signals through
this AND gate 272 and the OR gate 276 for
Output line 266 to lead. The data pulses labeled B are taken directly from the
Shift register stage 228 by means of the time pulses CP ₁

809 638/1253

which are applied to control the activity of the AND gate 268. Accordingly, the data bits A and B are coupled to the output channel 266, whereas the control bits C are excluded from transmission over this line. -5

In the foregoing description, some specific embodiments of the invention have been set forth. In FIGS. 1, 8, 9 and 12, a shift register circuit was shown for the decryption arrangements which has separate shift registers for the control bits and the information bits. These registers could of course be implemented in the form of a single long shift register, with connections to the parity group control circuits suitably made in order to enable the same function as in the case of the decryption arrangement according to FIG. 16. In the same way, the decryption arrangement according to FIG. Use 16 different shift registers in the manner of the decryption arrangements according to FIGS. 1, _3, 8, 9 and 12.

In each of the circuits described, a single scheme has been adopted for the circuit connections to the equality checking circuits. In certain cases it may be desirable to reduce the additional bit transfer by using two or more separate parity group patterns in a single system. It will be understood that the continuous encryption and decryption techniques discussed above can be readily adapted to systems in which more than one parity control pattern is used. In addition, the circuits explained have been developed on the basis of the use of binary digits; It will be understood, however, that systems with a base greater than 2 can also be implemented according to the above principles. For example, control bits can be formed by "adding up the input information bits contained in the parity check in accordance with the module that forms the basis of the digit system. Thus, if 'a parity check bit is to be formed" to assign two input decimal digits check digits 7 and 9, for example, the resulting parity check digit would be 4. You get this number by adding the numbers? and 9 and subtract from that. next higher decimal number that ends with a zero. Mathematically this can be expressed as follows: "- -, ^ ₀

9 + 7 = 6 (Mod 10). (2)

. The remainder 6 is then subtracted from 10 to find the control digit; The resulting control group consists of the. Numbers 9, 7 and 4, which together are 0 ^; (Mod 10). The changes in the circuit required to implement the design in conjunction with the existing circuits are given in the preceding example. _ ■ ■ ■ _; .....--. .; ■ 60,

In Figs. 3 and 4, which show the circuit in more detail, relay circuit arrangements are implemented. Other circuit techniques can of course can also be used to realize the logic circles indicated in the drawing> For example, the highly developed binary serial computer technology is immediately applicable. By Application 'of the computer techniques can impulse frequencies up to one million impulses per Second. In such implementations, delay lines became the shift registers form, the logical functions could be taken over by diodes and the necessary potentials can be supplied by electronic pulse generators.

Claims (5)

Patent claims: 1. Error detection and correction device for digital messages that have a Noisy channel giving rise to error bundles are to be transmitted, the the message in redundant form, d. H. in the form of information and check bits to the channel delivering encoder has a multi-stage shift register, which is connected to the output stage the channel is coupled and at the input stage with the information bits to be coded is applied, and wherein a decoder is provided which the redundant message from Channel decreases again, characterized in that the check bits in the encoder according to a predetermined parity rule generating circuit (26) with at least two non-adjacent positions of the shift register (24) is connected, so a check bit the Represents parity relationship of the information bits stored in these positions and each Information bit is included in the formation of at least two check bits, as well as switch (28) in the encoder are provided that each check bit in "the to insert the transmitted message train at a point that is not adjacent to the one Information bits is located from which this check bit has been determined, and that im Decoder shift registers (34, 36) and parity check circuits (38, 40) are provided, which continuously in each case the two non-adjacent information bits and compare the corresponding check bit of a parity group and the correctness determine an information bit common to two parity groups, as well as correction circles (42,44) are provided in the decoder, which respond to signals from the parity check circuits (38, 40) in the event of non-agreement of the information bit determined to be correct with the actual information bit correct the corresponding information bit. - 2. Device according to claim 1, characterized denotes signed, that the decoder has a first Paritätsprüfkreis (ig positions 1, 4, 7 in Fig. 1) (38, R in FIG. 1) for checking the parity of the first parity group corresponding to a first parity group education of the encoder, a second parity check circuit (40, S in FIG. 1) for checking the parity of a second parity group (positions 4, 7, Ϊ0 in FIG. (38 and 40) to the position (4) common to the two parity groups and each parity check circuit are also connected to the positions of the other bits of its parity group, and finally correction circuits (42, 44) connected to the output of the two parity check circuits for correcting incorrectly received Has bits. 3. Device according to claim 2, characterized in that the first parity check circuit (38) Entrances of at least three at a distance, e.g. B. of two bit positions, mutually lying shift register positions has, including inputs of at least one check bit position and one information bit position, and that the second parity check circuit (40) also inputs from at least three at a distance, e.g. B. of two bit positions, from each other has shift register positions lying, including at least one input of a bit position (e.g. 4 in Fig. 1) which is also connected to the first parity check circuit (38). 4. Device according to one of claims 1 to 3, characterized in that the encoder a control circuit for shifting the information by one bit position by the shift register and to repeat the parity check operation. 5. Device according to one of claims 1 to 4, characterized in that the shift register circuit a circuit for summing the bit information in at least two bit positions the shift register circuit and for determining corresponding check bits. Considered publications: U.S. Patent No. 2,653,996; USA. Reissue 23,601; Go ο de and Machol, "System Engineering", Mc Graw-Hill Book Company, 1957, pp. 150 to 155, 255, 297; Bell System Technical Journal, 29 (1950), p. 147. In addition 3 sheets of drawings 809 638/1253 11.68 ® Bundesdruckerei Berlin