DE1273583B - Magnetic core storage matrix - Google Patents

Description

FEDERAL REPUBLIC OF GERMANY

GERMAN

PATENT OFFICE

EDITORIAL

Int. Cl .:

GlIc

German class: 21 al-37/60

Number: Case number:
Filing date '
Display day:

P 12 73 583.0-53 (S 67452)

March 7, 1960

July 25, 1968

It is known to build memories from a large number of individual magnetic cores with a hysteresis loop that is as approximately rectangular as possible in the manner of a matrix. The individual memory elements are controlled via a column line and a row line of the matrix, the lines being guided through the ring-shaped cores in such a way that the lines cross each other in the core. In order to control a core, a current is passed over each line, which is not sufficient in itself to bring the core from one remanence position to the other, but which, together with the current over the other line, safely remagnetizes the core. A binary "0" is now stored in that the core is kept in its remanence position, ie a current pulse is sent at most over one of the lines. A binary "1", on the other hand, is stored in that the core is remagnetized, so that when the core is queried by the current pulse that occurs during reverse magnetization, the presence of the "1" is displayed again. In this case, a current pulse is passed over both lines, which then cause the desired magnetization reversal. To query the storage status of a core, a pulse of opposite polarity must then be given over each line so that the core, if it has been remagnetized for the storage of a "1", can be returned to its initial state. If, on the other hand, a "0" was stored in the corresponding cores , no pulse is induced except for a slight interference pulse in the output line through the activation with pulses of opposite polarity.

From these considerations it already follows that for storing information (writing) and for storing the same information (reading) pulses of different polarity over a and the same line must be provided. For the operation of known magnetic core matrix arrangements therefore pulse generators are required that emit bipolar pulses. Besides that such pulse generators, especially if they have positive and negative pulses of exactly the same size are relatively expensive, the supply of bipolar pulses interferes with switching the inputs of the individual matrix lines, since the switches are generally transistors, i.e. semiconductors, be used. Although a circuit arrangement is already known in which transistors for Switching of bipolar pulses can be used. Due to the very different tax conditions at Magnetic core storage matrix

Applicant:

Siemens Aktiengesellschaft, Berlin and Munich, 8000 Munich 2, Wittelsbacherplatz 2

Named as inventor:

Dipl.-Ing. Edgar Heimbach, 8000 Munich

the two polarities of the pulses, however, it is practically impossible to have approximately the same rise and To achieve fall times of the bipolar pulses. In addition, for the operation of such a

ao bipolar switching transistor depending on the direction of the current different tax potentials are provided. To avoid these disadvantages it already is became known to chain separate control lines with the cores for writing and reading. This in itself alleviates the difficulty of loading the switches, but will this increases the effort that has to be made in the manufacture of the individual dies. In addition, extremely small toroidal cores can be used in such arrangements, which also in terms of Power consumption are particularly favorable, no longer use, as in every dimension of the matrix a total of at least two wires, namely one wire for the control for writing and one for the Control for reading must be provided. In addition, there is an interrogation wire with each core and, if necessary, to chain a blocking winding in the case of multi-dimensional memories.

Furthermore, a circuit arrangement is also known in which the individual matrix lines are indirectly connected via Transformer with a subdivided primary winding and a secondary winding can be controlled. True is It is thus possible to have only one control wire in each row or column of the actual memory matrix to provide and to use unipolar switches, but this circuit arrangement is only in principle a modification of the aforementioned, which can be seen when the subdivided primary windings be viewed as consumers. In addition, the type of circuitry brings that at Introduction of such transformers is required, with certain difficulties. Apart from this,

809 587/393

there is only one line of the groups combined on the other side. This will a control of a line unambiguously.

If the information stored in the core K 22 is to be read, then the transistors T 9 and T 4 for the X lines and the transistors TIl and T 5 are switched on , and the pulse sources Xι and Yι give the drive pulse, the

that one half of the primary winding is idle, assigned to T 4. In the drawing there are also four, which can easily lead to an undesirable transient pulse sources X _s , Y _s , X _L , Y _L , via which the transformer can hold, depending on the operation (S - writing and L = reading ) Galvanic connection of the two winding halves at the desired times a pulse to which the pulse 5 induced in the idling winding is output via the transistors prepared matrix lines to the voltage applied to the blocked switch. If, for example, the core K22 should be increased. The consequence of this is that the switches are activated in the write direction, then the dielectric strength must first be significantly higher via the transistor Γ 2 and the transistor than the operating voltage used. Particularly when using Transio the pulse generator X _s interfere with a corresponding pulse as a switch, this increases the costs and is wasted. Activation via the Y-line may reduce operational safety under certain circumstances. follows via the transistors Γ16 and T14. The invention relates to a magnetic core - each transistor has two lines pre-storage matrix, in which these disadvantages are avoided, with the transistors at the beginning and the end. Also with the matrix according to the invention 15 at the end of each line the lines are grouped in such a way that the individual rows and columns are combined in pulses (in pairs) that in each group moderately for both storing (writing) and
also controlled for storage (reading) according to a coincidence current principle.

The invention is based on the object of providing a 20
To create memory that has one and the same drive wire in one dimension of the matrix using unipolar selection switches with unipolar
Pulses can be controlled. This is achieved according to the invention in that a selected »5 thus flows in the desired direction. Control wire when writing to one of them The synchronism between the individual im-

At the end of a unipolar switch with the pulse generator, the clock element T becomes forced and at the other end via a gene. As such, the impulses could be directly from further unipolar switch with a fixed potential - this clock element would have to be delivered tial or with a unipolar pulse source and at 30 this a power can be applied that of Reading at the other end is usually no longer derived via a common unipolar transistor can be. For this reason, the individual pulse generators are separated.

The transistors T1 to T16, which enable each individual matrix line to be driven in one direction or the other, are controlled in a manner known per se via the address register. The connection between the address register AR and the base connections of the individual transistors is off

pulses are applied, although this is not always the case for all transistors, contrary to reasons of clarity set end is preferably drawn above ground to the other.

Terminal of the pulse source is connected. I _n the F i g. 1 are only the switching elements

The principle of operation of a magnetic core reproduced for the basic understanding Memory matrix according to the invention will be of importance on the basis of the invention. At the Praktiin the F i g. 1 of the drawing shown embodiment 45 see embodiment of such a matrix arrangement example explained below. various additional measures are taken

The matrix M is equipped with four row lines Z1 to fen, but these are equipped for the peculiarity of driving a Z 4 and four column lines Sp 1 to Sp 4. Matrix with unipolar pulses for writing. In practical embodiments, self-reading and reading do not matter. In particular a memory matrix of a very much larger size, it is then conceivable to use the embodiment according to a larger number of lines, e.g. B. 20 x 50. Each one-F i g. 1 to migrate or to supplement so that the individual line should be linked to the magnetic cores individual transistors, which in the further Ausfühsein that are provided for storing information in the form of a passive switch, as a positive X-direction, so from left to right, and to use active switches in such a way that a voltage source is to flow indirectly on one side to the line in a negative pulse in the positive Y-direction, i.e. from bottom to top. To read the lines connect which then the current flow over the stored information must accordingly cause the line accordingly. In this case, negative pulses must also be provided in more negative sen but power transistors, direction, i.e. for the X line from right to the links necessary for a memory matrix and for the F line from top to bottom 60 relatively large currents switch able to flow. To this opposite operation are on the.

For design reasons, it turns out to be in

Line on both sides with two oppositely directed, many cases advantageous, the individual control diodes equipped, these diodes always paired lines are combined indirectly via an interposed way and to control a transistor transformer. In this case, switches will be assigned. For example, the unipolar pulses are driven by the primary windings of the diodes Dl and D 5 of the transistor switch Tl transformer, in one direction or and the diodes D 2 and D 4 of the transistor switch in the other direction, and the secondary windings spei-

Switch with the reference potential and on one
End with another unipolar switch
a fixed potential or with a unipolar
Pulse source is connected.

In the magnetic core memory matrix according to the invention, the control lines are optionally, depending
according to whether it should be written or read,
from one side or the other with unipolar im-

sen then the correspondingly assigned control lines of a memory matrix.

Regardless of whether transformers are provided or whether the control lines are controlled directly it has also proven to be advantageous to have all of the cables in one To hold rest potential, which is equal to the potential of the control pulses. This is just for one Matrix arrangement according to the present invention is important because the multitude of necessary Diodes enables capacitive coupling to all control lines, which leads to the fact that with With each drive pulse, the entire matrix lines are temporarily raised in terms of DC voltage Need to become. If, on the other hand, the lines are all at one potential via high-value resistors held, which corresponds to the potential of the impulses, then this potential shift does not apply the control pulses are loaded and on the other hand interference pulses in the output line (reading wire) for Consequence.

In the embodiment according to FIG. 1 can result in a direct current increase in the lines take place that, as shown for the line Zl, this via a high resistance Line is connected to a correspondingly negative potential. If this line is then to be controlled, then it is connected to ground via the transistor T 7, and the line thus shares the ground potential with. Since the transistor Γ 7 is turned on before the activation pulses are used (it is a passive switch), a slight residual current flows until the activation pulse occurs. However, this residual current does not disturb the organization of the matrix and becomes completely ineffective made when a transformer is connected upstream of the control lines, as mentioned above.

FIG. 2 shows a circuit design in which the matrix lines, specifically both the X and Y lines, are controlled via transformers. The transformers Ül to Ü4 are provided for controlling the X lines and the four transformers Ü5 to Ü8 for controlling the y lines. Each primary winding of a transformer should be traversed by a negative pulse in one direction as well as in the other if a pulse of a corresponding size for writing or reading is to flow via the associated control lines of the memory matrix.

The control takes place depending on the four pulse sources X _s , Y _s , X _L , Y _L in the same way as in FIG. 1. In addition, the transistors Tl to T 16 are provided in the circuit as shown in FIG Individual pulse sources emitted pulses to the associated transformers via the diodes D 1 to D 32 as shown in FIG. 1 feed. For reasons of control, the transistors are grouped together so that, depending on whether information is to be written or read, one of two transistors is prepared so that the address register AR determines the core in each case, without having to pay attention to whether this is Core a write process or a read process must be carried out.

This switchover is carried out by the L or S switch. The address register itself is shown to the right of it in the figure, the associated outputs of the register and the corresponding transistor switches being provided with the corresponding reference numerals.

In the arrangement shown, the pulses are generated in that a current is constantly drawn from the current source which corresponds to the pulse current for a control process. This current is first diverted via the transistors Ta and Tb. If a corresponding transformer is now to be controlled, the path is opened via the associated transistors (see FIG. 1). Since this path contains an inductance, the current coming from the voltage source initially flows through the transistors Ta and Tb, which are evenly loaded with the aid of the diodes D α and D b. As soon as the pulse is to begin, the transistors Ta and Tb are blocked at the same time, so that the current must now flow through the secondary winding of the switched-through transformer. The current will continue to flow in full, as the upstream connection of the throttle Dr forces a corresponding current constancy. The current therefore begins in the primary winding of the corresponding transformer with a very steep pulse edge. The transistors within the X or Y matrix take over the pulse switch-off, since the inductance to be represented by the primary winding of the transformer temporarily maintains a current flow even when the transistors Ta and Tb are made conductive again.

The memory matrix according to the exemplary embodiment is thus provided with partly active, partly passive switches controlled, whereby in each case only the current is switched off.

The invention has been explained using two exemplary embodiments. Like these exemplary embodiments show, the invention can be implemented in a wide variety of ways. Within the scope of the invention it is then also easily possible to combine the individual embodiments with one another.

A special application arises when building a spatial matrix in which a third Winding (inhibit winding) can be controlled accordingly.

The execution of the individual switching elements, which in the exemplary embodiments are only shown in block form are reproduced is within the skill of the art and can be done in various ways take place.

Claims (10)

Patent claims: 1. Magnetic core memory matrix, in which the individual rows and columns each have a Pulse control wire for both storing (writing) and storing out (Read) can be controlled via unipolar switches after a coincidence operation, characterized in that a selected Control wire when writing at one end via a unipolar switch with the reference potential and at the other end via another unipolar switch a fixed potential or with a unipolar pulse source and when reading at the other End via a unipolar switch with the reference potential and at one end via another unipolar switch with a fixed potential or connected to a unipolar pulse source. 2. Memory matrix according to claim 1, characterized in that the control wires in groups so combined at both ends via decoupling members S to form a unipolar switch are that of each group at one end only one lead in the group at the other end is available. 3. Memory matrix according to claim 1 and 2, characterized in that the switch is transistors are provided. 4. Memory matrix according to claim 3, characterized in that the transistors are passive Switch operated. 5. Memory matrix according to claim 3 or 4, characterized in that for each control direction for both the line and the. Column lines provided their own pulse generator is. 6. Memory matrix according to one of claims 1 to 5, characterized in that the line and column lines are controlled indirectly via an interposed transformer. 7. Memory matrix according to one of claims 1 to 6, characterized in that all Storage lines, possibly even the primary windings of the transformer, on a potential p. be kept tial, which at least approximately corresponds to the potential of the control pulses. 8. Memory matrix according to claim 7, characterized in that the control lines or the primary windings of the transformer within the decoupling directional conductor fields at the ends of the lines are connected to a DC voltage source via decoupling resistors. 9. Memory matrix according to one of claims 1 to 8, characterized in that the control pulses can be generated by interrupting a corresponding current-carrying secondary path. 10. Memory matrix according to claim 9, characterized in that only the use of the Control pulses on the control lines are determined by interrupting the secondary routes, during the end by opening the in the control lines to select a specific Line arranged switch is forced. Considered publications:
German Auslegeschrift No. 1 027 723;
British Patent Nos. 762 057, 807 700;
French Patent No. 1141398;
Italian Patent No. 575 044;
"Die Naturwissenschaften", 1953, no. 2, p. 49/50;
"Electronics Engineering Issue", 10.10.1958,
to 103. 1 sheet of drawings 809 587/393 7.63 © Bundesdruckerei Berlin