DE10346229A1 - A device for generating a clock signal and for decoding data, for use in a contactless integrated circuit card (CICC) - Google Patents

Abstract

The invention relates to a device for generating a clock signal and for decoding data for a contactless integrated circuit component, and to a data recovery device for a contactless integrated circuit card. According to the invention, a receiver (110) for receiving a high-frequency signal with a pause period, a divider (120) for dividing the received high-frequency signal or a received clock signal, a first counter (140) for counting a period of the divided signal during each non-pause period of the high-frequency signal, a second counter (150) for counting a period of the divided signal and a decoder (160) for generating a synchronous clock signal and a decoded data signal in response to the output signals of the first and second counters. DOLLAR A Use in IC card technology.

Description

The invention relates to a Device for generating a clock signal and decoding data for a Contactless integrated circuit component and on a data recovery device for a contactless integrated circuit card.

Since the advent of credit cards in the 1920s there were a majority developed by electronic information cards, such as payment cards, Credit cards, identification cards, department store customer cards etc. Younger Time are so-called integrated circuit cards (IC cards), at which a mini computer is integrated in the card, because of their Comfort and their robustness for numerous applications popular become.

In general, IC cards are like this designed that a thin Semiconductor component is attached to a plastic card, which the size of one Owns credit card. Compared to a conventional credit card, the one Containing strips of magnetic material, IC cards have some Advantages such as high stability, read-only data and high security. For this reason, IC cards have a high one Acceptance as the next generation of multimedia information media receive.

IC cards can roughly fall into the types of contact IC cards, contactless IC cards (CICC) and remote communication cards (RCCC) can be classified. For the ISO and IEC standards have a special system for the CICC type for worldwide Standardization formed. Specifically, the international specifies Standard ISO / IEC 14443 the physical properties of proximity cards, Interface for High frequency power and signal, initialization and anti-collision as well as transmission protocol. Under ISO / IEC 14443, contactless IC cards contain an integrated circuit (IC) that performs data processing and / or storage functions. The possibility The technology of contactless cards is a result of that Signal exchange via inductive coupling with a proximity coupling unit, such as one Card reader, can be realized and the card performance without Using galvanic elements, i.e. without an ohmic path from an external interface structure to the integrated circuit inside the card. A card reader creates an energy-producing high-frequency field that is coupled to the card, to transfer power and that for Communication purposes is modulated. The frequency of this RF operating field is typically 13.56MHz ± 7kHz.

The 1A and 1B illustrate concepts of communication signals of interfaces of type A and type B according to ISO / IEC 14443. In 1A a communication signal is transmitted from a card reader to a contactless IC card, in 1B a communication signal is transmitted from the contactless IC card to the card reader. The protocol according to ISO / IEC 14443 describes two communication signal interfaces of type A and B. Under communication signal interface type A, the ASK modulation principle is used for communication from the card reader to the contactless IC card to 100% of the HF operating field and a modified Miller coding principle , The bit rate for the transmission from the card reader to the contactless IC card is fc / 128, ie 106 kbps (kbit / s), where fc denotes the frequency of the HF operating field. The transfer from the contactless IC card to the card reader is encoded using the Manchester coding principle and then modulated using the on-off key (OOK) principle. For example, cards currently managed by the Type A communication signal interface and used, for example, in subways and buses in Seoul, Korea, generate a time control with a constant time interval using an ASK-modulated signal received by a card reader, and they receive and send one bit of data at a time.

When data is transferred from an IC card to a card reader, power is stably provided for the IC card by the card reader. On the other hand, when data is transferred from the card reader to the IC card, a pause period t2 is generated, as in FIG 2 shown. During this pause time t2, the power transmission from the IC card to the card reader is interrupted. As a result, a clock signal with a discontinuous course is generated in an RF receiver. Under these conditions, it is difficult to maintain the specified bit rate of 106 kbps for the Type A protocol according to ISO / IEC 14443, since a synchronous clock signal for transmission and reception is generated by dividing such a clock signal with a discontinuous period.

The 3A and 3B show frames of type A data from ISO / IEC 14443. Specifically illustrated 3A a short frame, which is used to trigger a communication process, and a communication start signal S, seven data bits b1 to b7, which are transmitted in a sequence with the LSB as the first bit, and a communication end signal E is constructed in this order. 3B illustrates standard frames that are used for data exchange and are composed of a communication start signal S, eight data bits b1 to b8 and a bit P for odd parity, and a communication end signal E. The LSB of each byte is transmitted first. Each byte is followed by bit P for odd parity, which is set so that the number 1s is odd (b1 to b8 and P).

A conventional decoding circuit in a contactless IC card extracts respective bits from an RF signal that is received in synchronism with a synchronous clock signal, separates the extracted bits into the start bit S, the data bits b1 to b7 and the end bit E and detects the received data from the separated bit information. For this purpose, a synchronous clock signal without discontinuous periods, ie without a pause time, is required in order to enable the decoder circuit to operate properly.

There is therefore a need for generating a synchronous clock signal of constant frequency from a high-frequency signal with a discontinuous or pause period t2 according to 2 for use in contactless IC card technology.

The invention lies as a technical Problem of providing a clock signal generation and data decoding device, which is capable of a synchronous clock signal with constant frequency without delivering a pause period from a received RF signal, and a data recovery device that is capable of Data from a received RF signal in contactless applications to restore integrated circuit cards precisely.

The invention solves this problem by Provision of a clock signal generation and data decoding device with the features of claim 1 and a data recovery device with the features of claim 6.

Advantageous further developments of Invention are in the subclaims specified.

Advantageous embodiments of the invention are shown in the drawings and are described below. Here show:

1A and 1B Diagrams of communication signals for interfaces of type A and type B under the protocol according to ISO / IEC 14443,

2 1 shows a signal waveform diagram for a signal transmitted from a card reader to an integrated circuit card,

3A and 3B Diagrams of data frames for the type A protocol according to ISO / IEC 14443,

4 2 shows a block diagram of a circuit for clock generation and data recovery of a contactless integrated circuit card according to the invention,

5 a timing diagram of the operation of various signals of the circuit of 4 .

6 an advantageous realization of a clock divider from 4 .

7 1 shows a block diagram of a further circuit for clock generation and data restoration of a contactless integrated circuit card according to the invention, the circuit being capable of restoring exact codes even in the event of large fluctuations in duration during a pause period,

8th a timing diagram of the operation of various signals of the circuit of 7 ,

4 shows a block diagram of a clock signal generation and data recovery circuit 100 which is built into a contactless IC card and an RF block 110 , a clock divider 120 , an OR gate 130 , a three-bit counter 140 , a two-bit counter 150 , a clock generator and decoder block 160 and a reset control unit 170 includes.

The RF block 110 receives an RF signal, for example with a frequency of 13.56MHz and a bit rate of 106kbps based on a type A protocol according to ISO / IEC 14443, and converts the received signal into a clock signal RF_CLK and a data signal RF_IN, as for a digital circuit are suitable. The clock divider 120 divides the clock signal RF_CLK of the block 110 and thereby generates a divided clock signal DIV_CLK. As will be explained below, the clock divider generates 120 Clock signals with different frequencies and outputs one of the clock signals in response to a selection signal SEL. The OR gate 130 receives a system reset signal SYS_RST and the data signal RF_IN from the block 110 ,

How out 4 The three-bit counter is also shown 140 by an output signal of the OR gate 130 resets and counts the period of the clock divider 120 supplied, divided clock signal DIV_CLK. The output signal RX_IN_CNT3 of the three-bit counter 140 varies sequentially from "0" to "7", ie in binary form from "000" to "111". The two-bit counter 150 is by a from the reset control unit 170 generated reset signal RST resets and counts the period of the divided clock signal DIV_CLK from the clock divider 120 , The output signal STATE_CNT2 of the two-bit counter 150 varies sequentially from "0" to "2", ie in binary form from "00" to "10".

The clock generator and decoder block 160 works in response to the output signals RX_IN_CNT3 and STATE_CNT2 of the counter 140 and 150 and generates a synchronous clock signal ETU_RX_CLK, a decoded data signal RX_IN and a frame end signal END_OF_RX. The reset control unit 170 is reset by the system reset signal SYS_RST and generates the reset signal RST in response to the synchronous clock signal ETU_RX_CLK.

5 illustrates the response and operation of various signals of the circuit of FIG 4 in the event that a short framework is used to trigger a communication process. The operation of the clock generation and data recovery circuit will now be described with reference to FIG 4 and 5 explained in more detail.

Like from the 4 and 5 to recognize the three-bit counter 140 and the reset control unit 170 reset by the system reset signal SXS_RST before a short frame is received by a card reader, not shown. The two-bit counter 150 is replaced by the reset signal RST Reset control unit 170 reset. After the reset process, the values of the output signals RX_IN_CNT3 and STATE_CNT2 of the two counters lie 140 and 150 to "0". As in 5 shown, the RF block gives 110 the RF_IN data signal goes high before the short frame is received.

When the start bit S is received as the first bit of the short frame, the data signal RF_IN of the RF block goes 110 from a high level (logic 1 level) to a low level (logic 0 level). The clock divider 120 This begins with the division of the clock signal RF_CLK. Assuming that a period of each bit corresponds to a short frame 3A represents an elementary time unit (ETU), has the divided clock signal DIF_CLK, that of the clock divider 120 a period of ETU / 4.

After resetting, the counters are leading 140 and 150 a counting process in response to the falling edge of the divided clock signal DIV_CLK. The clock generator and decoder block 160 generates rising and falling edges of the synchronous clock signal ETU_RX_CLK when the output signals RX_IN_CNT3 and STATE CNT of the counter 140 and 150 have special values.

Table 1

The table above shows the conditions under which the synchronous clock signal ETU_RX_CLK in response to the output signals RX_IN_CNT2 and STATE_CNT3 of the counter 140 and 150 is produced.

If, for example, the output signal RX_IN_CNT3 of the three-bit counter 140 to "1" and the output signal STATE_CNT2 of the two-bit counter 150 is at "1", this results in a rising edge of the synchronous clock signal ETU_RX_CLK. If the output signal RX_IN-CNT3 of the three-bit counter 140 to "2" and the output signal STATE_CNT2 of the two-bit counter 150 is at "2", this causes a falling edge of the synchronous clock signal ETU_RX_CLK.

The reset control unit 170 of 4 activates the reset signal RST in response to a falling edge of the synchronous clock signal ETU_TX_CLK from the clock generator and decoder block 160 , The two-bit counter 150 is reset by activating the reset signal RST. The three-bit counter 140 is reset when the RF_IN data signal of the RF block 110 from high to low level. By repeating the above processes, the synchronous clock signal ETU_RX_CLK is generated with a frequency of 0.11 MHz in this example. The clock generator and decoder block generates 160 the decoded data signal RX_IN in response to the output signals RX_IN_CNT3 and STATE_CNT2 of the count ler 140 and 150 ,

The table below shows the conditions under which the decoded data signal RX_IN in response to the output signals RX_IN_CNT3 and STATE_DNT2 of the counter 140 and 150 is produced.

Table 2

The data signal RF_IN is a modified Miller code and displays a logic "0" during an ETU if its value is "0111" or "1111" and a logic "1" if its value is "1101". If, for example the output signal RX_IN_CNT3 of the counter 140 equal to "0" and the output signal STATE_CNT2 of the counter 150 is "2", the block returns 160 the decoded data signal RX_IN at a high level. If the output signal RX_IN_CNT3 of the counter 140 equal to "4" and the output signal STATE_CNT2 of the counter 150 is "0", the block returns 160 the decoded data signal RX-IN from low level. Accordingly, a received data signal RF_IN "1111011101111101" is converted into a decoded data signal RX_IN "0001".

The procedure for recognizing the end bit E, which indicates the end of a frame, is as follows. The block 160 generates the frame end signal END_OF_RX in response to the output signals RX_IN_CNT3 and STATE_CNT2 of the counter 140 and 150 , The table below shows the conditions under which the frame end signal END_OF_RX in response to the values of the output signals RX_IN_CNT3 and STATE_CNT2 of the counter 140 and 150 is produced.

Table 3

As can be seen from Table 3, the clock generator and decoder block is activated 160 the frame end signal END_OF_RX at a high level when the value of the output signal RX_IN_CNT3 of the three-bit counter 140 is equal to six or seven and the value of the output signal STATE_CNT2 of the two-bit counter 150 is zero.

That way it allows the invention, data according to the protocol of type A according to ISO / IEC 14443 by generating the synchronous Clock signal ETU_RX_CLK with a frequency of e.g. 0.11MHz and the to receive decoded data signal RX-IN.

Although a bit rate of 106 kbps is used in the exemplary embodiment described, it is understood that the invention can also be used for other bit rates. 6 illustrates an exemplary implementation for the clock divider 120 of 4 , How out 6 apparent, the clock divider includes 120 in this case a plurality of divider units 121 to 127 and a bit rate selector 128 , The divider units 121 to 127 are in series between an input connector 120a and an output connector 120b looped. Every plate unit 121 to 127 divides the frequency of a received signal by a factor of two. The bit rate selector 128 selects one of the divided clock signals ETUD2 to ETUD64 of the divider units 121 to 127 as output signal DIV CLK.

According to the ISO / IEC 14443 standard, the clock signal RF_CLK has a frequency of 13.56MHz. In order to support a bit rate of 106 kbps, the clock signal ETUD4 of the divider unit 125 used as the clock signal DIV CLK, the two-bit counter 140 and the three-bit counter 150 as well as the clock generator and decoder block 160 is fed. To support a bit rate of 212kbps, the two-bit counter 140 and the three-bit counter 150 as well as the clock generator and decoder block 160 the clock signal ETUD8 of the divider unit as the clock signal DIV_CLK 124 fed. Thus, the clock generator and data recovery circuit according to the invention is capable of supporting a bit rate of up to 3.2Mbps.

As previously explained, the duration of the pause period of an RF signal transmitted from a card reader to an IC card varies as the IC card approaches the card reader or a connector thereof. The pause period varies depending on the distance between the card reader and the IC card, on the impedance matching of an antenna and / or on the strength of the RF signal. In the 4 The clock generation and data recovery circuit of the contactless IC card shown only works in a normal state if the duration of the pause period is set to a specific value in the range between a minimum value Min and a maximum value Max, as shown in 2 are specified. If the duration of the pause period varies in the range between Min and Max, it may be that the circuit 100 no exact codes restored. Because the counter 150 works with a two-bit count, which limits the resolution to 25% of a unit period.

7 illustrates in a block diagram the functional structure of a further clock generation and code recovery circuit 200 for a contactless IC card. The circuit 200 of 7 largely corresponds to the circuit 100 of 4 , where instead of the two counters there 140 . 150 a counter operating with four-bit count 240 and a three-bit count counter 250 are provided. The latter experiences a signal reset by a clock generation and decoding block 260 which, moreover, the block 160 of 4 equivalent.

The four-bit counter 240 works in sync with rising and falling edges of a clock divider 220 according to the clock divider 120 of 4 shared clock signal DIV_CLK when one of an RF block 210 according to the RF block 110 of 4 supplied data signal RF_IN is at a high level, and generates an associated output signal RX_IN_CNT4. The four-bit counter 240 is reset when the data signal RF_IN is at a low level. The output signal RX_IN_CNT4 of the four-bit counter 240 changes successively from "0000" to "1111", ie from the value "0" to the value "15". The three-bit counter 250 is in response to one of the clock generation and decoding circuitry 260 Deletion signal supplied CLEAR resets and works synchronously with rising and falling edges of the clock divider 220 divided clock signal DIV_CLK and generates a corresponding output signal STATE_CNT3. The output signal STATE_CNT3 of the three-bit counter 250 changes sequentially from "000" to "111", ie from the value "0" to the value "7".

The clock generation and decoding circuit block 260 generates a synchronous clock signal ETU_RX_CLK in response to the output signals RX_IN_CNT4 and STATE_CNT3 and generates the decoded data signal RX_IN, a frame completion signal END_OF_RX and the delete signal CLEAR.

8th illustrates the timed operation of the circuit 200 when it receives a short frame signal used to initialize a communication state. Like from the 7 and 8th can be seen, the four-bit counter 240 and the clock generation and decoding circuit 260 reset by the system reset signal SYS_RST before a short frame is received by a card reader, not shown. The three-bit counter 250 is cleared by the clear signal from the clock generating and decoding circuit 260 reset so that the initial output signals of the two counters 240 and 250 be at zero. The RF block 210 outputs the data signal RF_IN at a high level. As soon as a first bit S of the short frame is fed to it, the RF block generates 210 a transition of the data signal RF_IN from high to low level. This starts the clock divider 220 its frequency division operation. The cycle time of the clock divider 220 supplied, divided clock signal DIV_CLK is ETU / 4.

The two counters 240 and 250 perform up-counts from their reset state on every rising and falling edge of the divided clock signal DIV_CLK. The clock generation and decoding circuit 260 receives the output signals from the counters 240 and 250 and builds rising and falling edges of the synchronous clock signal ETU_RX_CLK from them if these output signals assume predetermined specific values. Table 4 below illustrates that from the clock generation and decoding circuit 260 depending on the output signals of the counters 240 and 250 generated pattern of the synchronous clock signal ETU_RX_CLK.

If, for example, the output signal RX_IN_CNT4 of the counter 240 equal to "1" and the output signal STATE_CNT3 of the counter 250 are also equal to "1", a rising edge of the synchronous clock signal ETU_RX_CLK is built up. If the output signal RX_IN_CNT4 of the counter 240 the value "4" and the output signal STATE CNT3 of the counter 250 also has the value "4", a falling edge of the synchronous clock signal ETU_RX_CLK is built up. Overall, this results in a synchronous clock signal ETU_RX_CLK with a data rate of, for example, 106 kbps.

Table 4

This from combinations of the output signal values of the counters 240 and 250 built-up synchronous clock signal ETU_RX_CLK can by means of logic logic circuits in the clock generation and decoding circuit 260 be generated.

The clock generation and decoding circuit 260 generates the data signal RX_IN depending on the output signals RX_IN_CNT4 and STATE_CNT3 of the counter 240 and 250 and in response to the falling edge of the synchronous clock signal ETU_RX_CLK.

The data signal RF_IN with the modified Miller code takes the logic value "0" when the count The output value during an ETU is "0111" or "1111". Table 5 below shows the setting of the decoded data signal RX_IN to the logic value “1” as a function of the output signals of the counters 140 and 150 on the falling edge of the synchronous clock signal ETU_RX_CLK.

Table 5

For output values other than those given in Table 5 240 and 250 the data signal RX_IN is set to the logic value "0".

How out 8th can be seen, gives the clock generation and decoding circuit 260 for example, the data signal RX_IN with the logic value "1" when the output signal RX_IN CNT4 of the counter is on the falling edge of the synchronous clock signal ETU_RX_CLK 240 equal to "0" and the output signal STATE_CNT3 of the counter 250 is equal to "3." If the output signal RX_IN_CNT4 of the counter is on the falling edge of the synchronous clock signal ETU_RX_CLK 240 equal to "0" and the output signal STATE_CNT3 of the counter 250 is "3", the clock generating and decoding circuit gives 260 the data signal RX_IN with the logic value "0". In this way, the data signal RF_IN with the value "0111 1101 1101 1111 0111 1101" is converted into the decoded data signal RX_IN with the value "011001". The binary number "011001" corresponds to that Decimal number "26".

Table 6 below shows a code arrangement in the clock generating and decoding circuit 260 to generate the clear signal CLEAR to reset the counter 250 ,

As can be seen from Table 6, the counter 250 through logical combinations of the output signals of the two counters 240 and 250 reset.

The following code arrangement for identifying the end bit E, which marks the end of a frame, is provided in an analogous manner. The clock generation and decoding circuit 260 generates the associated end signal END_OF_RX depending on the output signals of the counter 240 and 250 according to Table 7 below.

Table 6

The clock generation and decoding circuit 260 activates the frame end signal END_OF_RX with a high level if one of the logical combinations of the output signals of the counters 240 and 250 of Table 7.

Table 7

According to the above-described embodiments, the clock generation and data recovery circuit generates 200 the synchronous clock signal ETU_RX_CLK with 0.11 MHz and the decoded data signal RX_IN, which makes it possible to receive data that can be adapted to the type A protocol according to ISO / IEC 14443.

The one-bit data pause period is eight clock cycles when the data rate is 106 kbps, and one-bit data appears during thirty-two cycles of the RF_CLK clock signal. In the 4 shown circuit 100 can restore an accurate signal if the pause period is within the range of six to eleven clock cycles. While six to ten clock cycles correspond to a time span from 1.764μs to 3.234μs, the pause period of the clock signal RF CLK in typical operating conditions is approximately 0.294μs to 4.704μs. The clock generation and data recovery circuit 200 for a contactless IC card used in the example of 7 the counter 240 as a four-bit counter and the counter 250 as a three-bit counter to track a possible fluctuation in the pause period. The circuit 200 Allows the pause period to fluctuate in the range from 0.884μs to 4.129μs, whereby a pause period from 0.589μs to 2.604μs for a data rate of 212kbps and from 0.294μs to 0.884μs for a data rate of 424kbps can be allowed.

As explained above, a contactless creates IC card according to the invention a synchronous clock signal from an RF signal from a card reader is received, so that an adaptation to a protocol of the type A according to ISO / IEC 14443 possible and decodes the received data signal. In addition, a exact decoding result can be achieved even when the pause period of the RF signal fluctuates within a certain range.

Claims (19)

Device for generating a clock signal and decoding data for a contactless integrated circuit component, characterized by - a receiver ( 110 ) for receiving a high-frequency signal with a pause period, - a divider ( 120 ) for dividing the received high-frequency signal to provide a divided signal, - a first counter ( 140 ) for counting a period of the divided signal during each non-pause period of the received high-frequency signal, - a second counter ( 150 ) for counting a period of the divided signal and - a decoder ( 160 ) to generate a synchronous clock signal (ETU_RX_CLK) and a decoded data signal (RX_IN) in response to output signals of the first and second counters. Apparatus according to claim 1, further characterized in that the first counter while the pause period of the high frequency signal is reset. Apparatus according to claim 1 or 2, further thereby characterized that the second counter on a falling edge of the synchronous clock signal reset becomes. Device according to one of claims 1 to 3, further thereby characterized that the radio frequency signal on an interface Type A according to the standard ISO-14443 based. Device according to one of claims 1 to 4, further thereby characterized in that the decoder has a signal (END_OF_RX) which indicates the end of a received data frame in response to generates the output signals of the first and second counters. Data recovery device for a contactless integrated circuit card, characterized by - a receiver ( 210 ) for receiving a high-frequency signal with a pause period and for extracting data and clock signals from the received high-frequency signal, - a divider ( 220 ) for dividing the clock signal supplied by the receiver in order to generate a divided clock signal, - a first counter ( 240 ) for counting a period of the divided clock signal in each non-pause period of the data signal, - a second counter ( 250 ) for counting a period of the divided clock signal and - a decoder ( 260 ) for generating a synchronous clock signal (ETU_RX_CLK) and a decoded data signal (RX_IN) in response to the output signals of the first and second counters. Apparatus according to claim 6, further characterized in that the first counter reset at the beginning of the pause period of the data signal becomes. Apparatus according to claim 6 or 7, further thereby marked that the first counter a three bit counter is. Device according to one of claims 6 to 8, further thereby characterized that the second counter in response to the synchronous Clock signal reset becomes. Device according to one of claims 6 to 9, further thereby characterized that the second counter on a falling edge of the synchronous clock signal reset becomes. Device according to one of claims 6 to 10, further thereby characterized in that the second counter is a two-bit counter. Device according to one of claims 6 to 11, further thereby characterized in that the output signal of the second counter is sequential varies between "0" and "2". Device according to one of claims 6, 7 and 9 to 12, further characterized in that the first counter is a four-bit counter. Device according to one of claims 6 to 13, further thereby characterized that the second counter depending on a combination the output signals of the first and second counters are reset. Device according to one of claims 6 to 10 and 12 to 14, further characterized in that the second counter is a three-bit counter. Device according to one of claims 6 to 15, further thereby characterized that the radio frequency signal on an interface Type A according to ISO-14443 based. Device according to one of claims 6 to 16, further thereby characterized in that the decoder sends a signal which marks the end of a received data frame indicates in response to the output signals of the first and second counter generated. Device according to one of claims 6 to 17, further characterized by an OR gate ( 130 ) for receiving a reset signal for resetting the card and the data signal, the first counter being reset by an output signal of the OR gate. Device according to one of claims 6 to 18, further characterized in that the divider comprises the following elements: - a plurality of plate units ( 121 to 127 ) looped in series between an input terminal and an output terminal, the input terminal receiving the clock signal from the receiver and each plate unit dividing an input signal by a factor N, with N as an integer, and - a selector ( 128 ) to select one of the output signals of the plate units in response to an external selection signal to provide the selected output signal as the divided clock signal.