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DE10345524A1 - Overlay measurement structure method e.g. for determining relative off set of two structure switch patters on semiconductor wafer via raster electron microscope - Google Patents

Overlay measurement structure method e.g. for determining relative off set of two structure switch patters on semiconductor wafer via raster electron microscope Download PDF

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Publication number
DE10345524A1
DE10345524A1 DE10345524A DE10345524A DE10345524A1 DE 10345524 A1 DE10345524 A1 DE 10345524A1 DE 10345524 A DE10345524 A DE 10345524A DE 10345524 A DE10345524 A DE 10345524A DE 10345524 A1 DE10345524 A1 DE 10345524A1
Authority
DE
Germany
Prior art keywords
semiconductor wafer
electron microscope
patters
range
structural components
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE10345524A
Other languages
German (de)
Other versions
DE10345524B4 (en
Inventor
Ansgar Teipel
Stefan Gruss
Hans-Georg Froehlich
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to DE10345524A priority Critical patent/DE10345524B4/en
Publication of DE10345524A1 publication Critical patent/DE10345524A1/en
Application granted granted Critical
Publication of DE10345524B4 publication Critical patent/DE10345524B4/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H10P74/277—
    • H10W46/00—
    • H10W46/501—

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Length-Measuring Devices Using Wave Or Particle Radiation (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

The method involves forming a structure with structural components within a first range of a layer of a substrate of the semiconductor wafer by means of photolithographic projection. The components of the structure are for circuit samples. A reference structure is formed by photolithographic projection where the reference structure is trained in such a way, that it encloses the first range. A second structure with structural components within a second range is provided by photolithographic projection, where the structural components have a reference structure partly surrounding the second range. A distance is measured between the first structural component and the reference structure by a scanning electron microscope, in order to determine first placing error. A second distance is measured between one of the second structural components and the reference structure by a scanning electron microscope. A misalignment of the first structural component to the second structural components is calculated from the placing errors. An independent claim is included for an overlay measuring structure for the determination of a relative misalignment of two structured circuit samples on a semiconductor wafer.
DE10345524A 2003-09-30 2003-09-30 Method for determining a relative offset of two structured circuit patterns on a semiconductor wafer by means of a scanning electron microscope Expired - Fee Related DE10345524B4 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE10345524A DE10345524B4 (en) 2003-09-30 2003-09-30 Method for determining a relative offset of two structured circuit patterns on a semiconductor wafer by means of a scanning electron microscope

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE10345524A DE10345524B4 (en) 2003-09-30 2003-09-30 Method for determining a relative offset of two structured circuit patterns on a semiconductor wafer by means of a scanning electron microscope

Publications (2)

Publication Number Publication Date
DE10345524A1 true DE10345524A1 (en) 2005-05-04
DE10345524B4 DE10345524B4 (en) 2005-10-13

Family

ID=34399116

Family Applications (1)

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DE10345524A Expired - Fee Related DE10345524B4 (en) 2003-09-30 2003-09-30 Method for determining a relative offset of two structured circuit patterns on a semiconductor wafer by means of a scanning electron microscope

Country Status (1)

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DE (1) DE10345524B4 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116165853A (en) * 2023-04-26 2023-05-26 长鑫存储技术有限公司 Overlay error measurement method, calibration method and semiconductor test structure

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5498500A (en) * 1993-12-27 1996-03-12 Hyundai Electronics Industries Co., Ltd. Overlay measurement mark and method of measuring an overlay error between multi patterns in a semiconductor device using the measurement mark
US5702567A (en) * 1995-06-01 1997-12-30 Kabushiki Kaisha Toshiba Plurality of photolithographic alignment marks with shape, size and spacing based on circuit pattern features
US6063529A (en) * 1996-10-29 2000-05-16 Hyundai Electronics Industries Co., Ltd. Overlay accuracy measurement mark
US6228705B1 (en) * 1999-02-03 2001-05-08 International Business Machines Corporation Overlay process for fabricating a semiconductor device
US6288452B1 (en) * 1998-03-27 2001-09-11 Nec Corporation Semiconductor device including registration accuracy marks
US20010048145A1 (en) * 2000-05-30 2001-12-06 Mitsubishi Denki Kabushiki Kaisha Photomask including auxiliary mark area, semiconductor device and manufacturing method thereof
US20010055720A1 (en) * 2000-06-08 2001-12-27 Kabushiki Kaisha Toshiba Alignment method, overlay deviation inspection method and photomask
US20030003677A1 (en) * 2001-06-27 2003-01-02 Canon Kabushiki Kaisha Alignment method, exposure apparatus and device fabrication method
WO2003071471A1 (en) * 2002-02-15 2003-08-28 Kla-Tencor Technologies Corporation Overlay metrology and control method

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5498500A (en) * 1993-12-27 1996-03-12 Hyundai Electronics Industries Co., Ltd. Overlay measurement mark and method of measuring an overlay error between multi patterns in a semiconductor device using the measurement mark
US5702567A (en) * 1995-06-01 1997-12-30 Kabushiki Kaisha Toshiba Plurality of photolithographic alignment marks with shape, size and spacing based on circuit pattern features
US6063529A (en) * 1996-10-29 2000-05-16 Hyundai Electronics Industries Co., Ltd. Overlay accuracy measurement mark
US6288452B1 (en) * 1998-03-27 2001-09-11 Nec Corporation Semiconductor device including registration accuracy marks
US6228705B1 (en) * 1999-02-03 2001-05-08 International Business Machines Corporation Overlay process for fabricating a semiconductor device
US20010048145A1 (en) * 2000-05-30 2001-12-06 Mitsubishi Denki Kabushiki Kaisha Photomask including auxiliary mark area, semiconductor device and manufacturing method thereof
US20010055720A1 (en) * 2000-06-08 2001-12-27 Kabushiki Kaisha Toshiba Alignment method, overlay deviation inspection method and photomask
US20030003677A1 (en) * 2001-06-27 2003-01-02 Canon Kabushiki Kaisha Alignment method, exposure apparatus and device fabrication method
WO2003071471A1 (en) * 2002-02-15 2003-08-28 Kla-Tencor Technologies Corporation Overlay metrology and control method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116165853A (en) * 2023-04-26 2023-05-26 长鑫存储技术有限公司 Overlay error measurement method, calibration method and semiconductor test structure
CN116165853B (en) * 2023-04-26 2023-09-29 长鑫存储技术有限公司 Overlay error measurement method, calibration method and semiconductor test structure

Also Published As

Publication number Publication date
DE10345524B4 (en) 2005-10-13

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8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee