DE10337562A1 - Production of a trench capacitor comprises forming a trench in a substrate using a hard mask with a corresponding opening, placing a capacitor dielectric in the trench and over the mask, and further processing - Google Patents

Abstract

Production of a trench capacitor comprises forming a trench (5) in a substrate (1) using a hard mask (2, 3) with a corresponding opening, placing a capacitor dielectric (30) in the trench and over the mask, pouring an electrically conducting filler (20) into the trench until it is below the upper side of an insulating collar (10), exposing an insulating region (IS) of the substrate above the upper side of the collar and forming an insulating layer (70) in the trench on the insulating region, exposing a contact region (KS) of the substrate lying opposite the insulating region and forming a conducting layer (90) in the trench on the contact region by selective epitaxy, and pouring a further conducting filler (21) in the trench above the sunk conducting filler (20).

Description

The The present invention relates to a manufacturing method for a Trench capacitor with an insulation collar over one buried contact on one side electrically connected to a substrate is, in particular for a semiconductor memory cell.

Even though in principle be applicable to any integrated circuits the present invention and its underlying problem in relating to integrated memory circuits in silicon technology explained.

1 shows a schematic sectional view of a semiconductor memory cell with a trench capacitor and a planar selection transistor connected thereto.

In 1 denotes reference numeral 1 a silicon semiconductor substrate. Provided in the semiconductor substrate 1 are trench capacitors GK1, GK2, which have trenches G1, G2, their electrically conductive fillings 20a . 20b form first capacitor electrodes. The conductive fillings 20a . 20b are in the lower and middle trench area through a dielectric 30a . 30b opposite to the semiconductor substrate 1 isolated, which in turn forms the second capacitor electrodes (possibly in the form of a buried plate, not shown).

In the middle and upper area of the trenches G1, G2 are circumferential insulation collars 10a . 10b provided, above which buried contacts 15a . 15b attached to the conductive fillings 20a . 20b and the adjacent semiconductor substrate 1 to be in electrical contact. The buried contacts 15a . 15b are only one-sided to the semiconductor substrate 1 connected (cf. 2a . b ). isolation regions 16a . 16b isolate the other substrate side from the buried contacts 15a . 15b or isolate the buried contacts 15a . 15b towards the top of the trenches G1, G2.

This allows a very high packing density of the trench capacitors GK1, GK2 and the associated selection transistors, which will now be explained. In this case, reference is mainly made to the selection transistor belonging to the trench capacitor GK2, since only the drain region D1 and the source region S3 are shown in adjacent selection transistors. The selection transistor belonging to the trench capacitor GK2 has a source region S2, a channel region K2 and a drain region D2. The source region S2 is connected via a bit line contact BLK to a bit line arranged above an insulation layer I (not shown). The drain region D2 is on one side to the buried contact 15b connected. Above the channel region K2 runs a word line WL2, which has a gate stack GS2 and a gate insulator GI2 surrounding it. The word line WL2 is an active word line for the selection transistor of the trench capacitor GK2.

Parallel adjacent to the word line WL2 run word lines WL1 consisting consisting of gate stack GS1 and gate insulator GI1 and word line WL3 from gate stack GS3 and gate insulator GI3, which for the selection transistor of the trench capacitor GK2 passive word lines are. These word lines WL1, WL3 serve to drive selection transistors, in the third dimension compared to the sectional view shown are shifted.

Obviously out 1 is the fact that this type of single-ended connection of the buried contact enables a direct juxtaposition of the trenches and the adjacent source regions or drain regions of the selection transistors. As a result, the length of a memory cell can only be 4 F and the width only 2 F, where F is the minimum technologically realizable unit of length (cf. 2a . b ).

2A shows a plan view of a memory cell array with memory cells according to 1 in a first arrangement possibility.

Reference DT in FIG 2A denotes trenches which are arranged line by line with a period of 4 F to each other and column by column with a period of 2 F. Adjacent lines are shifted by 2 F against each other. UC in 2A denotes the area of a unit cell which is 4 F × 2 F = 8 F ² . STI denotes isolation trenches, which are arranged in the row direction at a distance of 1 F to each other and isolate adjacent active areas against each other. Also at a distance of 1 F each other run bit lines BL in the row direction, whereas the word lines in the column direction at a distance of 1 F to each other. In this arrangement example, all the trenches DT on the left side have a contact area KS of the buried contact with the substrate and an isolation area IS on the right side (areas 15a . b respectively. 16a . b in 1 ).

2 B shows a plan view of a memory cell array with memory cells according to 1 in a second arrangement possibility.

In this second arrangement possibility, the rows of trenches have alternating terminal regions or isolation regions of the buried contacts. So are in the bottom row of 2 B the buried contacts each on the lin Ken side with a contact area KS1 and on the right side with an isolation area IS1 provided. On the other hand, in the row above, all trenches DT on the left side are provided with each isolation area IS2 and on the right side with a contact area KS2. This arrangement is alternating in the column direction. However, it requires additional lithography steps.

The Object of the present invention is a simple and safe manufacturing method for such a one-sided specify connected trench capacitor.

According to the invention this Task by the production method specified in claim 1 solved.

The Advantages of the method according to the invention lie in particular in the fact that there is a precise definition of the connection area or the complementary one Isolation area at the respective buried contact of the trench capacitor allows.

In the dependent claims find advantageous developments and improvements of in claim 1 specified production method.

According to one preferred development happens the provision of the insulation layer in the trench on the isolation area by selective oxidation.

According to one Another preferred development, the following to expose the isolation area Steps performed: Remove the capacitor dielectric to the top of the electrical conductive filling; Providing a thermal silica liner and an overlying one Silicon nitride liner over the resulting structure; Forming a mask from a first Silicon liner layer; Removing the silicon nitride liner over the isolation area by means of the mask; and optionally leaving the thermal silica liner above Quarantine.

According to one Another preferred embodiment, the mask is formed Will that silicon liner layer over the trench and the hard mask is deposited, then one straight and one oblique Implantation of boron ions or boron ions in particular performed the trench and then the mask is patterned by a selective etch.

According to one Another preferred development to the exposure of the contact area after the steps of forming the insulating layer are: forming a mask of a second silicon liner layer; Remove the thermal silica liner and silicon nitride liner over the Contact area using the mask.

According to one further preferred embodiment, the mask is formed by that the silicon liner layer over the trench and the hard mask is deposited, then a in particular implantation of boron ions or boron-containing ions performed in the ditch and then the mask is patterned by a selective etch.

According to one Another preferred development, the following to expose the isolation area Steps performed: Providing a silicon nitride liner and an overlying one Silicon oxide liner over the capacitor dielectric; Forming a mask from a third one Silicon liner layer; Removing the silicon nitride liner and the Silicon oxide liner over the isolation area by means of the mask; Removing the mask; and Removing the capacitor dielectric over the isolation area.

According to one Another preferred embodiment, the mask is formed Will that silicon liner layer over the trench and the hard mask is deposited, then a straight implantation in particular of boron ions or borhalti conditions Ions carried in the trench and then the mask is patterned by a selective etch.

According to a further preferred development, the following steps are performed to provide the insulation layer: deposition of a silicon oxide layer over the trench and the hard mask after exposure of the insulation region; Forming a mask of an Al ₂ O ₃ liner over the silicon oxide layer; Removing the silicon oxide layer over the contact area by means of the mask.

In accordance with a further preferred development, the mask is formed by depositing the Al ₂ O ₃ liner layer over the silicon oxide layer, then performing a straight implantation and an oblique implantation, in particular of nitrogen ions, into the trench and then the mask by a selective etching is structured.

embodiments The invention is illustrated in the drawings and in the following Description closer explained.

It demonstrate:

1 a schematic sectional view of a semiconductor memory cell with a trench capacitor and a planar selection transistor connected thereto;

2A . B a respective plan view of a memory cell array with memory cells according to 1 in a first and second arrangement possibility;

3A -L are schematic representations of successive process stages of a manufacturing process as a first embodiment of the present invention; and

4A -E schematic representations of successive process stages of a manufacturing process as a second embodiment of the present invention.

In the same reference numerals designate the same or functionally identical Ingredients.

at The embodiments described below are for the sake of clarity to a description of the fabrication of the planar select transistors omitted and only the formation of the unilaterally connected buried contact of the trench capacitor discussed in detail. The steps of manufacture the planar select transistors are the same unless otherwise stated as in the prior art.

3A -L are schematic representations of successive process stages of a manufacturing process embodying the present invention.

In 3A denotes reference numeral 1 a silicon semiconductor substrate having on its surface OS a pad oxide layer 2 and a pad nitride layer 3 are provided. The pad oxide layer 2 and the pad nitride layer 3 Together form a hard mask, with a ditch 5 has been generated in the substrate. Provided in the middle and upper trench area is a substrate 1 integrated insulation collar 10 made of silicon oxide, but not up to the top OS of the substrate 1 enough.

In the ditch 5 and on the surface of the pad nitride layer 3 deposited is a capacitor dielectric 30 , for example, silicon nitride. Furthermore, in the ditch 5 a conductive filling 20 made of polysilicon, which extends below the top of the insulation collar 10 in the ditch 5 is sunken.

Regarding 3B first becomes the capacitor dielectic 30 up to the level of the conductive filling 20 sunk. Then it will go over the structure of 3A a thermal oxide layer 50 formed and over the thermal oxide layer 50 a silicon nitride liner layer 55 deposited.

Continue with reference to 3C Then, an amorphous silicon liner layer is formed over the resulting structure 60 deposited. Following the deposition on the silicon liner layer 60 Two ion implantations I1, I2 are carried out with boron ions or boron-containing ions. The implanted region of the silicon liner layer 60 has a lower etch rate for an alkaline etch such as an NH ₄ OH etch than the shadowed or unimplanted areas, respectively 60a ,

As in 3C recognizable, the first ion implantation I1 is substantially parallel to the normal of the surface OS of the substrate 1 whereas the second ion implantation I2 in 3C inclined to the right opposite the normal, so that they are essentially only one half of the trench 5 meets and forms a certain overlap with the previous ion implantation I1.

As in 3D shown, followed by a selective alkaline etching with NH ₄ OH as the etching medium to the shaded areas 60a the silicimliner layer 60 to remove.

Continue with reference to 3E thereafter becomes the exposed area of the silicon nitride liner 55 removed by wet etching. After that, as in 3F shown an etch to remove the remaining implanted region of the silicon liner 60 , Now, the later contact area KS of the substrate 1 through the silica liner 50 and the overlying silicon nitride liner 55 whereas the later isolation region IS of the substrate is masked 1 only through the silica liner 50 is covered.

As in 3G shown, then takes place in the upper trench area above the insulation collar 10 in the silicon nitride liner 55 later isolation area IS liberated a local oxidation to form an insulation layer 70 ,

After performing the local oxidation step, an amorphous silicon liner is again formed 80 deposited over the resulting structure. Also in this silicon liner layer 80 For example, an implantation I3 of boron ions or boron-containing ions is carried out, the implantation I3 being essentially parallel to the normal of the surface OS of the substrate 1 runs. The shaded areas resulting from the implantation I3 are with 80a designated.

Regarding 3I Then there is a selective removal of the shaded areas 80a by means of alkaline NH ₄ OH etching.

In a further process step, the in 3J is illustrated, thereafter becomes the exposed portion of the silicon nitride liner 55 located on the left side of the trench in the figure.

In the following process step, the in 3K is thereafter also the exposed portion of the thermal Siliziumoxidliners 50 removed so that the surface of the substrate 1 is exposed in the later contact area KS on the left side of the trench in the figure, wherein the right trench side through the insulating layer 70 is isolated and being the lower trench area with the filling 20 through the remaining liner residues 50 . 55 remains protected.

Regarding 3L Then, a selective epitaxial growth of a conductive polysilicon layer 90 in the connection area KS, in order to move away the later burial contact away from the memory cell array to the trench center.

Consequently are the connection area KS and the opposite isolation area IS clearly defined, and the subsequent process steps are known per se, which is why they are mentioned here only briefly.

In the subsequent process step, after providing a (not shown) thin Siliziumnitridliners over the entire structure is then carried out a re-deposition and etching back of a conductive polysilicon filling 21 to the conductive filling 20 with the polysilicon layer 90 and above with the substrate 1 connect to.

When re-etching the further polysilicon filling 21 also becomes the polysilicon layer 90 something etched back to a later closing of the trench 5 with an insulation cover 71 to enable. Finally, the separation and re-etching of the insulation cover takes place 71 of silicon oxide for closing the trench 5 ,

4A -E are schematic representations of successive process stages of a manufacturing process as a second embodiment of the present invention.

The in 4A Process state shown corresponds to that in 3A shown process state.

Regarding 4B On the resulting structure, a silicon nitride liner layer is formed 150 deposited and an upper portion of the Siliziumnitridlinerschicht 150 in a silicon oxide liner layer 155 converted. In this connection, it should be noted that in this second embodiment, in contrast to the first embodiment, the capacitor dielectric 30 in the trench and on the surface of the pad nitride layer 3 remains.

Regarding 4C becomes an amorphous silicon liner in a subsequent process step 160 deposited over the entire structure. Thereupon, an ion implantation I1 'of boron ions or boron-containing ions takes place, the direction of which runs essentially parallel to the normal top side OS of the semiconductor substrate. In this ion implantation I1 'remain the areas 160a the silicon liner layer 160 shadowed.

In the following process step, the in 4D is illustrated, then takes place a selective removal of the shaded areas 160A by means of an alkaline NH ₄ OH etching. This is followed by an etching of the exposed Siliziumoxidlinerschicht 155 and the underlying silicon nitride liner layer 150 ,

Subsequently, with reference to 4E the remaining silicon liner layer 160 removed in a further etching step. Thereafter, using the remaining Siliziumoxidlinerschicht 155 the capacitor dielectric 30 removed from the trench, whereupon also the Siliziumoxidlinerschicht 155 Will get removed. Now the substrate is 1 both in the later connection area KS (left side of the figure) and in the later isolation area IS (right side of the figure) exposed.

Continue with reference to 4F then becomes a silicon oxide layer 170 deposited over the resulting structure and above an Al ₂ O ₃ liner layer 180 formed and annealed to make them crystalline.

Following the formation of the Al ₂ O ₃ liner layer 180 First, an ion implantation I2 'with nitrogen ions, whose direction is substantially parallel to the normal of the top surface OS of the substrate 1 lies. This is followed by another ion implantation I3 'of nitrogen ions, the direction of which is tilted to the right with respect to the normal top surface OS of the substrate in the drawing, so that the regions 180a are shadowed after this second ion implantation I3 '.

In the subsequent process step, which in 4G is illustrated, then takes place a selective wet etching of the implanted regions of the Al ₂ O ₃ liner layer 180 , In contrast to the abovementioned boron implantation I1 ', the nitrogen implantations I2' and I3 'increase the etching rate of the implanted regions of the Al ₂ O ₃ liner layer 180 , so that according to 4G be selectively removed. Thus, one creates an inverse mask structure with regard to the implantation.

Subsequently, by means of the mask Etching the silicon oxide layer 170 in the later connection area KS and on the ground.

At the in 4G shown process state, the later connection area KS (left side of the figure) exposed, whereas the later isolation area IS (right side of the figure) exposed by the remaining silicon oxide layer 170 is covered.

Continue with reference to 4H Then, an etching of the remaining areas 180a the Al ₂ O ₃ liner layer 180 , a selective epitaxial growth of a conductive polysilicon layer 190 in later terminal area and etching of the silicon nitride liner layer 150 where the top of the conductive filling 20 is exposed in the middle region of the trench.

Finally done Further known per se process steps analogous to the above first embodiment, which only briefly mentioned here become.

In the next subsequent process step, after provision of a (not shown) thin Siliziumnitridliners over the entire structure is carried out a re-deposition and etching back of a conductive polysilicon filling 121 to the conductive filling 20 with the polysilicon layer 190 and above with the substrate 1 connect to.

When re-etching the further polysilicon filling 121 also becomes the polysilicon layer 190 something etched back to a later closing of the trench 5 with an insulation cover 171 to enable. Finally, the separation and re-etching of the insulation cover takes place 171 of silicon oxide for closing the trench 5 ,

Even though the present invention above based on a preferred embodiment It is not limited to this, but in many ways and modifiable.

Especially is the selection of the layer materials, in particular the liner layers, only as an example and can be varied in many ways.

Also can instead of boron ions or boron-containing ions, also neutral ions or ions other doping type can be used. The same applies to nitrogen implantations.

Claims (10)

Manufacturing method for a trench capacitor with an insulation collar ( 10 ) in a substrate ( 1 ) which, via a buried contact, is unilaterally connected to the substrate ( 1 ) is electrically connected, in particular for a semiconductor memory cell with a in the substrate ( 1 ) and connected via the buried contact planar selection transistor, comprising the steps of: providing a trench ( 5 ) in the substrate ( 1 ) using a hard mask ( 2 . 3 ) with a corresponding mask opening; Providing a capacitor dielectrics ( 30 ) in the ditch ( 5 ) and over the hard mask ( 2 . 3 ); Providing an electrically conductive filling ( 20 ) in the ditch ( 5 ), which are below the top of the insulation collar ( 10 ) is sunken; Exposing an isolation region (IS) of the substrate ( 1 ) in the ditch ( 5 ) above the top of the insulation collar ( 10 ) and providing an insulation layer ( 70 ; 170 ) in the ditch ( 5 ) on the isolation area (IS); Exposing a contact region (KS) of the substrate (KS) which is opposite to the isolation region (IS) 1 ) in the ditch ( 5 ) and providing a conductive layer ( 90 ; 190 ) in the ditch ( 5 ) on the contact area (KS) by selective epitaxy; and providing a further conductive filling ( 21 ; 121 ) in the ditch ( 5 ) above the depressed conductive filling ( 30 ), which via the conductive layer ( 90 ; 190 ) is in conductive connection with the contact region (KS) and which through the insulating layer ( 70 ; 170 ) is isolated from the isolation region (IS). Method according to claim 1, characterized in that the provision of the insulating layer ( 70 ) in the ditch ( 5 ) on the isolation region (IS) by selective oxidation. Method according to claim 1 or 2, characterized in that the following steps are carried out to expose the isolation region (IS): removal of the capacitor dielectric ( 30 ) to the top of the electrically conductive filling ( 20 ); Providing a thermal silicon oxide liner ( 50 ) and an overlying silicon nitride liner ( 55 ) over the resulting structure; Forming a mask from a first silicon liner layer ( 60 ); Removing the silicon nitride liner ( 55 ) over the isolation region (IS) by means of the mask; and optionally leaving the thermal silica liner ( 50 ) above the isolation area (IS). A method according to claim 3, characterized in that the mask is formed by the fact that the silicon liner layer ( 60 ) above the ditch ( 5 ) and the hard mask ( 2 . 3 ), then a straight and an oblique implantation (I1, I2), in particular of boron ions or boron-containing ions into the trench ( 5 ) and then the mask is patterned by a selective etch. Method according to one of the preceding Claims, characterized in that in order to expose the contact area (IS) after the formation of the insulation layer ( 70 ) the following steps are performed: forming a mask from a second silicon liner layer ( 80 ); Removal of thermal silica liner ( 50 ) and the silicon nitride liner ( 55 ) over the contact area (KS) by means of the mask. A method according to claim 5, characterized in that the mask is formed by the fact that the silicon liner layer ( 80 ) above the ditch ( 5 ) and the hard mask ( 2 . 3 ), then a straight implantation (I3), in particular of boron ions or boron-containing ions into the trench ( 5 ) and then the mask is patterned by a selective etch. Method according to claim 1 or 2, characterized in that the following steps are carried out for exposing the insulation region (IS): provision of a silicon nitride liner ( 150 ) and an overlying silicon oxide liner ( 155 ) over the capacitor dielectric ( 30 ); Forming a mask from a third silicon liner layer ( 160 ); Removing the silicon nitride liner ( 150 ) and the silicon oxide liner ( 155 ) over the isolation region (IS) by means of the mask; Removing the mask; and removing the capacitor dielectric ( 30 ) above the isolation area (IS). A method according to claim 7, characterized in that the mask is formed by the fact that the silicon liner layer ( 160 ) above the ditch ( 5 ) and the hard mask ( 2 . 3 ), then a straight implantation (I1 '), in particular of boron ions or boron-containing ions into the trench ( 5 ) and then the mask is patterned by a selective etch. A method according to claim 7 or 8, characterized in that for providing the insulating layer ( 170 ) the following steps are carried out: deposition of a silicon oxide layer ( 170 ) above the ditch ( 5 ) and the hard mask ( 2 . 3 after exposing the isolation area (IS); Forming a mask from an Al ₂ O ₃ liner layer ( 180 ) over the silicon oxide layer ( 170 ); Removing the silicon oxide layer ( 170 ) over the contact area (KS) by means of the mask. A method according to claim 9, characterized in that the mask is formed by the Al ₂ O ₃ liner layer ( 180 ) over the silicon oxide layer ( 170 ), followed by a straight implantation (I2 ') and an oblique implantation, in particular of nitrogen ions, into the trench ( 5 ) and then the mask is patterned by a selective etch.