DE10326716A1 - Automatic development of modified standard cell for semiconducting component involves automatically optimizing parameter in respect of stored discrete parameters according to defined target function - Google Patents

Abstract

The method involves using a standard cell database with pre-stored parameters for at least one standard cell (1), whereby at least one parameter is automatically optimized in respect of the stored discrete parameters in accordance with a defined target function, whereby the optimal solution deviates from the discrete gradations of the parameters of the standard cell database.

Description

The The invention relates to a method for automatically designing a modified standard cell for a semiconductor component according to the preamble of claim 1.

The The invention relates to the place & route process used in the design of semiconductor circuits to place and wire the standard cells.

At the Designing ASICs is a high number (compared to memory design) of metal levels available for wiring, so that the standard cells can be placed very tightly; the wiring of the cells with each other is unproblematic.

at Memory devices (e.g., DRAMs) have fewer metal levels available leaving room for Wiring needed becomes. If you want to use standard cells, e.g. in the periphery of memory modules Arrange, typically only three metal levels in total and two of them for the wiring of the standard cells available. As these are the metal levels also partly in the standard cells and for the power supply Wiring is more difficult here than with the ASIC design. For this reason, only a much lower density the standard cells are reached.

on the other hand is currently working on a high-volume product, such as the DRAM memory the need for space optimization very much in the foreground, so that even more compared to the ASIC design Effort in the area optimization the standard cells can or must be plugged.

At the Design of such circuits uses databases that are standard cells with different functions included (flip-flops, logic gates Etc.). These databases were created to make the design more complex Making circuits easier, which leads to certain design assumptions by discrete gradations of certain parameters in the database are stored permanently. This can lead to problems because these are fixed design specifications in conflict with other target functions, in particular the space requirement for wiring can reach.

at The production of standard cells requires different drive strengths (Amperage) to provide various capacitive loads (due to connected to drive other standard cells and the lines there to drive). This grading is done in discrete stages, which are not necessarily the available area optimally exploit in the standard cell, because all standard cells into a given grid with the same height and discretely stepped width values have to fit.

But not only the absolute driver strengths become discrete values uses.

At usual Standard cell libraries are the standard in multi-level standard cells drive strengths graded so that the signal propagation time from the input to the output considering the standard cell the input capacity preferably is short. In the literature (e.g., Ivan Sutherland et al., "Logical Effort" Morgan, Kaufmann Publishers, Inc., San Francisco, 1999; Page 59) are for grading Values in the range of "4" are recommended, where slight deviations from this theoretical optimum value (which also depends on the characteristics of the technology) even very small Deviations from the optimal signal propagation time has the consequence. These But gradation is usually one for all standard cells Library uniformly selected or a specific gradation range is specified. The usual Databases for Standard cells assume that all standard cells are optimized in the direction of "signal propagation time". A group of standard cells that differ from this specification are not available.

Should Such cells, however, are used in paths where the Signal transit time plays no or no major role ("noncritical cells"), the Gradation actually be chosen larger, which gives advantages in other parameters (such as cell area or pin capacitance) achieve.

Of the The present invention is based on the object, a method to create, with the existing standard cells in a targeted manner be modified to use this more flexible.

These The object is achieved by a Method solved with the features of claim 1.

In this case, for at least one standard cell stored in the standard cell database, at least one parameter is automatically optimized with respect to the stored discrete parameter according to a predetermined objective function, the optimized solution deviating from the discrete steps of the parameters of the standard cell database. The standard cell database, which is implemented on a data processing system, is thus au modified automatically.

there it is advantageous if the parameters of the optimized solution turn be included in the standard cell bank, so they further Draft process or for new designs for disposal stand.

In an advantageous embodiment the method according to the invention there is a variation of the driver strengths of at least one inverter circuit, at least one P-FET, at least one N-FET and / or a variation of the minimum needed Place for Wiring to optimize the ratio between driver strength and area the standard cell and / or the space for wiring within the Standard cell.

Also it is advantageous if a variation of the ratios of the widths at least two transistors of an inverter circuit, in particular a p-type field effect transistor and an n-type field effect transistor to maximize the space for wirings within the standard cell is done. It is particularly advantageous if a Optimization of an amplifier circuit to maximize the space for Wiring within the standard cell takes place.

With Advantage is an optimization of the amplifier circuit by optimization the relative size values in the amplifier circuit existing elements, in particular of gates and / or inverters.

The Invention will be described below with reference to the figures of Drawings on several embodiments explained in more detail. It demonstrate:

1a to 1c schematic representation of standard cells with different driver strength;

2a to 2c schematic representation of modified standard cells with optimized wiring space;

3a . 3b schematic representation of an amplifier circuit for critical signal paths ( 3a ) and non-critical signal paths ( 3b );

4a . 4b schematic representation of an amplifier circuit for critical signal paths ( 4a ) and optimized for minimum area and minimum input capacity;

5a . 5b schematic representation of a critical path amplifier circuit ( 5a ) and non-critical paths.

Based on 1a to 1c the mode of operation of an embodiment of the method according to the invention should be illustrated. In the 1a to 1c is a standard cell 1 shown. Every standard cell 1 has two transistors, a p field effect transistor (P-FET) and an n field effect transistor (N-FET). There is a space for wiring between the transistors 10 ,

In standard standard cell libraries, the driver strengths are the standard cells 1 graded with the factor 2, ie a stronger driver variant can, under the same electrical conditions, each drive double capacitive load.

For all transistors in the standard cells 1 a layout frame must be found which has a constant height and whose width is variable. This layout frame is discretely graded by a given grid. Transistors which do not fit in the height of the layout frame have to be distributed over several so-called fingers, which is the width of the standard cell 1 elevated.

requires e.g. a certain driver strength one Transistor width w of 4.0, but the layout frame only allows maximum 3.5 per transistor, then this transistor must be on two fingers be distributed. On the same surface, however, would have a transistor 7.0 (i.e., two fingers of maximum width 3.5).

However, after the driver strengths are discretely scaled by a factor of 2 and correspondingly only discretely graded values are used for the transistor widths w, these intermediate values can not be used and in many cases non-optimal area utilization in the standard cells occurs 1 ,

For different standard cells 1 will have different space for wiring 10 the transistors needed. As a result, even the width of the transistors that optimally fit in the layout frame, not all standard cells 1 is equal to. Since in conventional standard cell libraries, the driver strengths are always graded uniformly for all cells, it always comes to suboptimal area utilization, at least for some standard cells 1 ,

In 1a a simple inverter is shown in which the transistor areas (P-PET, N-PET) in compliance with the technology-related minimum distances together with the minimum space required for wiring 10 the transistors in the middle make optimum use of the available area of the standard cell. In the 1a to 1c the height of the transistors can be seen as a measure of the width w of the transistors. The p-field effect transistor P-FET has a width w = 11, the n-field effect transis Gate N-FET has a width w = 9.

The problem is that this optimal inverter deals with the standard cells stored in the database 1 can not map. Enlarging the transistors, and thus increasing the drive strength, would only be possible by increasing the area of the standard cell 1 possible.

1b shows an inverter that corresponds to a driver strength of "2". The widths w = 11 and w = 7.5 of the transistors are predetermined by the driver strength. The available area is not completely filled together with the wiring.

1c on the other hand shows an inverter with the driver strength "4", which has a width w = 11 × 2 = 22 or 7.5 × 2 = 15 due to the discrete screening. Due to the transistor widths given thereby the space in the cell is not sufficient, so that both transistors must be distributed to two fingers, whereby the width of the standard cell increases significantly.

In this example, the in 1a have a driver strength factor of about 13/11 x 2 or 9 / 7.5 x 2 = 2.4 (determined by the width of the transistors in the "optimal inverter" versus the "small inverter" in FIG 1b having the driver strength "2"); Conventional standard cell libraries do not use such "crooked" values of driver strength.

An embodiment of the method according to the invention for producing modified standard cells is explained below. The solution is that beside and / or in place of the discrete factor 2 (or other factor) graded driver strengths, variable driver strengths are used to design standard cells 1 be used. This embodiment of the method according to the invention thus enables an automatic modification of the standard cells to generate new solutions. The solutions do not correspond to discrete values. Also, the solutions may vary from standard cell to standard cell. When these new solutions are stored in the database, a database supplement can be automatically made; ie new solutions are purposefully and automatically generated for existing solutions.

As a guide to the width w of the transistors of the output stage of the respective standard cell 1 used so that the transistors of the output stage (taking into account in the respective standard cell 1 necessary wiring space) have a maximum width w of the fingers and thus the ratio of driver strength to standard cell area 10 is optimized.

In a second step then becomes the transistors of the other stages varies within certain limits in order to save some fingers can (if this causes an area reduction of Cell results). In an extension of the invention may also the latitudes between p field effect transistor and n-field effect transistor of a stage varies within certain limits if this results in a reduction in area the cell possible is. This is especially true if it is not the output stage often without appreciable influence on the behavior of the cell possible.

A Gradation of driver strengths exactly with the factor "2" is not necessary required; this grade may be finer or coarser as needed.

This ensures that variants are available for all cell types that optimally exploit the available space in the standard cell area. Also, with consistent application of the method required for the same performance space of the standard cells 1 be reduced or it is to be expected with the same space requirement with slightly increased performance of the circuit.

As an example, the example below 1a to 1c used. With reference to the p-type field effect transistor, the small inverter ( 1b ) a driver strength "2" a width of 11, the large inverter ( 1c ) with driver strength "4" a width of 22. The optimal inverter ( 1a ) has a driver strength of 2.4 at a width of 13.

By applying the concept to larger driver strengths, the following gradation could be achieved in this example (the new, surface-optimal values are underlined): drive strength width 11 2 13 2.4 22 (2 × 11) 4 26 (2 × 13) 2.8 33 (3 × 11) 6 39 (3 × 13) 7.2 44 (4 × 11) 8th

In this example, for the sake of simplicity, the allowable assumption is made that the minimum space required for wiring 10 between the transistors n-FET, p-FET remains the same with increasing number of fingers for the transistors.

As mentioned above, can (in particular by the different sized minimum required Wiring space), the optimal driver strength varies from cell to cell be.

In the 2a to 2c this is described. In 2a an initial form is shown in which in the standard cell 1 between the transistors (n-FET, p-FET, three fingers each) a minimum necessary area for wirings 10 consists. In comparison, the standard cell needs 1 according to 2 B a larger minimum space for wiring 10 , which has the consequence that only a smaller maximum width w of the individual transistors or the fingers is allowed. In 2c There will be relatively little space for the wiring 10 needed, which allows a greater width w of the transistors or fingers.

In the following, embodiments of the method according to the invention are described, which concern the gradation of the driver strengths in the case of multistage standard cells 1 goes. It is here specifically on standard cells 1 where the signal propagation time is not critical, so that a change in gradation compared to the "normal" standard cells is possible, which may make a deterioration of the runtime behavior appear tolerable. However, an improvement in the area requirement, the power consumption and / or the wiring is achieved by such a deterioration.

This is related to the 3a and 3b which explains a simple noninverting amplifier 20 relate, having two inverters.

The amplifier 20 in 3a consists of two inverters 21 . 22 with the staggered size values of "3 and" 12 ", so the grading has a factor of" 4 ", which gives the best signal propagation time according to the theory in runtime-critical cases.

In 3b is an amplifier 20 shown having the staggered size values of "1" and "12". The gradation has the factor "12", so that the signal propagation time is deteriorated from the optimum value. At runtime uncritical signal paths this may be tolerated. In particular, with this gradation, a slightly smaller area of the standard cell 1 and a lower capacity of the input (and thus a lower load of previous stages) can be achieved.

The following standard cells are suitable for the application of this method:
Scan-path flip-flops: attenuation of driver strength in the input area (ie in the area of the scan multiplexer)
AND / OR gate: attenuation of driver strength in the input area
Buffer (non-inverting): attenuation of the first-stage driver strengths

By this embodiment of the method according to the invention, it is avoided that standard cells 1 combined (eg NAND gates and inverters to an AND gate) in order to achieve a desired gradation. This combination would lead to a larger area requirement.

A slightly more complex example that in 4 is illustrated, this clarifies.

In the 4a and 4b The circuit shown consists of an AND gate 30 (composed of a NAND 31 and an inverter 32 in the respective upper half of the picture, with dashed frame). This AND gate 30 drives a noninverting amplifier 20 that made two inverters 21 . 22 in the respective lower half of the picture, with a dotted frame.

Because the AND gate 30 , as indicated on the right, to drive further, not shown here standard cells, at the output of this AND gate, a large driver strength (here "12") is required.

The 4a describes the default configuration, because the gradation within the AND gate 30 and the non-inverting amplifier 20 has the factor "4". The non-standard configuration that is generated with an embodiment of the method according to the invention is in 4b shown. The circuit elements correspond to those in 4a presented version. However, the gradation is within the AND gate 30 and the non-inverting amplifier 20 each different and it deviates from the optimal value "4".

Compared to the standard implementation ( 4a ) is in the implementation with coarse gradation of the driver strength ( 4b ) Is not the only reason to spend a smaller cell area because the respective input levels are reduced, but ^`also because due to the reduced pin capacitance of the inputs of the output of the AND gate 30 as a result, it has less load to drive and therefore can be slightly reduced in its output stage ("10" instead of "12"). Under the plausible assumption that the surface area requirement of the standard cells grows in proportion to the drive strength (which may only be approximately approximate in reality due to fitting to a discrete grid and a fixed cell height), in this example the circuit composed of cells for non-critical paths would be on the right opposite the standard version on the left 20% smaller (sum of driver strengths 4a = "30", 4b = "24"). Thus, the solution is according to 4b for both the minimum area of the standard cell 1 as well as optimized for the input capacity.

It is particularly advantageous if this method with the above in connection with the 1 and 2 described method of driver strength optimization based on the available layout surface is combined. In this case, one would consider the internal grading of driver strengths in multistage standard cells 1 for non-critical paths, make sure that at least the first step surface is designed optimally (ie, if possible with only one "finger").

This is based on 5a and 5b described. In 5a an amplifier circuit for a time-critical layout is shown, in 5b a non-term critical. In the standard cells 1 are contained in each case a plurality of transistors n-FET, p-FET, wherein it is possible by an embodiment of the method according to the invention, the space requirement of the standard cell in non-transit time critical case ( 5b ) compared to the maturity-critical case ( 5a ) to reduce by almost a third.

This is achieved by the input stage 41b for the non-critical case versus the input stage 41a in the critical case of two is reduced to a finger. The width w of the second-stage fingers 42b is used in the non-critical case ( 5a ), until only the minimum space required for wiring 10 remains. With only a slight reduction of the total driver strength, a non-critical case becomes a second-stage finger 42b saved. In the critical case according to 5a be in the second stage 42a four fingers needed.

The Driver strength ratio between Increased output and input level in this (simplified) example from 2: 1 to 3: 1, while the standard cell area by almost a third decreases.

By the insertion some additional multi-level Standard cells for the use in for the term noncritical paths and / or the deviation when Driver strength ratio between Output and input stage of the theoretical optimum (on signal propagation time related), other parameters, In particular, the standard cell area can be improved.

The Restricted invention in their execution not to the preferred embodiments given above. Rather, a number of variants are conceivable that of the inventive method also in principle different types Make use.

1

standard cell

10

space for wiring within a standard cell

20

amplifier circuit

21

inverter

22

inverter

31

NAND gate

32

inverter

41a

doorstep (for signal propagation time critical case)

41b

doorstep (for signal propagation time uncritical case)

42a

Second Stage (for Signal delay critical case)

42b

Second level (for Signal delay uncritical case)

w

transistor width

Claims (6)

A method of automatically designing a modified standard cell for a semiconductor device using a standard cell database having prestored parameters for at least one standard cell, wherein at least one parameter of the standard cell is stored in discrete increments in the standard cell database, characterized in that for at least one standard cell stored in the standard cell database ( 1 ) at least one parameter is automatically optimized with respect to the stored discrete parameter according to a predetermined objective function, wherein the optimized solution deviates from the discrete gradation parameters of the standard cell database. Method according to claim 1, characterized in that that the parameters of the optimized solution in the standard cell bank is recorded. Method according to claim 1 or 2, characterized by a variation of the driver strengths of at least one inverter circuit, at least one P-FET, at least one N-FET and / or a variation of the minimum required space for wirings ( 10 ) for optimizing the ratio between driver strength and area of the standard cell and / or the space for wiring ( 10 ) within the standard cell ( 1 ). Method according to Claim 3, characterized by a variation of the ratios of the widths (w) of at least two transistors of an inverter circuit, in particular a p field effect transistor and an n field effect transistor, in order to maximize the space for wirings ( 10 ) within the Stan standard cell ( 1 ). Method according to at least one of the preceding claims, characterized in that an optimization of an amplifier circuit for maximizing the space for wiring ( 10 ) within the standard cell. Method according to Claim 5, characterized in that the amplifier circuit is optimized by optimizing the relative magnitude values of the elements present in the amplifier circuit ( 21 . 22 . 31 . 32 ), in particular of gates and / or inverters.