DE10322882A1 - Integrated memory circuit with dynamic memory cell, into which date is to be written, fitted on word line and bit line, while read-out amplifier is coupled to two supply lines for high and low supply potential respectively to amplify charge - Google Patents

Abstract

Dynamic memory cell (1) is fitted on word line (WL) and bit line (BL1). Read-out amplifier (3) is coupled to first supply line (12) for high supply potential and second supply line (13) for first low supply potential to amplify charge difference on two bit lines (BL1,2). Two data lines (17) are connectable, via circuit (5) to both bit lines to write datum, by activating this circuit (5), according to two data signals (LDQ1,2) to both bit lines. Control (L1) separates both supply line from supply potentials, with connecting circuit activation, to deactivate amplifier. Independent claims are included for method to write data signal into memory cell.

Description

The invention relates to an integrated Memory circuit with a dynamic memory cell in which a Date should be written. The invention further relates to a method for writing a date in a memory cell integrated memory circuit.

A dynamic memory cell is common arranged on a word line and on a bit line. For reading out the word line of the content of the dynamic memory cell is activated, so that stored charge information on the bit line flows. A read amplifier assigned to the bit line amplifies one that is caused thereby Charge difference between the bit line on which the dynamic Memory cell is arranged, and a complementary adjacent Bit line. Before write access to the dynamic memory cell the word line is also activated, which leads to the fact that the readout amplifier assigned to the memory cell is activated, the Charge difference between the bit line and the complementary bit line reinforced and writes back to the dynamic memory cell. While writing one regarding of the previous date inverse date into the dynamic memory cell the reinforcement process of the readout amplifier be overcome by an appropriate write driver. That the The write driver must work against the amplification of the read amplifier and the corresponding information against this "resistance" into the memory cell write in. Should one of the original contents of the memory cell different date will be written into the memory cell first the process of pulling the charges apart on the bit line path counteracted the writing driver. After the charge difference has been reversed on the bit lines of the bit line pair, amplify readout amplifiers and Write driver the charge difference in the same direction.

So far, usually through simulations, the driver strengths the readout amplifier and optimized the write driver. The readout amplifier is dimensioned so that he's of sufficient strength has to do that quickly and safely in the dynamic memory cell read out the saved date. The write driver becomes dependent on the read amplifier dimensioned that it by a certain factor, e.g. four times, stronger is as the driver of the readout amplifier. The strength of the The write driver is selected in particular so that, on the one hand, the readout amplifier against it Driver power overwritten and on the other hand process-related or parasitic effects, such as. the crosstalk between the bit lines ("cross talk "), the leakage currents (" leakage "), the signal strength, the poor diffusion constants and other manufacturing fluctuations compensated can be.

Likewise, due to manufacturing fluctuations the driver strength the writer deteriorates, causing the readout amplifier no longer, or overwritten in a considerably longer time can be. Such effects can through longer Access times of the memory and overall in a worse Make memory circuit performance noticeable. In particular, must guaranteed that the setup and hold times of the data signal to be written for the Write process are sufficiently large that the write driver writes the date to be written against the gain of the readout amplifier can write to the bit lines. This results in the access time during writes into an integrated memory circuit.

It is an object of the present invention Memory circuit and a method for writing a date in A memory cell of a memory circuit is available ask, overwriting the charge difference on the bit lines with reduced access time or with reduced driver strength of the writer reliably he follows.

This task is accomplished through the integrated memory circuit according to claim 1, and by the method for writing a date solved in a memory cell according to claim 6.

Further advantageous configurations of the invention are in the dependent claims specified.

According to a first aspect of the present Invention is an integrated memory circuit with a dynamic Storage cell provided. The dynamic memory cell is on one Word line and arranged on a bit line. A readout amplifier is provided for reading out a date. The readout amplifier is on a first supply line for a first high supply potential and on a second supply line for a first low supply potential connected. The readout amplifier serves one on the bit line and a complementary bit line to strengthen existing charge difference. A data line and a complementary Data line are over a switching device with the bit line and the complementary bit line connectable to write a date by activating the Switching device according to a write signal a corresponding data signal to the bit line and a corresponding one complementary data signal to the complementary Bit line. A control device is also provided, around the first supply line when the switching device is activated from the first high supply potential and the second supply line from the first low supply potential to isolate the readout amplifier deactivate.

The integrated memory according to the invention Circuit has the advantage that when a data item is written to a dynamic memory cell, the readout amplifier is switched off or deactivated by separating the readout amplifier from the supply potentials. As a result, when the word line is activated before the write process, the potential difference on the bit line and on the complementary bit line caused by the charge information of the memory cell does not lead to a separation of the charge potentials of the bit lines, so that charge information can be driven more easily onto the bit lines during the write process. This is particularly significant when a charge information that is complementary to the charge information of the relevant memory cell is to be written into the memory cell. In this case, with an activated readout amplifier, the charge potentials on the bit lines would be pulled apart in one direction, the charge potentials of the bit lines having to be reached in the opposite direction in order to write the data into the memory cell. Therefore, the driver strength for writing the date must be chosen so large that the driver strength of the read-out amplifier is overcompensated. By deactivating the read-out amplifier by separating the read-out amplifier from the supply voltage, it is achieved that the driver strength when writing the data signal can be selected to be lower, since there is no need to drive against the function of the read-out amplifier. Alternatively, with the same driver strength, the hold time, ie the duration that the data signal must create for correct writing, can be reduced when writing.

The control device is preferably designed to be the first with an activated switching device Supply line of the readout amplifier with a second low Supply potential and the second supply line with one second high supply potential to connect to the readout amplifier deactivate. For no additional Supply potentials available to have to face the first high supply potential preferably corresponds to that second high supply potential or the first low supply potential the second low supply potential.

This represents a further improvement the integrated memory circuit, since the polarity reversal of the readout amplifier the readout amplifier faster can be deactivated by remaining on the supply lines Charges by the second high and the second low supply potential be dismantled quickly. After separating the read amplifier from The supply potential remains in the supply potential First of all on the supply lines so that the readout amplifier is still a certain time after disconnection from the supply potential at least partially able to work stays and during this time counteracts the writing of the date. As a result of that the first supply line with a second low supply potential connected, flows the charge existing on the first supply line, caused by the previously created first high supply potential is determined via the Potential source for the second low supply potential. Analog flows on the second supply line, whose charge through before the write process the first low supply potential is determined, the cargo corresponding to the potential source for the second high supply potential. In this way, the readout amplifier is essentially reversed, so that the transistors of the readout amplifier are completely deactivated in one State and no charge separation on the bit lines after activating the word line.

Furthermore, a charge compensation circuit be provided to charge potentials before writing the date equalize the bit line and the complementary bit line. The charge compensation circuit is coupled to the control device, around the first supply line when equalizing the charge potentials of the readout amplifier and the second supply line from the first high and the second to separate low supply potential. This meadow can on the one hand, the equalization of the charge potentials on the bit lines be accelerated because any existing charge differences are not caused by the readout amplifier reinforced become. On the other hand, by deactivating the read-out amplifier while of balancing the charges can be saved time to deactivate the readout amplifier needed becomes. This ensures that at the beginning of the writing process be that the readout amplifier is deactivated and is not reinforced against the date to be written.

The readout amplifier preferably has two mutually coupled inverter circuits, each of the Inverter circuits via the first and the second supply line with a supply voltage is supplied.

According to a further aspect of the present invention, a method for writing a date into a memory cell of an integrated memory circuit is provided. The memory cell is arranged on a word line and on a bit line. To read out the memory cell, a charge difference between the bit line and a complementary bit line is amplified by a readout amplifier. To operate the readout amplifier, a first high supply potential is applied to the readout amplifier to amplify the charge difference via a first supply line and a first low supply potential via a second supply line. To write the data, a corresponding data signal is sent to the bit line and a corresponding one mentary data signal applied to the complementary bit line. When the date is written, the first supply line of the readout amplifier is disconnected from the first high supply potential and / or the second supply line is disconnected from the first low supply potential in order to deactivate the readout amplifier.

The method according to the invention has the advantage that that to be driven on the bit line and the complementary bit line Data signal or complementary Data signal does not have to be driven against the readout amplifier, when the charge information to be written into the memory cell is complementary to the previously stored charge information.

Preferably when writing on the date of the first supply line of the read-out amplifier a second low supply potential and the second supply line applied to a second high supply potential to the potentials to reload the first and second supply lines so that the readout amplifier Completely is deactivated. By reloading the supply lines the charges there change more quickly so on the supply lines Apply potentials with which the readout amplifier is completely deactivated and none strengthen of charge differences. By reloading the deactivation of the readout amplifier Reached faster because after just disconnecting the read amplifier from the supply potentials on the supply lines a charge that remains the readout amplifier another one activated shortly after disconnection from the supply potentials holds.

Before writing the Date the charge potentials of the bit line and the complementary bit line balanced. When balancing the charge potentials, the first supply line of the readout amplifier and the second supply line from the first high and the first low supply potential Cut.

A preferred embodiment The invention will now be described with reference to the accompanying drawings explained in more detail. It demonstrate:

1 a circuit diagram of a section of an integrated memory circuit according to a preferred embodiment of the invention;

2a a signal diagram with a selection signal and an associated waveform of a bit line, which is to be written with a low signal level, in a conventional memory circuit;

2 B a waveform of the selection signal and the bit line signal in an integrated memory circuit according to a preferred embodiment of the invention;

3a a waveform of the selection signal and the bit line signal of a bit line to be written with a high signal level, as in a conventional memory circuit; and

3b a waveform of the selection signal and the bit line potential according to a preferred embodiment of the invention.

In 1 a circuit diagram of a section of an integrated memory circuit is shown. A pair of bit lines BLP can be seen with a first bit line BL1 and a complementary second bit line BL2. The bit line pair BLP is crossed by a word line WL, with a memory cell at an interface between the word line WL and the first bit line BL1 1 is arranged.

The memory cell 1 has a memory capacitance C, which is connected to the first bit line BL1 via a memory transistor T when a word line activation signal is applied to the word line WL. That is, when the word line WL is activated by the word line activation signal, the memory transistor T turns on, so that charge information of the memory capacitance C flows onto the first bit line BL1.

Usually are multiple word lines WL in integrated memory circuits and a plurality of bit line pairs BLP arranged in a field arrangement, so that a memory cell array is formed. Generally located at an interface between a word line and a Bit line pair only one memory cell, including memory cells can be arranged on the respective second bit line BL2. During a first connection of the storage capacity switchable with the first Bit line BL1 is connectable, there is a second connection of the storage capacity C. a fixed potential, preferably a center potential VBLEQ, that between a high and a low potential that at the first and the second bit line BL1, BL2 can occur.

The memory cell 1 is addressed by selecting the respective word line and the respective bit line pair BLP using a multiplexer device 2 is selected. The multiplexer device 2 is controlled using a multiplexer signal MUX. With the aid of the multiplexer signal MUX, the first and the second bit lines BL1, BL2 are connected to a section of the bit line pair which is a readout amplifier 3 , a charge balancing device 4 and a switching device 5 for connecting to external data signals for writing a date in the memory cell. The multiplexer device 2 has a multiplexer transistor for each of the bit lines BL1, BL2 6 on, which is switched through or blocked according to the multiplexer signal MUX.

The bit line pair BLP is still in the switched multiplexer device 2 the charge balancing device 4 with which the charge potentials on the first and second bit lines BL1, BL2 can be compensated. For this purpose there is preferably an equalizing transistor 7 is provided, which is connected between the first and the second bit lines BL1, BL2 such that they are compensated in accordance with a compensation signal EQ. The equalization of the charge potentials on the bit lines BL1, BL2 is necessary in order to compensate for the low charge information of the memory cell 1 , which leads to a small charge difference. For this reason, the charge potentials on the bit lines BL1, BL2 must be equalized before each reading of the charge information.

The charge balancing device 4 can be designed in different ways. The illustrated embodiment consists of a simple compensation transistor, which only compensates for the charges on the bit lines BL1, BL2 of the bit line pair BLP. Further embodiments are possible in which the bit lines can be brought to a defined center potential according to the equalization signal EQ.

A readout amplifier is still on the bit line pair BLP 3 provided, which is arranged between the first and second bit lines BL1, BL2 of the bit line pair BLP. The readout amplifier 3 has a first n-channel transistor 8th and a second n-channel transistor 9 on. The readout amplifier also has a first p-channel transistor 10 and a second p-channel transistor 11 , The first n-channel transistor 8th and the first p-channel transistor 10 are connected in such a way that they form a first inverter, the input of which connects to the first bit line BL1 and the output of which connects to the second bit line BL2. The second n-channel transistor 9 and the second p-channel transistor 11 form a second inverter, which is connected in the opposite direction with respect to the first inverter formed by the first n-channel and p-channel transistors, so that the second inverter is connected with its input to the second bit line BL2 and with its output to the first bit line BL1 ,

The first and second inverters thus formed are via a first supply line 12 and a second supply line 13 with a supply circuit 20 connected to operate it with a supply voltage. To the first supply line 12 is for the operation of the read amplifier 3 a first high supply potential VBLH is applied in accordance with a first control signal Pset1.

The first control signal Pset1 is "low" active and is connected to a gate input of a third p-channel transistor 14 the supply circuit 20 on. When a logic "0" of the first control signal Pset1 is present at the gate input of the third p-channel transistor 14 the first high supply potential VBLH is applied to the first supply line. The second supply line 13 is through a third n-channel transistor 15 connected to a first low supply potential VBLL. The third n-channel transistor 15 is switched according to a second control signal Nset1. The first and the second control signal Pset1, Nset1 are from a control unit 21 made available and switched so that to operate the read-out amplifier 3 the third p-channel transistor 14 and the third n-channel transistor 15 are switched through to the first and second supply lines 12 . 13 to create the respective supply potential.

The switching device 5 is used to apply data signals LDQ1, LDQ2 corresponding to a data to be written to the first bit line BL1 and the second bit line BL2 if the data to be written is to be written into the memory cell. For this purpose, switching transistors are used according to a selection signal CSL 16 switched through so that the corresponding data lines 17 can be connected to the corresponding bit lines BL1, BL2. Via the data lines 17 a read out date can also be read out after activating the selection signal CSL.

When writing a date in the memory cell 1 the addressed word line is activated so that the memory capacitance C is connected to the respective bit line. The data signals LDQ1, LDQ2 corresponding to the data to be written are essentially simultaneously on the data lines 17 provided. In order on the bit lines BL1, BL2 of the bit line pair BLP on which the memory cell to be written 1 is to bring to a defined state, the compensation device 4 activated, and using the equalization signal EQ equalizes the charge potentials on the bit lines. During the equalization, the addressed bit line pair BLP is over the multiplexer 2 switched through with the aid of the multiplexer signal MUX, so that the charge potentials on the bit lines BL1, BL2 can be equalized overall.

The one on the data lines 17 Data signals LDQ1, LDQ2 are now switched on by switching the switching transistors 16 applied to the corresponding first and second bit lines BL1, BL2, so that the resulting charge on the first bit line BL1 via the memory transistor T, which is switched on by an activated word line activation signal, into the memory capacitor C of the memory cell 1 is loaded.

The data amplifier can write the data signals on the bit lines BL1, BL2 3 be delayed if the charge potentials on the bit lines BL1, BL2 are not completely compensated 4 have been compensated and the date to be written is complementary to the previously saved date. In this case there is just before or during the switching of the switching device 5 a charge difference between the bit lines BL1, BL2 of the bit line pair BLP with opposite signs with respect to the data signals LDQ1, LDQ2 to be applied. Ie the read-out amplifier is switched on 3 tries the existing charge difference on the bit lines To increase BL1, BL2 without changing the sign of the charge difference. At the same time, an attempt is made to drive the data signals LDQ1, LDQ2 on the data lines 17 the attempt of the readout amplifier 3 to increase the charge difference, counteract it, and reverse the sign of the charge difference. This requires an adapted high driver strength on the data lines 17 for the data signals LDQ1, LDQ2.

In order to reduce the necessary driver strength for the data signals LDQ1, LDQ2, or to accelerate the time for writing the data signals LDQ1, LDQ2 to the bit lines BL1, BL2, the invention provides that the readout amplifier is deactivated when the date is written. This is done by using the first and second control signals Pset1, Nset1 the third p-channel transistor 14 and the third n-channel transistor 15 be blocked so that the first high supply potential VBLH and the first low supply potential VBLL from the first and second supply lines 12 . 13 be separated.

The supply lines are usually 12 . 13 for the readout amplifier 3 several readout amplifiers 3 connected for several bit line pairs BLP. The resulting long line lengths lead to a large capacity of the first and second supply lines 12 . 13 so that after disconnecting the supply lines 12 . 13 of the respective supply potentials VBLH, VBLL, the corresponding charge potentials on the supply lines 12 . 13 are initially maintained and only change their charge potential after a time determined by flowing charges. This means that the readout amplifier is not switched off immediately 3 , The readout amplifier 3 continues to work for a certain time after the supply potentials have been switched off and can thus counteract the data signals to be written on the bit lines BL1, BL2 for a certain time.

To completely deactivate the read-out amplifier 3 A fourth p-channel transistor can be reached within a short time 18 and a fourth n-channel transistor 19 intended. To a control input of a fourth n-channel transistor 19 is a third control signal Pset2 and to a control input of the fourth p-channel transistor 18 a fourth control signal Nset2 is applied. The third and fourth control signals are also made available by the control device. The fourth n-channel transistor 19 allows to the first supply line 12 with a second low supply potential, which preferably corresponds to the first low supply potential VBLL, after the third p-channel transistor has been switched off 14 according to the first control signal Pset1, rapid discharge of the first supply line 12 to achieve the low supply potential VBLL.

The fourth p-channel transistor becomes essentially simultaneously according to the fourth control signal Nset2 18 switched through so that the second supply line 13 is connected to a second high supply potential, which preferably corresponds to the first high supply potential VBLH. This causes the initially low charge potential of the second supply line 13 quickly drawn to the high supply potential.

This essentially means that the supply voltage at the readout amplifiers 3 is reversed so that they are deactivated as quickly as possible. Deactivation takes place considerably faster than with a mere disconnection of the supply potentials from the supply lines, since after the disconnection of the supply potentials there remain charge potentials on the supply lines 12 . 13 can be compensated quickly by reversing the polarity so that the read amplifier 3 can no longer carry out charge separation.

Since the data signals LDQ1, LDQ2 are not against the action of the readout amplifier when writing a date 3 must be driven on the bit lines BL1, BL2, it is possible to reduce the driver strength for driving the data signals LDQ1, LDQ2. Alternatively, if the driver strength is not changed, it is possible to reduce the length of time during which the data signals have to be present for writing to the bit lines BL1, BL2, since the readout amplifier is deactivated 3 a lower charge has to be driven onto the bit lines BL1, BL2. This enables the switching device 5 to be switched on for a shorter period of time in accordance with the selection signal CSL, so that the writing process can be accelerated overall.

In 2a 1 shows a signal curve of the selection signal CSL and the signal curve on one of the bit lines, which is to be pulled to a low potential with the aid of the data signal, for a conventional memory circuit. The selection signal CSL is shown in dashed lines and was varied for a variable time period between one and three nanoseconds. In the case of the charge potential on the bit line shown as a continuous line, it can be seen that if the selection signal is too short, the bit line potential cannot be reliably pulled to a low potential, but rather to a high potential, since the activated readout amplifier 3 could not be overwritten by the driven data signals. In 2 B the same simulation is shown if before switching on or simultaneously with switching on the switching device 5 the supply lines according to the selection signal CSL 12 . 13 of the readout amplifier 3 have been separated from the respective potential sources. It can be seen that, even with the short selection signals, the respective data signal is reliably written to the corresponding bit line, for which a date to be written beforehand could not be written successfully.

In 3a is analogous to 2a shown that for the complementary bit line, the high potential is not reached in a conventional memory circuit if the selection signal CSL is present for too short a period of time. In 3b it is shown that the high potential on the complementary bit line is achieved even with very short selection signals CSL if the readout amplifier 3 is deactivated when switching through the switching device.

The first and second control signals Pset1, Nset1 are preferably controlled such that the third p-channel transistor 14 and the third n-channel transistor 15 be locked while the charge balancing device 4 is activated in order to equalize the charge potentials on the bit lines BL1, BL2. Only after deactivating the charge balancing device 4 the third and fourth control signals Pset2, Nset2 are then controlled so that the fourth n-channel transistor 19 and the fourth p-channel transistor 18 be switched through to the charge potentials on the first and the second supply line 12 . 13 tranship. Because essentially immediately after deactivating the compensation device 4 by the equalizing signal EQ the switching device 5 is switched through to apply the charge signals LDQ1, LDQ2 to the bit lines, the switching device is switched through 5 essentially simultaneously with the reloading of the first and second supply lines 12 . 13 ,

1

memory cell

2

multiplexer

3

sense amplifier

4

Load balancer

5

switching device

6

multiplexer transistor

7

equalizing transistor

8th

first N-channel transistor

9

second N-channel transistor

10

first P-channel transistor

11

second P-channel transistor

12

First supply line

13

Second supply line

14

third p-Kanaltransitor

15

third N-channel transistor

16

switching transistors

17

data lines

18

fourth P-channel transistor

19

fourth N-channel transistor

20

supply circuit

21

control unit

WL

wordline

BL1, BL2

 first, second bit line

BLP

bit line

T

memory transistor

C

memory

EQ

equalization signal

MUX

multiplexer signal

CSL

select signal

LDQ1, LDQ2

 data signals

VBLH

high supply potential

VBLL

low supply potential

set pset1

first control signal

Nset1

second control signal

pset2

third control signal

Nset2

fourth control signal

Claims (8)

Integrated memory circuit with a dynamic memory cell ( 1 ), which is arranged on a word line (WL) and a bit line (BL1), a readout amplifier ( 3 ) connected to a first supply line ( 12 ) for a first high supply potential and on a second supply line ( 13 ) is connected for a first low supply potential, is provided in order to amplify a charge difference existing on the bit line (BL1) and a complementary bit line (BL2), a data line ( 17 ) and a complementary data line ( 17 ) via a switching device ( 5 ) can be connected to the bit line (BL1) and the complementary bit line (BL2) in order to write a datum by activating the switching device ( 5 ) according to a write signal, a corresponding data signal (LDQ1) to the bit line (BL1) and a corresponding complementary data signal (LDQ2) to the complementary bit line (BL2), characterized in that a control device ( 21 ) is provided so that when the switching device is activated ( 5 ) the first supply line ( 12 ) from the first high supply potential ( 13 ) and separate the second supply line from the first low supply potential in order to remove the readout amplifier ( 3 ) to deactivate. Integrated memory circuit according to Claim 1, characterized in that the control device ( 21 ) is designed so that with an activated switching device ( 5 ) the first supply line ( 12 ) of the readout amplifier ( 3 ) with a second low supply potential and the second supply line ( 13 ) with a second high supply potential to connect the readout amplifier ( 3 ) to deactivate. Memory circuit according to claim 2, characterized in that the first high supply potential to the second high supply potential and / or the first low supply potential the second low supply potential equivalent. Memory circuit according to one of claims 1 to 3, characterized in that a charge compensation circuit ( 4 ) is provided to equalize the charge potentials of the bit line (BL1) and the complementary bit line (BL2) before the date is written, the charge equalization circuit ( 4 ) with the control device ( 21 ) is coupled to the first supply line (when equalizing the charge potentials) 12 ) of the readout amplifier ( 3 ) and the second supply line ( 13 ) from the first high and the second low supply potential. Memory circuit according to one of Claims 1 to 4, characterized in that the read-out amplifier ( 3 ) has two mutually coupled inverter circuits, each of the inverter circuits via the first and the second supply line ( 12 . 13 ) is supplied. Method for writing a date in a memory cell ( 1 ) an integrated memory circuit, the memory cell ( 1 ) is arranged on a word line (WL) and a bit line (BL1), whereby for reading out the memory cell ( 1 ) a charge difference between the bit line (BL1) and a complementary bit line (BL2) due to a readout amplifier ( 3 ) is amplified, whereby to operate the read-out amplifier ( 3 ) a first high supply potential via a first supply line to amplify the charge difference ( 12 ) and a first low supply potential via a second supply line ( 13 ) to the readout amplifier ( 3 ) is created, with a corresponding data signal being applied to the bit line (BL1) and a corresponding complementary data signal being applied to the complementary bit line (BL2) for writing the date, characterized in that when the date is written the first supply line ( 12 ) of the readout amplifier ( 3 ) is separated from the first high supply potential and the second supply line from the first low supply potential to the readout amplifier ( 3 ) to deactivate. A method according to claim 6, characterized in that when writing the date, the first supply line ( 12 ) of the readout amplifier ( 3 ) to a second low supply potential and the second supply line ( 13 ) is applied to a second high supply potential in order to use the potentials of the first and the second supply line ( 13 ) so that the readout amplifier ( 3 ) is completely deactivated. A method according to claim 7, characterized in that the charge potentials of the bit line (BL1) and the complementary bit line (BL2) are equalized before writing the date, the first supply line ( 12 ) of the readout amplifier ( 3 ) and the second supply line ( 13 ) are separated from the first high and the first low supply potential.