DE1031366B - Circuit arrangement for evaluating n different potentials, in particular for digit identification, in systems of communication technology - Google Patents

Description

In systems of communication technology there is often the task of defining certain identifiers in larger number from a numeric transmitter to a memory or from a memory to a dial set transferred to. When choosing a keyboard, to give an example, they are implemented by pressing a key Transfer potentials that represent the selected digits from the keyboard to a register and save. Only a few transmission lines are typically available for such transmissions.

It is known to save as many labels as possible over a single one in order to save transmission lines Transfer line. For this are z. B. when transmitting sixteen license plates over two Lines per line require four different potentials, which transmit combined accordingly will.

The invention is now based on the object of enabling the transmission of as many identifiers as possible, which are present in the form of certain different potentials, via a single line. A receiving circuit should be brought into different states by the transmitted potentials, so that these states represent a statement as to which particular potential of η possible potentials was transmitted.

This object is achieved with the aid of a circuit arrangement for evaluating η different potentials according to the invention in that n-1 transistors are provided which are connected to different DC voltages, the control electrodes of which are connected to a common transmission line carrying the different potentials and corresponding to their different reference voltages can only be controlled by certain potentials in their permeability range, and that depending on a certain number of permeable transistors, the effect of this modulation for certain transistors is canceled again in such a way that the transistors remaining in the permeability state represent the evaluation indicator for the potential in question.

The invention is explained in more detail with reference to the exemplary embodiments in FIGS. 1 to 4, specifically showing

1 shows an evaluation circuit according to the invention for η different potentials with directional conductors for changing the comparison voltage at each transistor,

Fig. 2 shows an evaluation circuit with auxiliary transistors to change the different equivalent stress,

3 shows a circuit arrangement according to the invention for evaluating ten different potentials

Circuit arrangement for evaluation
of η different potentials,
in particular for the identification of digits,
in systems of communication technology

Applicant:

Siemens & Halske Aktiengesellschaft,

Berlin and Munich,
Munich 2, Witteisbacherplatz 2

Heinrich Ubelhack, Munich,

Dipl.-Ing. Peter Gerke, Munich-SoUn,

and Dipl.-Ing. Otto Kneisel,

Großhesselohe near Munich,

have been named as inventors

tial · in the form of a binary code, with the evaluation the modulation is partially reversed by coincidence,

FIG. 4 shows a circuit corresponding to FIG. 3 below

Use of two-stage transistor amplifiers.

In Fig. 1, n-1 transistors T1, T2, T3 to Tm-I are provided for evaluating η different potentials. These transistors are with their control electrodes, here with the respective base, via limiting resistors Wl, W2, W 3 to Wn-I, on which the different potentials leading transmission line L. Each emitter of the transistors Tl, T2, T 3 to Tm-I is to the tap of a voltage divider consisting of the resistors Ria and RIb, R2a and R2b, R3a and R3b ... Rna-1 and Rnb-1 attached. To achieve a greater gain, the collectors of the transistors Tl, T2, T3 to Tw-I are connected to the base of a further transistor amplifier stage TIl, T12, T13 to Tw-I via a coupling resistor RKl, RK2, RK 3, RKn-I. In the output circuit of these further amplifier stages there is

the evaluation relays Al, A2, A3 to An-I. The voltage dividers relevant for the generation of the different comparison voltages of the individual evaluation transistors Tl, T2, T 3 to Tn-I are z. B. between earth and the office battery voltage.

809 529/177

3 4

It is an advantage of the circuit L according to the invention that the line resistance RL can be produced in an excessive manner. In the exemplary embodiment, the transmission line L can be high, since the transmission circuit according to FIG. 1, the different lines are always only loaded by one transistor or short-term potentials at a voltage divider from the resistors 5 through two transistors, Sp 1 would be , Sp2, Sp3 to Spn-1 via contacts A1, It is tapped in the circuit according to the invention k2, k3, kn-1. The contacts k 1, k2, k $. .. for the example that the third potential can be transmitted kn-1 , for example through a keyboard or, the following:

can also be operated via relays. The third potential runs through as a result of the cable um now an influencing of the capacitance at the taps io initially that for modulation in the through-

the voltage divider of the transistors T1, T2, T 3 to the permeability range of the first transistor sufficient

Tm-I lying different comparison voltage-first potential and then also in the same

gen depending on a certain number in way the second potential. This will make the two of them

To allow their permeability range of controlled trans transistors T1 and T2 in their permeability are controlled in the 15 range according to the invention, but the transistor Π is

Circuit directional conductor Gl, G 2 ... to Gn as well as rectifying from the output of the second evaluation stage over

Head of GR2, GR3. . . etc. provided. the director Gl immediately blocked again. Through this

With the help of this directional ladder works the invention blocking is relieved of the voltage divider, since the

according to receiving circuit now as follows: transistor Tl now no more control current-It is assumed that the first takes when closing 20, and it can now the transistor T3 in his

of the contact k 1 via the line L transmitted permeability range can be controlled. In order to

The potential for modulating the first transistor Tl is, however, at the same time again over the transistor T2

Sufficient in its permeability range, while the directional guide G 2 is blocked. The momentary opening

the second potential for modulating the first two transistors T1 and T2 does not matter, since the

the transistors T1, T2 in their permeability 25 response time of the relays A1, A2 , etc. are larger anyway

area is sufficient, etc. The directional director G 1 connects.

Now the tap of the voltage divider of the first tran- With electronic evaluation at the output of the transistor T1 with the collector of the transistor T12, transistors T11, T12, T13 ... it is possibly which is the output of the second evaluation stage. It is necessary to provide timing elements that have an off. Here, under the evaluation stage, each transi- 3 ° control of said transistors TIl, T12 ... storpaar Tl, TIl; T2, T12, etc. can be understood. for the time during which the transistors In the same way, the directional conductor G 2 connects the T1, T2 etc. are briefly permeable. Tapping of the voltage divider of the transistor T 2 with In the event that the transmission arrangement for the output of the third evaluation stage T 3, T13. different potentials in a different remote If, for example, the third potential is now arranged over the reporting office than the one according to the invention, which is of sufficient size for the receiving circuit, it may be useful to put the first three transistors T1, T2, T3 in If measures are taken to control the operating voltage of its permeability range, the receiver circuit ensures that the above-mentioned directional conductor G1, G 2 and the directional conductor voltage use the comparison GR 2 described above to ensure that the comparison voltage for the first 40 voltages via the voltage divider between the two transistors is changed in such a way that the states j? I a, Rib, R2a, R2b. . . are derived, the next controlled transistors T1, T2 are again. If the transmitter and receiver are in separate offices, they are blocked. This happens e.g. For example, for the transistor, opposing voltage fluctuations, which here is a transistor of the NPN type, can occur in relation to the official batteries Missing soon for the modulation in the permeability evaluations can lead. In order to avoid such an error area of the transistor T1 a little more negative than the evaluations, according to an advantageous potential at the base of the transistor Tl, a control element adhering to the invention is raised far so that the potential at the emitter here is the control transistor amplifier RT is somewhat more positive in the collector than at the base, so that the tran- 50 circuit is provided. The base of the control transistor sistorTl is blocked, that is, no current RT flows via a further line & Signalspanmehr to the collector of the transistor Tl the operating voltages in the transmitter depend on the voltage divider from which the resistors Ria are. Thus, the control transistor RT is overall in such a way and Rib is thereby controls more positive than the potential at 55, that at its emitter to the base connected to the transistor Tl that in modulation voltage divider comprising resistors Ria, Rib, of the transistor T2 and the transistor T12 through- R2a, R2b ... which is the equivalent stresses for the casual. This sets the potential that is now transistors T1, T2 ... supply, on an operating at the collector of the transistor T12, over the voltage that changes in the same direction as the voltage directional conductor G1 also at the tap of the said span 60 fluctuations in the transmitter, whereby this voltage divider by. The directional conductors GR2, GR3 are compensated for voltage fluctuations, at the same time preventing a reaction from the The arrangement of such a control transistor RT output of the evaluation stage concerned has the advantage that only a branch's own comparison voltage and the comparator control current over the line b is to be delivered, while for the voltage of the following evaluation levels. With the help of 65 supply of the receiver required current from this evaluation circuit according to the invention, it is supplied to the office battery of the recipient location, ensuring that only one relay A 1, A 2, etc., in Fig. 2 are also underexcited to evaluate the. The status of the evaluation relay represents different potentials on the line L transistors so a direct evaluation indicator for the relevant Tl, T2 to Tm-I via the resistors Wl, W2 to fende transmitted potential. 70 Wn-I connected. Also the voltage dividers that

5 6

the different equivalent voltages for the len are when the third, fourth and

individual transistors T1, T2 ... supply are in fifth potential. The transistor Γ2 contributes

in the same way from the resistors Rla and RIb, its modulation in the permeability range

R2α and R2b as well as Rna-1 and Rnb-1 are built up. The via the resistor K2 and the directional conductor GL2 the

different potentials are measured here via pressure 5 second evaluation device £ 2. In the same way

keys oil, D2, DZ ... at resistors RP1, RP2, the transistor T 3 acts through the resistor K 3

RP 3 ... RPn-I tapped, with a span, the evaluation device £ 3, and the transistor

voltage division between the comparison resistor RV Ti controls the evaluation input via the resistor Kl

and the resistor RPl just switched on, direction El ·, d. i.e., when transferring the fifth potential

RP 2 ... sets. In the collector circuits of the tran- iotials, all four evaluation devices £ 1 to

sistorenTl, Γ2 etc. the evaluation £ 4 are also activated here,

Relays A1, A2 to An-I provided. If now the sixth potential is transferred,

In order to influence the comparison voltages at which this would be sufficient in its size to make the taps of the mentioned voltage dividers of the first transistors T1 to T5 permeable, so up to the penultimate transistor are now, according to another 15, the reversing transistor UT1 ensures that the Further embodiment of the invention auxiliary transistors caused by the transistor Tl modulation of the THl, TH2 ... provided, which is prevented depending on the evaluation device £ 1 by controlling the modulation of the next following transistor in transistor UTl from the collector of transistor T 5 to their permeability range forth is made conductive and thus the collector and thus the resistor Ria or R2a etc. no longer bridge overcurrent of the transistor T1 for activation, so that the associated transistor T1, T2. . . the evaluation device £ 1 is sufficient, since it is consequently blocked via the transistor UT1, which has its emitter and is conductive and therefore low-resistance. For example, when that drains. As a result, when the second potential is transmitted, which in itself would only reach the evaluation devices from the sixth potential, both the transistor T1 and the 25 E2, E3 and El device £ 1 is not operated,
In the same way, the reversing transistors act to make the transistor TH 1 permeable and thus UT2 and UT3, and that ensures the transmission of the potential through this potential when the transistor Tl is transmitted by bridging the voltage Line dividing resistor blocked again, so that only ₃₀ tend made transistor T 6 can respond by modulating the evaluation relay A 2. Similarly Umsteuertransistors UT2 in its permeability, the blockage of additional transistors T 3 takes place, area for the fact that the transistor T2, the evaluation Tl · etc. The isolator D prevents retroactive means 2 £ can not change course. This means that the output of the transistor T2 acts on its own, i.e. when the seventh potential is transferred, a single comparison voltage. 35 Hch the evaluation devices £ 3 and El · activated.

Fig. 3 shows an embodiment according to the invention. When the eighth potential is transmitted, which makes the transmission for evaluating ten different transistor T 7 conductive, the reversing transistor potentials in the form of a binary code. The ten different potentials generated by the transistor T7 with different permeability are controlled in the range, and the transistor CTT3 is transmitted over the line L , and the individual 40 changes so that the transistor T 3 controls the evaluation transistors T1, T2. .. are activated in the same way as direction £ 3. When transferring the eighth it was described with reference to FIGS. 1 and 2, only the evaluation device is consequently switched on. Accordingly, the transistors Tl through the device El · are activated via the transistor T4. This ver-T9 via resistors Wl to W9 with their control prevent the transistors T5, T6, T7 with the help of the electrodes, here with the base, on the transmission 45 reversing transistors UTl, UT2, UT 3, the over line L and with their emitter at individual base resistors Bl, B 2, 53 at a certain voltage divider Λ1 to St 9, which are for each transi bias voltage, the modulation of the relevant gate Tl to T9 each deliver a certain comparison voltage to the evaluation device through the transistors Tl. The order of figuring the Transi- T2, T 3.

disturb T1 to T9 was carried out in Fig. 3 so, 50 On the other hand, the control of the first two is that the numbering a certain subdivision of the evaluation devices £ 1 and £ 2 can be recognized through the Transiser nine transit gates in four groups. disturb T 8 or T9 when transmitting the ninth or the group I summarizes the transistors Tl, T5 and T8 of the tenth potential regardless of the state of the together. Group II contains the transistors T2, T6 reversing transistors UT1 and UT2, respectively. This is da- and T 9, while group III, the transistors T3 and 55 achieved by that contains the ninth potential in T7. In group IV there is only the transi-transistor Tl · controlled by its permeability range. Each of the four groups is assigned an ejector T8 via the coupling resistor K8 to the evaluation device £ 1, £ 2, £ 3, El · . This facility £ 1 can directly affect. Likewise, evaluation devices are only shown as boxes of the transistors that can be controlled by the tenth potential, since they are known flip-flops, can interfere with the evaluation relay or the like via the coupling resistor K 9. affect facility £ 2 directly. The judges

The circuit according to the invention now works as follows: GL1 and GL2 are used to decouple the transgenders: When the first potential is transmitted, T 8 and T9 from the collector interfere with the reversing transition, none of the transistors T1 to T9 in its transistors UT1 or UT2. This allows the transi-permeability range to be controlled. The second 65 interfering T 8 or T 9 regardless of the state of the Tran potential controls the transistor Tl in its transistors UT1 and UT2 on the evaluation device permeability range, and thus the via the £ 1 or £ 2 will act. The resistors K1 to K9, resistor K 1 and the directional conductor GL1 with the are coupling resistors.

Evaluation unit connected to the collector of the transistor Tl. The switching device according to the invention shown in FIG. 4 £ 1 actuated. The same processes work in the same way as it does for the circuit.

described processing of FIG. 3, but the transistors Tl to TS to are each connected to a further transistor amplifier stage TVL to TV 9 here. All transistors T1 to T9 are again divided into four groups, namely group I includes transistors T1, TS and T 8 with the associated amplifier transistors TV1, TV 5, TV 8. Correspondingly, group II includes transistors T 2, T 6 and T 9 together with the amplifier transistors TV2, TVQ, TV9 . Group III contains the transistors T 3 and T 7 with their amplifier transistors TV 3, TV 7 . Group IV is represented solely by transistor T 4 with its amplifier transistor TV 4 : . The transistors Tl to T9 are located on individual voltage dividers STl to ST 9, which provide the different reference voltages, and are coupled via resistors WKL to WK9 to the control electrode, here with the base, of the associated amplifier transistors TVL to TV. 9 The amplifier transistors are above base resistors WBl WB to 9 at a certain bias.

The reference to FIG. 3 for the Umsteuertransistoren UTL, UT2 and UT-described functions 3 are in the circuit of Fig. 4 by the amplifier transistor TV 5 in the group I, through the amplifying transistor TV 6 in the Gruppell and through the amplifying transistor TV7 in of group III carried out. In group I, the amplifier transistor TV 5 prevents the evaluation device E1 from being activated by the transistor TV1 when the sixth potential is transmitted, in that the collector current of the transistor T1 is diverted via the amplifier transistor TV5, which is made conductive when the sixth potential is transmitted and is therefore low-impedance , ie, the amplifier transistor TV5 blocks the amplifier transistor TV1. The transistors TV 6 and TV7 act in the same way. Caused in the circuit of Fig. 3 through the isolator Gl 1 and G12, decoupling of the collector of the transistors T 8 and T 9 of the koi lecturer of the conductive transistors UTL and UT2 is in the circuit of Fig. 4 by the transistors TVL and TV 2 is effected by these transistors as blocking elements between the collector of the transistor TV8 or TV9 and the collector of the transistor TV 5 or TV6 . The circuit arrangement according to FIG. 4 thus works in the same way as the circuit according to FIG. 3. When the potentials 1 to 5 are transmitted, the evaluation devices E 1 to E 4 are controlled. When the sixth potential is transmitted, the amplifier transistor TVS prevents the evaluation device E1 from being modulated. When transferring the seventh potential of the amplifier transistor TV 6 prevents the modulation of the device E2, and transmission of the eighth potential of the amplifier transistor TV 7 prevents the modulation of the evaluation device E 3. The amplifier transistors TV 8 and TV9 the devices E1 and E2 may independently from Control the conductive state of the amplifier transistors TVS or TV 6.

With a corresponding change in the potential ratios, the described inventive Circuits also use transistors of the respective complementary type.

The control circuit with the transistor RT described with reference to FIG. 1 can also be used analogously to control the operating voltage in the circuits according to FIGS. In FIG. 2, the same voltage dividers consisting of the resistors Ria, RIb, R2a, R2b . In FIGS. 3 and 4, the corresponding voltage components StI, St 2 ... were also to be connected to the emitter of the regulating transistor, as described.

Claims (8)

Claim ii 1. Circuit arrangement for evaluating η different potentials, in particular for ZifFernkennzeichen, in systems of communication technology, characterized in that MI transistors are provided which are at different reference voltages and which have their control electrodes on a common transmission line carrying the different potentials and according to their different ones Comparison voltage can only be controlled by certain potentials in their permeability range, and that, depending on a certain number of permeable transistors, the effect of this modulation for certain transistors is canceled again in such a way that the transistors remaining in the permeability state represent the evaluation indicator of the relevant potential. 2. Circuit arrangement according to claim 1, characterized in that for evaluating the η potentials Ji-1 transistors (Tl, T2 ... Tn-I) are provided in an emitter circuit, the bases of which are connected to the transmission line (L) and their emitters to different voltage dividers (Ria, RIb, R2a, R2b ... ) which supply the different reference voltages, which are made dependent on the modulation of the following transistor for the first to the penultimate transistor in such a way that the last in the series of those modulated in the permeability range Transistors cancels the conduction state of all preceding transistors by changing the comparison voltage at the voltage divider of the preceding transistors, in such a way that only one specific transistor is conductive for each potential. 3. Circuit arrangement according to claim 2, characterized in that the taps of the voltage divider of the first to penultimate transistor via directional conductors (Gl, G2 ... GR2, GR3...) Are connected to the outputs of all subsequent transistors in such a way that the last one in the row of transistors controlled in the permeability range via said directional conductor influences the comparison voltages of the preceding transistors in such a way that the permeability state is canceled again. 4. Circuit arrangement according to claim 2, characterized in that in each case a resistor (Ria, R2a ...) of the voltage divider of the first to penultimate transistor by an auxiliary transistor (THl, TH2 ... ) Which can be controlled as a function of the modulation of the respective following transistor. can be bridged and thus the comparison voltage of the first to penultimate transistor (Tl, T2... ) can be changed. 5. Circuit arrangement according to claim 1, characterized in that for the evaluation of ten different potentials in the form of a binary code, nine transistors (Tl, T2 ... ) Located at different comparison voltages in four groups (I, II, III, IV) are subdivided, the four evaluation devices (£ 1, E2, EZ _} £ 4) control, and that one specific transistor (T5, T6, T 7) of the first three groups each Reversing transistor (UTl, UT 2, UT3) is assigned, which prevents the modulation of the evaluation device in question, which can be effected by the transistors (Tl, TZ ₁ TS) , when the relevant reversing transistor (UTl, UT2, UTZ) is replaced by the associated transistor (T 5, T 6, TT) is activated, while the control of the first two evaluation devices by a further transistor (T 8, T9) of the first two groups (I, II) is independent of the state of the reversing transistor (UTl, UT2) , such that the associated evaluation device is only actuated at certain potentials and thus the respective state of all evaluation devices represents a statement as to which potential level is being evaluated. 6. Circuit arrangement according to claim 5, characterized in that each of the nine transistors (Tl, T2 ...) Controls an amplifier transistor (TVl, TV2... ) And the transistors in such a way to four groups (I, II, III, IV) , which control four evaluation devices, are summarized that in the first three groups one of the amplifier transistors (TV 5, TV 6, TV 7) prevents the control of the evaluation devices caused by the transistors (TV1, TV2, TVZ) if the relevant amplifier transistor ( TV 5, TV 6, TVT) is activated by the associated transistor (T5, T 6, TT) , while another amplifier transistor (TV 8, TV 9) in the first two groups controls the evaluation device in question regardless of the state of the first-mentioned amplifier transistors (TVS , TV6, TV 7) . 7. Circuit arrangement according to one of claims 1 to 6, characterized in that voltage fluctuations that arise at the transmission location of the different potentials are reported to the receiving location via a dedicated transmission line (b) and evaluated by a control element, preferably a transistor amplifier (RT) in a collector circuit are, in such a way that the operating voltages of the receiver, in particular the voltage from which the comparison voltages for the individual transistors (Tl, T2. 8. Circuit arrangement according to claim 7, characterized in that two or more transistor amplifiers are provided in a compound circuit to compensate for the voltage fluctuations occurring in the transmitter at the receiving location. For this purpose 2 sheets of drawings @ 809 529/177 5.58