DE10301496A1 - Semiconducting arrangement with p- and n-channel transistors has transistors with drift paths with at least one region of opposite type to channel types and complementary symmetry in drift paths - Google Patents

Abstract

The invention relates to a p / n channel pair, in which both transistors (22, 21) are manufactured with the same structure by means of a mask (M) by introducing compensation areas (5, 3 ').

Description

The present invention relates to a semiconductor arrangement comprising at least one first transistor with a channel of one conduction type and at least a second one Transistor with one channel of the other, on the one hand opposite type of conduction Conductivity type. The two transistors can, for example, in one Semiconductor body (Semiconductor chip) with a semiconductor substrate of the other conductivity type and a semiconductor layer of one conductivity type arranged thereon be provided. The transistors are preferably Field effect transistors, in particular MOS transistors. In addition, the present refers Invention on a method for producing such a semiconductor device and a mask for that.

In power electronics currently transistors with channels of different line types, so-called p / n-channel pairs either two housed Semiconductor chips, that is, from two separate semiconductor chips, each with a housing, or from two semiconductor chips in one housing or also monolithic manufactured integrated. The monolithic integration continues a complex technology ahead so that the integrated formed by the p / n channel pair Circuit is high voltage compatible. The most common use is currently two separate transistors on one semiconductor chip each in a housing, since this is the cheapest solution to form a p / n channel pair.

P / n channel pairs, for example in half-bridge applications and used here in particular in lamp ballast applications. The monolithic integration of such a p / n channel pair with reasonable effort would be here not least as a result of the space savings of great Advantage. That would be it is particularly useful if for such p / n-channel pairs a structure and a layout can be chosen could that if possible same masks and individual processes for both transistors of the pair would be applicable.

It is therefore the task of the present Invention to provide a semiconductor device with a p / n channel pair that is structured in such a way that its two transistors are as possible same masks and individual processes in a relatively simple way monolithic can be manufactured integrated; also should a method for producing such a semiconductor device and a mask can be specified, the simple manufacture of the semiconductor device allowed.

This task is accomplished with a semiconductor device of the type mentioned according to the invention by the in the characterizing Part of claim 1 specified features solved.

An advantageous method of making the Semiconductor arrangement is the subject of claim 25. A practical mask for the production of the semiconductor arrangement according to the invention is in Claim 26 specified.

Advantageous further developments of Invention result from the subclaims.

The monolithic integration of a p / n channel pair according to the invention offers first the main advantage of being able to use standard housings in which only houses a semiconductor chip ("single die attach"). Back end lines with such a single the attachments are in contrast to the placement of two semiconductor chips in one housing ("dual die attach") due to their far-reaching automation much cheaper as the latter.

A disadvantage of a monolithic Integration of a p / n channel pair but so far that is for one p-channel transistor and an n-channel transistor different Basic materials are required, what in lateral and vertical Structures with drain leading to the top of the semiconductor chip are numerous different masks and individual processes are required.

It is precisely this last difficulty mentioned overcome by the invention, by using a preferably lateral compensation concept Application in which compensation areas are designed so that these are complementarily symmetrical in the semiconductor layer are. This is to be understood as, for example, an n-type Semiconductor layer embedded to form an n-channel transistor and regions to form a p-channel transistor Areas that leave embedded areas of the n-type layer, be introduced. The embedded areas are preferred each island-like and in particular columnar.

The invention is explained below the drawings closer explained. Show it:

1 3 shows a sectional illustration through an n / p-channel pair according to a first exemplary embodiment of the invention,

2 a schematic for the n / p channel pair of 1 .

3 2 shows a detailed representation to further explain an advantageous embodiment of the first exemplary embodiment of the invention,

4 a top view of the n / p channel pair of 1 in an advantageous variant,

5a and 5b schematic representations for explaining a further embodiment of the invention in plan view,

6a and 6b schematic sectional views for explaining another embodiment example of the invention, and

7a and 7b schematic plan views for explaining a further embodiment of the invention.

The semiconductor material used in the semiconductor device according to the invention preferably silicon used. The invention is in the same way but also with other semiconductor materials, such as SiC, compound semiconductors etc. applicable.

Furthermore, in the following embodiments Of course the specified line types, ie "n" and "p", are exchanged.

1 shows a schematic sectional view of a semiconductor chip with a p ^- -silicon substrate 2 , on which an n- (or n ^- -) silicon layer 3 is applied. The layer 3 can be generated, for example, by epitaxy. The substrate 2 is at his to shift 3 opposite surface with a backside metallization 4 made of aluminum, for example. To achieve an ohmic connection, it is possible in the surface area of the substrate 2 ap ⁺ conductive contact zone 1 be introduced, for example, by internal implantation. The backside metallization 4 can be soldered to a lead frame (not shown) or mounted with a conductive adhesive or bonded to ground by bonding to an assembly island. The metallization is in the illustrated embodiment 4 - as shown schematically - to ground potential.

It is essential to the present invention that the n-type layer 3 for example by masked implantation and subsequent diffusion (temperature treatment) of p-type regions 5 . 8th . 14 is structured such that it can perform at least two, but preferably three, different functions in different areas of the semiconductor chip. Instead of a masked implantation and diffusion, another doping method can optionally be used.

In the 1 is an n-channel transistor on the left 22 shown while the right side is a p-channel transistor 21 shows.

The drift distance of the n-channel transistor 22 has a grid-like shape. For this purpose, for example, hexagonal or square or strip-shaped or otherwise structured p-type regions 5 into an n-type matrix of the layer 3 embedded. The layer 3 here represents a continuous, uninterrupted current path from a source zone 9 through one in a p-type tub 15 formed channel to an n-type drain zone 7 in an n-type tub 11 to disposal. The p-type regions serve here 5 , which are island-like and preferably columnar in the n ^- -conducting layer 3 are embedded, for charge compensation and thus allow a significantly higher doping of the n-type layer according to the principles of the compensation principle 3 , Connecting the areas 5 takes place over the conductive substrate 2 , the contact zone 1 and the backside metallization 4 ,

The tub 11 can have an opening in polycrystalline silicon that is above the surface of the layer 3 is provided in an insulating layer also having an opening, self-aligned in the layer 3 be introduced. The tub can 11 Be dimensioned in width so that the space charge zone, which is in the layer 3 spreads, not to the drain zone 7 reaches through and is gently stopped by a gradually increasing doping. That is, the drain zone 7 is more heavily endowed than the tub 11 , and the tub 11 in turn is again more heavily endowed than the layer 3 ,

On the right side of the 1 on which a p-channel transistor 21 shown remain from the layer 3 only columnar n-type areas 3 ' that here in a lattice-shaped p-type area 14 embedded, which is a continuous current path from an n-type source zone 10 over an n-type trough 12 , the p-type regions 14 to a p-type tub 15A and a p-type drain zone 13 provides.

In an edge termination between the n-channel transistor 22 (left side of 1 ) and the p-channel transistor 21 (right side of 1 ) and especially between the source zones 9 and 10 an edge termination of the two transistors can be formed by the n-type layer 3 for example structured so that the width of the remaining areas of the layer 3 and the width of p-type regions 8th is significantly reduced in each case. This reduction can be up to half the width of the areas, for example 5 respectively. 14 amount, so that here there is half the width of the drift zone areas. By means of these areas 8th with the remaining areas of the layer in between 3 a quasi intrinsic net doping can be achieved by diffusing them together, which is particularly advantageous for the dielectric strength of the edge termination.

The structuring and doping of the p-type regions 5 . 8th . 14 can be carried out in a particularly advantageous manner with the aid of a single mask M, such as this in the lower part of FIG 1 is shown schematically. Here openings correspond 5A . 8A and 14A in the mask M the areas 5 . 8th and 14 , That is, through these openings 5A . 8A and 14A become the endowments for the formation of the areas 5 . 8th and 14 for example by implantation.

Since in the semiconductor arrangement according to the invention both the p-channel transistor 21 (right half of 1 ) as well as the n-channel transistor 22 (left half of 1 ) with their doping concentrations should be close to an ideal compensation of n-doping and p-doping, there is a layout in which, after the diffusion sion from the implanted areas, there are approximately the same area proportions of p-type and n-type areas with approximately the same high doping concentration. Circular or hexagonal openings (in the exemplary embodiment of 1 : circular openings 5A ) or a connected grid (see reference number 14A ) are designed and designed in such a way that after a suitable diffusion, an approximately 50% area coverage is achieved.

The areas 8th in the border can like the areas 5 be circular or hex. However, they can also have a strip-like or other shape, as is the case in their mask openings 8a in the lower part of the 1 for the mask M is shown. The same applies to the areas 5 and 14 ,

The drift zone of the p-channel transistor with the areas 14 and the remaining areas 3 ' the layer 3 is symmetrical to the drift zone of the n-channel transistor with the regions 5 in the shift 3 built up, but for the contacting by the remaining layer 3 in the fields of 3 ' lying n-type pillars a buried n-type area 18 in the upper area of the substrate 2 is drawn in. This area 18 is over an area of the remaining layer 3 ' and the n-type tub 11 with the source zone 10 and a source contact of the p-channel transistor 21 connected.

In a similar way as in 3 the contacting of the n ⁺ -conducting source zone is shown 9 and the p-type well zone 15 via a deep contact hole in an insulating layer 19 from for example silicon dioxide by means of a source metallization consisting for example of aluminum 20 , The drain zone 7 of the n-channel transistor 22 is with a drain metallization 16 made of aluminum, for example. This drain metallization 16 can be through a bond wire 17 be contacted like this in 3 is shown.

The in 3 shown n-channel transistor 22 still has gate electrodes 6 made of polycrystalline silicon and field plates 23 made of polycrystalline silicon. The gate electrodes 6 and the field plates 23 are in the insulating layer 19 embedded. The field plates can 23 , as in 3 is shown, may be contacted.

With the p-channel transistor 21 is the blocking pn junction on the one hand by the p-type substrate 2 and the n-type areas 12 . 3 ' and 18 and on the other hand through the p-type regions 13 . 15A . 14 at the drain contact and the n-type tub in the area 18 educated.

The n-type area 18 must be cleared out under tension. For this to happen, the area must 18 on the one hand from the areas above 14 and the remaining area 3 ' the layer 3 , i.e. the compensation areas, and on the other hand from the underlying substrate 2 be cleared out. Therefore, the area load in the area 18 are below about 4 × 10 ¹² charge carriers cm ⁻² if the semiconductor material consists of silicon.

In terms of circuitry, an n / p-channel pair according to the semiconductor arrangement according to the invention is designed, for example, in a back-to-back configuration, as shown in FIG 2 is shown. The p-channel transistor lies between a positive voltage + U and ground potential 21 and the n-channel transistor 22 in row. Here is the source zone 10 of the p-channel transistor connected to the voltage + U, the drain zone 13 of the p-channel transistor is on the drain zone 7 of the n-channel transistor 22 connected and the source zone 9 of the n-channel transistor 22 is connected to ground potential.

Such a circuit structure has the advantage that for driving the n-channel transistor 22 a low voltage IC is sufficient while driving the p-channel transistor 21 a pull-down resistor can be used. No more positive voltage than the voltage + U is required as an intermediate circuit voltage, so that no charge pump needs to be used. There is a load between the two transistors.

For a monolithically integrated semiconductor arrangement with such a p / n channel pair, this means that the two drain zones 7 . 13 should be interconnected, which is easily done using a bonding wire, for example the bonding wire 17 , to the load connection of a housing is possible. A complex double layer metallization with a coupling capacitance and a field breakdown between the two metallization levels can thus be avoided.

In order to enable such an arrangement with a small footprint, an edge termination structure with symmetrical source and drain metallizations can be used 20 respectively. 16 be chosen, like this one from the 3 are evident. This way there is enough space around the drain zone 7 directly in their active area via metallization 16 with the bond wire 17 to contact.

In order to achieve the smallest possible space requirement for such a semiconductor arrangement in the layout, the drain zone 7 of the n-channel transistor 22 provided on the inside, being ring-shaped from the source zone 9 is surrounded. This allows space for the edge termination of the n-channel transistor 22 be saved.

When designing the p-channel transistor 21 the procedure is similar: here is the drain zone 13 circular from the source zone 10 surround. However, since the back of the semiconductor chip, i.e. the metallization 4 , is on ground is the source zone 10 of the p-channel transistor 21 to the outside still ring-shaped from p-conducting areas 8th from the edge termination and, if necessary, a p-conducting space charge zone stop made of p-conducting command 5 and 15 surround. The potential is therefore on a chip edge 27 and on the back of the chip with the metallization 4 each to ground. A corresponding arrangement is shown schematically in plan view in 4 shown.

In the semiconductor arrangement according to the invention, the compensation areas can 5 and 3 ' can each be designed variably, which means in particular the geometrically restricted narrowing of the current path in the direction of the drain 7 respectively. 13 can be counteracted. For example, the degree of compensation in the direction of current flow in the n-channel transistor can be 22 by gradually reducing the size of the p-type regions 5 vary towards a stronger dominance of the n-line. In the p-channel transistor 21 can also along the current flow by gradually widening the p-type grid from the areas 14 be shifted in the direction of the p-line.

While in the above embodiment the 1 to 4 a semiconductor arrangement is shown, in which the compensation by columnar or lattice-shaped areas 5 respectively. 14 in the vertical direction, other configurations are possible. Examples of this are in the 5A . 5B . 6A . 6B and 7A . 7B shown.

5A shows a plan view of an n-channel transistor 22 , in which an n-type area and a p-type area are located parallel to one another in the direction of the current path (see the arrow) as compensation areas.

In 5B is an equivalent representation for a p-channel transistor 21 also shown in top view.

The 6A and 6B show possible designs of the drift zone with vertically superimposed compensation areas. So is in 6A on average an n-channel transistor 22 shown while 6B equivalent to a p-channel transistor on average 21 shows. In the n-channel transistor 22 the current flows through an n-type layer on top (see arrow), while in the p-channel transistor the current path is conducted through a p-type layer which extends over an n-type well.

The 7A and 7B illustrate yet another embodiment of the invention, in which - similar to the embodiment of the 1 to 4 - with an n-channel transistor 22 p-type compensation areas 5 in an otherwise n-conducting environment 3 and with a p-channel transistor 21 n ^- leading compensation areas 3 ' in a p-type environment 14 are embedded. The areas 5 respectively. 3 ' can have an essentially arbitrary shape. It is only essential that approximately charge compensation is achieved in the drift path.

In the above exemplary embodiments, each is shown in n / p-channel pairs. The transistors can 5A . 5B respectively. 6A . 6B respectively. 7A . 7B in a similar manner as in the embodiment of 1 be integrated with each other. Such an integration can also include more than two transistors.

1

p ^* contact zone

2

p ^- silicon substrate

3

n-silicon layer

3 '

to Implantation remaining semiconductor layer

4

backside metallization

5

compensation region

6

gate electrode

6 '

gate electrode

7

drain region

8th

P-type area

9

source zone

10

source zone

11

n-well

12

n-well

13

drain region

14

P-type area

15

p-well

15A

p-well

16

Drain metallization

17

bonding wire

18

n-region

19

insulating

20

Source metallization

21

p-channel transistor

22

n-channel transistor

23

field plate

27

chip edge

M

mask

5A

Opening in mask for area 5

8A

Opening in mask for area 8th

14A

Opening in mask for area 14

Claims (26)

Semiconductor arrangement comprising at least one first transistor ( 22 ) with a channel of one conduction type and at least one transistor ( 21 ) with one channel of the other, for one conduction type of opposite conduction type, both transistors ( 22 . 21 ) in a semiconductor body ( 2 . 3 ) are provided, characterized in that - the at least one first transistor ( 22 ) at least one area in its drift section ( 5 ) of the other conductivity type, - the at least one second transistor ( 21 ) at least one area in its drift section ( 3 ' ) of one conductivity type, and - the at least one first transistor ( 22 ) and the at least one second transistor ( 21 ) are complementarily symmetrical in their drift ranges. A semiconductor device according to claim 1, there characterized in that the at least one area ( 5 ) of the at least one first transistor ( 22 ) and the at least one area ( 3 ' ) of the at least one second transistor ( 21 ) are designed to be complementary symmetrical. Semiconductor arrangement according to claim 1 or 2, characterized in that - the semiconductor body ( 2 . 3 ) a semiconductor substrate ( 2 ) of the other conductivity type and a semiconductor layer arranged thereon ( 3 ) of one line type, - that the at least one area ( 5 ) of the other conductivity type in the semiconductor layer ( 3 ) is embedded, and - that the at least one area ( 3 ' ) of one conductivity type through areas of the semiconductor layer ( 3 ) is formed. Semiconductor arrangement according to claim 3, characterized in that the semiconductor layer ( 3 ) of the at least one first transistor ( 22 ) and embedded areas ( 14 ) of the other conductivity type of the at least one second transistor ( 21 ) are essentially of the same structure. Semiconductor arrangement according to one of claims 4, characterized in that the at least one embedded region ( 5 ) of the other conductivity type and / or through areas of the semiconductor layer ( 3 ) formed area ( 3 ' ) of the one line type are each structured like an island. Semiconductor arrangement according to one of claims 1 to 5, characterized in that the second transistor ( 21 ) with a tub zone ( 18 ) of one line type. Semiconductor arrangement according to one of Claims 1 to 6, characterized in that the at least one region ( 5 ) of the other line type and the at least one area ( 3 ' ) of the one line type are compensation areas. Semiconductor arrangement according to Claim 7, characterized in that the compensation areas are aligned vertically. Semiconductor arrangement according to claim 7, characterized in that the compensation areas are laterally aligned (cf. 5A . 5B . 6A . 6B ). Semiconductor arrangement according to claim 8, characterized in that the compensation areas are columnar (cf. 7A . 7B ). Semiconductor arrangement according to one of Claims 1 to 10, characterized in that in each case one transistor ( 21 ) with a channel of the other conduction type and a transistor ( 22 ) with a channel of the one conduction type in a p / n-channel pair in the semiconductor body ( 1 . 2 ) are integrated. Semiconductor arrangement according to claim 11, characterized in that in the transistor ( 22 ) with a channel of one line type a source zone ( 7 ) from a drain zone ( 9 ) is essentially surrounded (cf. 4 ). Semiconductor arrangement according to claim 11 or 12, characterized in that in the transistor ( 21 ) with a channel of the other line type a drain zone ( 13 ) from a source zone ( 10 ) is surrounded. Semiconductor arrangement according to claim 13, characterized in that around the source zone ( 10 ) of the transistor ( 21 ) with a channel of the other line type an edge termination with areas ( 8th ) of the other line type is provided. Semiconductor arrangement according to Claim 14, characterized in that the regions ( 8th ) of the edge finish are columnar. Semiconductor arrangement according to one of Claims 1 to 15, characterized in that the transistor ( 21 ) with a channel of the other conduction type and the transistor ( 22 ) are in series with a channel of one line type between a positive voltage (+ U) and ground potential. Semiconductor arrangement according to claim 16, characterized in that drain ( 13 ) of the transistor ( 21 ) with a channel of the other conduction type with drain ( 7 ) of the transistor ( 22 ) is connected to a channel of one line type. Semiconductor arrangement according to claim 16 or 17, characterized in that at the connection point between the transistor ( 21 ) with a channel of the other conduction type and the transistor ( 22 ) there is a load with a channel of one line type. Semiconductor arrangement according to one of Claims 1 to 18, characterized in that the degree of compensation in the direction of the current flow in at least one of the two transistors ( 21 . 22 ) is designed variably. Semiconductor arrangement according to one of Claims 1 to 19, characterized in that a drain zone ( 7 ) of the transistor ( 22 ) with a channel of one line type through a tub zone ( 11 ) one line type is reinforced. Semiconductor arrangement according to one of claims 1 to 20, characterized in that between the transistor ( 22 ) with a channel of one conduction type and the transistor ( 21 ) with a channel of the other line type an edge termination from areas ( 8th ) of the other line type is provided. Semiconductor arrangement according to one of Claims 1 to 21, characterized in that a drain zone ( 13 ) of the transistor ( 21 ) with a channel of the other line type through a tub zone ( 15A ) of the other line type is reinforced. Semiconductor arrangement according to Claim 6 and one of Claims 1 to 5 and 7 to 22, characterized in that the trough zone ( 18 ) of the one conduction type in a semiconductor body consisting of silicon has a surface charge below 4 × 10 ¹² charge carriers cm ⁻² . Semiconductor arrangement according to one of Claims 1 to 23, characterized in that the one line type is the n line type is. Method for producing the semiconductor arrangement according to Claim 4 and one of Claims 1 to 3 and 5 to 24, characterized in that the at least one region ( 5 ) of the other line type and / or the embedded areas ( 14 ) of the other line type and / or the areas ( 8th ) of the edge closure at the same time by internal implantation into the semiconductor body using a mask (M) ( 2 . 3 ) are introduced. Mask for performing the method according to claim 25, characterized in that the mask (M) with openings ( 5A ) for the manufacture of the transistor ( 22 ) with a channel of one conduction type and covered areas for the production of the transistor ( 21 ) of the other line type is essentially of the same structure.