DE102023203783A1 - DEVICE AND METHOD FOR ACCESSING A CODE FLASH MEMORY - Google Patents

Abstract

A device (30; 300) and a method for accessing a CF memory chip (40), also called a CodeFlash memory, are provided. The device (30; 300) has a command interpreter (31) for interpreting a command from a microcontroller (10) that is intended to access a DF memory chip (50), and a telegram decoder (313) for determining whether a transaction requested with the command from the microcontroller (10) must act on the CF memory chip (40) that is to be accessed with the device (30) instead of the DF memory chip (50), or whether the command from the microcontroller (10) can be processed locally in the command interpreter (31).

Description

The present invention relates to a device and a method for accessing a CodeFlash memory, which is also referred to as a CF memory module.

To control technical systems or machines, data must be saved or written to remanent memory when required, read out again when required and/or deleted from the memory. Remanent memory, for example, uses flash memory, which is also called flash memory modules or flash modules. Writing, reading or deleting the memory is done using control commands that a microcontroller sends to the memory via an interface. Flash modules in NOR technology with a serial interface, also commonly referred to as "SPI flashes", are very common. NOR stands for "not or" in English.

Flash modules have a remanent memory area in which stored data values are retained even when the electrical power supply is switched off. With a conventional SPI flash memory module, which is referred to below as a CF memory module, the operating microcontroller carries out the data writing processes directly in the remanent memory area. Consequently, the microcontroller and thus also the higher-level application of the technical system must accept wait cycles.

An additional problem with CF memory chips is that when creating the control commands for a flash chip, the microcontroller has to take into account that the memory areas of the flash chip are divided into individual pages. The pages are grouped together to form blocks. Several blocks are grouped together to form sectors. In this case, a microcontroller can only erase the flash chip at block, sector or chip granularity before rewriting it with the appropriate commands, but not individual pages. Depending on the application, this can disadvantageously extend the microcontroller's wait cycles for interaction with the flash chip. This also extends the wait cycle for a higher-level application of the technical system, which can slow down the operation of the system.

It is possible to use a flash module instead, which has two internal SRAM buffers in front of the actual flash background memory. SRAM stands for static RAM (= Random Access Memory), which is a static direct access memory and belongs to the group of volatile memories. This means that the information stored in the SRAM is lost when the operating voltage is switched off. Such a flash module is referred to below as a DF module.

The SRAM buffers of the DF module allow write data to be received in one of the SRAM buffers via the serial interface (by means of or through or with (the help of) a "Buffer Write" command) and at the same time data from the other SRAM buffer to be transferred to the remanent flash background memory. A "Page Program" or "Page Program with Built-In Erase" command is used for this. This can shorten the previously mentioned wait cycles. Another advantage of this DF module is the efficient manipulation of individual data within the memory module, as the data blocks, which are organized in pages, or so-called "pages", do not have to be transferred to the microcontroller via the external interface, but can be processed in the upstream SRAM buffers and, if necessary with automatic deletion (Built-In Erase), written back to a page of the remanent flash area.

The problem is that a microcontroller must control a DF module with different commands than a CF memory module due to its described properties. If it is necessary to replace a DF module with a CF memory module, this also forces the microcontroller's software to be replaced. However, such an exchange is not always possible or is not permitted or desired due to a required qualification or certification chain for safety reasons.

It is therefore an object of the present invention to provide a device and a method for accessing a CF memory chip, with which the aforementioned problems can be solved. In particular, a device and a method for accessing a CF memory chip are to be provided which make it possible to accelerate further processing of data using the CF memory chip even when using a CF memory chip, so that wait cycles can be shortened by accessing the CF memory chip and the operation of a higher-level application of a technical system can be accelerated and/or that at least the temporal properties of the overall system which previously existed when using a DF memory are retained even when replaced by a CF memory.

This object is achieved by a device for accessing a CF memory module according to claim 1. The device has a command interpreter for interpreting a command from a microcontroller that is provided for accessing a DF memory module (50), and a telegram decoder for determining whether a transaction requested with the microcontroller's command must act on the CF memory module that is to be accessed with the device instead of the DF memory module, or whether the microcontroller's command can be processed locally in the command interpreter.

The described design of the device makes it possible to store data using a DF module, if required, additionally or alternatively using a CF memory module, without having to change the software of the controlling microcontroller.

As a result, the device increases the variability for the selection of the flash memory module of a technical system. In addition, the effort and the associated costs for changing and/or replacing the software of the microcontroller can be saved.

In addition, the device can be used to create redundancy using a different type of memory module without having to change the software of the controlling microcontroller. Parallel operation of at least two memory modules is possible, in particular to achieve diversity in the area of so-called functional safety. This can increase the safety of the technical system.

As a result, the device can, among other things, help to avoid lengthy and thus expensive downtimes of a higher-level technical system and/or to at least keep the temporal behavior of the system invariant in the event of replacing a DF memory module with a CF memory module.

Advantageous further embodiments of the device are specified in the dependent claims.

It is conceivable that the telegram decoder is designed to output a signal to a telegram generator in order to access the CF memory module.

In one embodiment, the device further comprises an SRAM buffer memory unit for temporarily storing data for a write command from the microcontroller to write the data into the CF memory chip, a data collector for temporarily storing data for a read command from the microcontroller to read the data stored in the CF memory chip, and a read multiplexer for outputting the data stored in the CF memory chip or in the SRAM buffer memory unit in response to a read command from the microcontroller.

The data collector may implement a FIFO queue so that data that is first stored into the data collector is first taken out of the data collector.

The device can also have a DF status register for signaling a status of the DF memory chip addressed by the microcontroller command, and a flash status decoder for decoding a status signaled by a CF status register of the CF memory chip, and for generating a signal for a status in the DF status register from the signaled status of the CF status register. The flash status decoder can be designed to generate the signal for writing to a bit of the DF status register as an identifier that indicates the status or flash status ready/not busy.

In one embodiment, the flash status decoder is designed to set a busy identifier in the DF status register when a program or erase command is issued to the CF memory device.

According to one embodiment, the telegram generator has an address allocator for allocating an address of the CF memory chip to an address of the DF memory chip that is included in the microcontroller's command. The device can also have a flash address register, the command interpreter being designed to generate a signal for the flash address register from the microcontroller's command, and the flash address register being designed to generate and output a signal to the telegram generator, the signal having the address of the DF memory chip in which the data is to be stored.

The telegram generator may have a command mapper for mapping a command for the CF memory chip to a command for the DF memory chip from a command telegram received from the microcontroller.

The telegram generator may have a shift register for composition and Sending a command telegram for the CF memory module.

In one embodiment, the command interpreter and/or the telegram generator has at least one of the following components/elements, namely AND gate, NAND gate, OR gate, NOR gate, flip-flop, a programmable logic component. The programmable logic component can be a CPLD and/or a gate array, in particular an FPGA, and/or a customer-specific integrated circuit (ASIC).

The device described above may also have an interface for connecting the device to the CF memory chip, wherein the interface should have a lower latency and a higher data rate than the interface between the microcontroller and the device.

The device described above can be part of a control device of a system that also has at least one technical installation. The control device is designed to control storage of data from or for the at least one technical installation.

The at least one technical system described above can be designed to carry out a work process and/or a manufacturing process.

The aforementioned object is also achieved by a method for accessing a CF memory module according to claim 15. The method has the steps of interpreting, with a command interpreter, a command of a microcontroller that is provided for accessing a DF memory module, and determining, with a telegram decoder, whether a transaction requested with the command of the microcontroller must act on the CF memory module that is to be accessed with the device instead of the DF memory module, or whether the command of the microcontroller can be processed locally in the command interpreter.

The method achieves the same advantages as previously mentioned with respect to the device.

Further possible implementations of the invention also include combinations of features or embodiments described above or below with respect to the exemplary embodiment that are not explicitly mentioned. The person skilled in the art will also add individual aspects as improvements or additions to the respective basic form of the invention.

• 1 ein Blockschaltbild eines Systems mit einer Vorrichtung gemäß einem ersten Ausführungsbeispiel;
• 2 ein Blockschaltbild eines Befehlsinterpreters der Vorrichtung von 1;
• 3 ein Blockschaltbild eines CF-Speicherbausteins für ein System von 1 oder für ein System mit einer Vorrichtung gemäß einem zweiten Ausführungsbeispiel;
• 4 ein Schaubild zur Veranschaulichung der Funktionsweise der Vorrichtung gemäß dem zweiten Ausführungsbeispiel für eine Umsetzung von Adressen eines DF-Speicherbausteins in Adressen des CF-Speicherbausteins von 3; und
• 5 ein Blockschaltbild eines Telegramm-Generators einer Vorrichtung gemäß dem zweiten Ausführungsbeispiel.

The invention is described in more detail below with reference to the accompanying drawings and exemplary embodiments. They show:

• 1 a block diagram of a system with a device according to a first embodiment;
• 2 a block diagram of a command interpreter of the device of 1 ;
• 3 a block diagram of a CF memory module for a system of 1 or for a system with a device according to a second embodiment;
• 4 a diagram to illustrate the operation of the device according to the second embodiment for converting addresses of a DF memory module into addresses of the CF memory module of 3 ; and
• 5 a block diagram of a telegram generator of a device according to the second embodiment.

In the figures, identical or functionally equivalent elements are provided with the same reference symbols unless otherwise stated.

1 shows a system 1 with a technical system 3 in which a work and/or production process is to be carried out. The technical system 3 is controlled with the aid of data 4 by a control device 5 of the system 1. The control device 5 can be designed at least partially as software. The control device 5 of 1 has a microcontroller 10, a serial interface 20, a device 30 and a CF memory chip 40 for storing the data 4. The CF memory chip 40 has an input/output interface with interface logic 41, a memory area 42 and a CF status register 43. Optionally, the control device 5 has a DF memory chip 50 to enable redundancy or an expansion of the memory capacity, for example. The DF memory chip 50 can also be connected to the interface 20 in order to be controlled by the microcontroller 10.

The technical system 3 can have a drive system (not shown) and/or a robot and/or a tool, such as a turning tool and/or milling tool and/or a joining tool, and/or an agitator or the like. The joining tool is in particular a welding tool or a riveting tool or a screwing tool, etc.

The working process is in particular a transport process or printing process or mixing process, etc. In the transport process, for example, a tool or workpiece or another object can be transported. In a manufacturing process, for example, at least one of the work processes can be carried out. Additionally or alternatively, in the manufacturing process, at least one workpiece can be treated with at least one tool that is mentioned above.

The control device 5 is designed for the operation and/or during operation of the system 1 to exchange data 4 with the technical system 3 as required. The data 4 are recorded, for example, by sensors (not shown) during operation of the technical system 3 and are passed on with the help of the microcontroller 10 via the interface 20 to the device 30 for storage in the CF memory module 40 and/or to the DF memory module 50. In addition, the control device 5 can send data 4 to the technical system 3 as required with the help of the microcontroller 10 via the interface 20, in particular target values for actuators of the drive system (not shown), etc.

The microcontroller 10 has a central processing unit (CPU) which is designed as a microprocessor 11, software 12 and memory modules 13, such as a main memory and a read-only memory (ROM). The central processing unit (CPU) or the microprocessor 11 can access the memory modules 13 using the software 12.

The microcontroller 10 is connected to the device 30 via the serial interface (SPI) 20. During operation, the microcontroller 10 sends a telegram CmdTG, which can also be called CmdTelegram, to the device 30 via the serial interface 20. The transmission of the telegram CmdTG takes place by or with (the help of) the signals DF_MOSI, DF_CLK, DF_CS, as described in more detail in 2 shown. The signal DF_MOSI transmits a command for the DF memory module 50, in which two SRAM buffer memories are arranged in front of a remanent flash background memory, as previously described with reference to the prior art. Additionally or alternatively, the microcontroller 10 receives a signal DF_MISO from the device 30 via the serial interface 20, by or with (the help of) which read data is transmitted to the microcontroller 10. These functions and signals are described in more detail below.

The device 30 has a command interpreter 31, which can also be called a command interpreter, an SRAM buffer memory unit 32, a flash address register 33, a telegram generator 34, a data collector 35, a read multiplexer 36, which can also be called a read multiplexer, and a serial interface 37.

The device 30 can comprise any logic components to form its aforementioned components 31 to 36. In particular, the device 30 comprises at least one of the following components/elements, such as AND gate, NAND gate, OR gate, NOR gate, flip-flop, a programmable logic device (PLD), such as a CPLD (Complex Programmable Logic Device) and/or a gate array, in particular FPGA (Field Programmable Gate Array), and/or a customer-specific integrated circuit (ASIC). In a special embodiment, the command interpreter 31 and the telegram generator 34 consist exclusively of digital logic and digital memory elements, so that they are implemented in a programmable logic device (PLD). In another special embodiment, the command interpreter 31 and the telegram generator 34 have exclusively digital logic and digital storage elements which are implemented in a programmable logic device (PLD) and implement the functions of the command interpreter 31 and the telegram generator 34 described below. The command interpreter 31 has a DF status register 311 in which the status of the DF memory module 50, such as ready, busy, etc., is displayed with an identifier or bit 31A, 31B. The data collection device 35 implements a FIFO (First In First Out) queue so that data 4 which is first stored in the device 35 is first taken out of the device 35.

During operation, the command interpreter 31 receives the commands of the software 12 and, if applicable, write data that may be based on the data from the microcontroller 10 via the serial interface 20. The commands are contained in the CmdTG telegram for the aforementioned DF flash memory chip or DF memory chip 50. The command interpreter 31 extracts the commands from the CmdTG telegram. The command interpreter 31 also enters any additional write data contained in the CmdTG telegram into the SRAM buffer memory unit 32.

In addition, the device 30 generates the signals CF_CLK, CF_CS during operation and sends them via the serial interface 37 to the serial interface 41 of the CF memory chip 40. The clock signal CF_CLK clocks the access for writing or reading to/in the memory area 42 of the CF memory chip 40.

The serial interface 37 has a lower latency and a higher data rate than the interface 20, which is located between the microcontroller 10 and the device 30. The serial interface 37 can be a QSPI interface. In such an embodiment, the signals CF_MISO and CF_MOSI are combined as a so-called "bidirectional bus" and comprise a total of four digital signals instead of just one signal each.

For this purpose, the command interpreter 31 controls the telegram generator 34 according to the data transmitted via the signal DF_MOSI ( 2 ) received commands from the software 12. In addition, the command interpreter 31 stores the currently obtained address for the DF memory chip 50 in the commands received from the software 12 in the flash address register 33. In addition, the command interpreter 31 implements the status register of the DF memory chip 50 with its DF status register 311. In addition, the command interpreter 31 outputs a signal AddrSt to the flash address register 33. The flash address register 33 generates a signal Addr from this and outputs this to the telegram generator 34. The signal Addr contains the address of the previously mentioned DF memory chip 50.

In addition, the command interpreter 31 sends a signal CmdCtrl to the telegram generator 34. And the command interpreter 31 receives from the telegram generator 34 a signal word CmdFdb/FLSt_In, which contains status information FLSt_In from the telegram generator 34.

In addition, the command interpreter 31 controls the storage of any write data transmitted with the telegram CmdTG in the SRAM buffer memory unit 32 and for this purpose outputs a signal or a command WrCtrl for writing to the SRAM buffer memory unit 32. The write data from the SRAM buffer memory unit 32 can be passed on to the telegram generator 34 by or with (the help of) a signal WrDt.

In addition, the command interpreter 31 controls the reading of data in the SRAM buffer memory unit 32 via the read multiplexer 36, which emulates the two SRAM buffer memories of the DF memory module 50. The SRAM buffer memory unit 32 outputs the read data to the read multiplexer 36 through or with the signal RdDt2.

For the purpose of reading the emulated DF status register 311, the command interpreter 31 outputs the register contents to the read multiplexer 36 through or with (the help of) the signal RdDt1.

Additionally or alternatively, the command interpreter 31 outputs a signal or a command RdEn/RdAddr to activate reading of the data in the CF memory chip 40 to the data collection device 35. The data collection device 35 outputs the read data to the SRAM buffer memory unit 32 by or with the signal RdDt3. The signal RdDt3 is also passed on to or output from the read multiplexer 36 in the event that the read data is not to be stored in the SRAM buffer memory 32 but is to be output directly via the serial interface 20.

The command interpreter 31 as well as the SRAM buffer memory 32 are specifically designed and/or dimensioned and/or tuned for the DF memory device that is addressed with the commands of the microcontroller 10, as previously described.

The telegram generator 34 converts read, write and erase commands (Read, Program, Erase), which the command interpreter 31 signals through or with the control word CmdCtrl, into CF-specific commands and sends the corresponding telegrams to the CF memory module 40 via the data lines WrDt of the serial interface 37. The telegram generator 34 thus generates the specific telegrams for the CF memory module 40. The telegram generator 34 is thus designed and/or dimensioned and/or coordinated specifically for the CF memory module 40.

The telegram generator 34 also controls or monitors the reception of read data via the signal RdDt of the CF memory chip 40 and collects these in the data collection device 35. For this purpose, the telegram generator 34 controls the data collection device 35 with the signals WrENa/WrAddr and gives the command interpreter 31 feedback via or with the signal word CmdFdb.

In the case of program processes and/or erase processes for the module 40, the telegram generator 34 cyclically reads the CF status register 43 of the CF memory module 40. The telegram generator 34 forwards a busy status of the CF memory module 40 to the command interpreter 31, which displays the information (busy identifier 31B or "BusyFlag") about the status in the emulated DF status register 311. The read protection status (WriteProtection status) and locking or unlocking of memory areas of the DF memory module 50 are also managed in the command interpreter 31, more precisely its DF status register 311, or forwarded to the telegram generator 34.

Another function of the command interpreter 31 is the representation of the JEDEC Device ID information of the emulated DF memory module 50, which can be generated by or with (the help of) its own a command telegram can be read out via the serial interface 20. The information is an identifier with a length of 6 bytes, the structure of which was defined by a standard of the US organization "JEDEC Solid State Technology Association".

The structure of the command interpreter 31 and the SRAM buffer memory 32 is shown in 2 shown in more detail.

According to 2 In addition to the DF status register 311, the command interpreter 31 has a state machine 312, a telegram decoder 313, a memory multiplexer 314 and a DF deviceID register 315. The SRAM buffer memory 32 has a first SRAM buffer 321, a second SRAM buffer 322 and a write multiplexer 323. The read multiplexer 36 has 2 the five channels 1, 2, 3, 4, 5.

The processes described below are controlled by the state machine 312, which can also be referred to as a finite state machine (FSM). Information Op/St about the requested transactions is exchanged between the telegram decoder 313 and the state machine 312. In 2 However, for reasons of clarity, the control signals and write/read addresses generated by the state machine 312 to the individual components of the command interpreter 31 are omitted, namely control signals to the multiplexers 36, 323, write and read addresses to the SRAM buffers 321, 322, a WriteEnable qualifier to the SRAM buffers 321, 322 and to the registers 33, 311, 315.

The command telegram CmdTG of the microcontroller 10 arriving via the data input DF_MOSI is broken down, i.e. decoded, in the telegram decoder 313. For this purpose, the DF command, a possibly subsequent DF-related address and possibly subsequent write data are extracted from the command telegram CmdTG. The telegram decoder 313 therefore receives the signals DF_CS, DF_CLK, DF_MOSI.

With regard to the DF command information, the telegram decoder 313 first determines (first option) whether the transaction requested with the command telegram CmdTG must act on the downstream CF memory module 40 or (second option) can be processed locally in the command interpreter 31. Transactions that must act on the downstream CF memory module 40 are, for example, the commands MainMemRead, WriteStatus, Erase, WriteBufferToMainMem. In contrast, transactions that can be processed locally in the command interpreter 31 are, for example, the commands Write/Read-SRAM-Buffer (= write or read at least one of the SRAM buffers 321, 322), Read-DF-DevicelD-Register (= read the DF-DevicelD register 315), Read-DF-StatusRegister (= read the DF status register 311).

If the telegram decoder 313 decides that the first option mentioned above applies, i.e. that the downstream CF memory module 40 is to be controlled, the telegram decoder 313 generates a corresponding control information CmdCtrl and passes this on to the telegram generator 34. In addition, the telegram decoder 313 stores a DF address received after the DF command with the signal AddrSt in the flash address register 33. The DF address is then also available to the telegram generator 34 via the signal Addr. The address register 33 also has a control input 331, via which the stored address Addr can be increased according to the request by the SPI clock DF_CLK of the interface 20 (address increment).

If, however, the telegram decoder 313 decides that the second option mentioned above applies, i.e. that only a local data transaction is requested from the microcontroller 10, no control information CmdCtrl is generated. Instead, the telegram decoder 313 controls at least one of the SRAM buffers 321, 322, the memory multiplexer 314 and, if applicable, the read multiplexer 36 accordingly.

In addition, the telegram decoder 313 is designed to store the write data WDt received via the SPI interface 20 and output in the telegram decoder 313 via the memory multiplexer 314 in at least one of the SRAM buffers 321, 322, which is/are selected at the DF_MOSI input in accordance with the received DF command, in the case of a command for a DF write operation (FlashProgram). The write data WDt can be passed on to the telegram generator 34 via the write multiplexer 323, provided that a WriteBufferToMainMem command has been decoded.

In addition, the telegram decoder 313 is designed to output the read data RDt21, RDt22 from at least one of the SRAM buffers 321, 322 to the microcontroller 10 via the signal DF_MISO in the case of a read command via channels 1 and/or 2 of the read multiplexer 36. The read data RDt21, RDt22 correspond to the signal RdDt2 in 1 .

The signal RdDt3 is received on channel 3 of the read multiplexer 36, read data from the data collection device 35, as previously described with respect to 1 described.

For the telegram decoder 313, a local transaction is also the reading of the DF DeviceL register 315 (channel 5 of the read multiplexer 36) and the output of the read data RdDt4. In addition, for the telegram decoder 313, a local transaction is also the reading of the emulated DF status register (channel 4 of the read multiplexer 36) and the output of the read data RdDt1. The DF status register 311 emulated in the command interpreter 31 must be updated with the commands or transactions "Write Status", "Erase", "Write Data to Buffer in Main Memory" (WriteBufferToMainMem). The telegram generator 34 initiates the updating and supplies the corresponding information as the FLSt_In (“FlashStatusInfo”) signal to the command interpreter 31, from which the information is reproduced in the DF status register 311. The DF status register 311 is updated cyclically with an Erase and a WriteBufferToMainMem command, and once and directly with a WriteStatus command.

The device 30 can thus access the memory area 42 of the CF memory module 40 by means of an input/output interface with interface logic 41 of the CF memory module 40. The input/output interface 41 is a serial interface and has corresponding interface logic modules of a serial interface, as described in more detail later.

3 until 5 describe an embodiment of the telegram generator 34 for a device 300 according to a second embodiment. In the second embodiment, the device 300 is designed to also process commands from the microcontroller 10, which can not only be processed locally in the command interpreter 31.

Accordingly, the telegram generator 34 is designed to carry out an address conversion, which can also be called address assignment, to addresses of the CF memory chip 40 on the basis of the DF address obtained from the flash address register 33. Such an address conversion may be necessary for a DF-typical page-granular programming and erasability, which is not available with the CF memory chip 40. An example of such an address conversion is shown in 3 and 4 explained.

3 shows the structure of the CF memory chip 40 in more detail. The CF memory chip 40 sends read data to its input/output interface 41 via the CF_MISO signal to a connected device, for example the device 30 of 1 . In addition, the CF memory chip 40 receives data at its input/output interface 41 via the signal CF_MOSI, as previously described.

The input/output interface 41 is usually implemented by an embedded microcontroller, which interprets CF commands or CF command telegrams received via the interface 41 and controls the execution of the corresponding operations in the memory area 42.

The memory area 42 of the CF memory module 40 is divided into pages P0, P1, P2, P3 to Pn-1, where n is a natural number > 1. Each of the pages P0, P1, P2, P3 to Pn-1 has a specific memory address Addr, as shown in 3 more precisely referred to as Addr_P0, Addr_P1, Addr_P2, Addr_P3 to Addr_Pn-1. The specific memory address is communicated to the CF memory chip 40 via the data signal CF_MOSI. Thus, data 4 is stored in the page P0, P1, P2, P3 to Pn-1 according to the specific memory address Addr_P0, Addr_P1, Addr_P2, Addr_P3 to Addr_Pn-1.

4 shows a special geometric example for the DF memory chip 50 with individually erasable pages DP0, DP1, DP2 to DP4095 (pages). Each of the pages DP0, DP1, DP2 to DP4095 of the DF memory chip 50 has a size of 512 bytes. The number of erasable pages DP0, DP1, etc. is not limited to the special example, but can be selected arbitrarily.

In contrast, in 4 the memory area 42 of the CF memory module 40 of 1 In this example, blocks B0, B1 to B4095, which can be individually erased. Each of the blocks B0, B1 to B4095 has 16 pages of 256 bytes each, namely block B0 has pages P0, P1 up to page 15, block B1 has pages P16, P17, etc., block B2 has pages P32, P33, etc., block B4095 has pages P65520, P65521, etc. The pages P0 to P65535 of the CF memory chip, however, cannot be individually erased.

This means that the CF memory module 40 of 1 can only individually erase a minimal granulation of 4KB blocks B0, B1 to B4095 (blocks with a size of 4KB), which in turn consist of 16 pages. Each of the pages P0, P1, P2, etc. of the CF memory chip 40 has a size of 256 bytes. Thus, a page of 512 bytes of the DF memory chip 50 is realized by two pages P0, P2, etc. of 256 bytes each within a block B1, B2, etc. of the CF memory chip 40, which results in a separate erasability in page granularity of the DF memory module 50.

Therefore, the device 300, more precisely the telegram generator 34, carries out a corresponding address conversion from the pages DP0, DP1, DP2 to DP4095 of the DF memory module 50 into 4 to blocks B0, B1 to B4095 of the CF memory module 40.

Accordingly, the telegram generator 34 is designed as in 5 shown in more detail.

According to 5 the telegram generator 34 has a state machine 341, an address allocator 342, a command allocator 343, a shift register 344 and a bus driver 345. The telegram generator 34 is connected to the command interpreter 31, the data collector 35, the read multiplexer 36 and the write multiplexer 323, as already explained above.

The data collector 35 has a read FIFO buffer 351, which may be implemented as a DPRAM, and a flash status decoder 352.

As previously mentioned, the data collection device 35 implements a FIFO (First In First Out) queue, namely for read data RdDt3 etc., as already described in 2 shown. The read data RdDt3 etc. are to be fetched from the CF memory module 40 in several read command sequences (read command sequences) due to the address conversion, but must be output continuously via the data signal DF_MISO after the clock DF_CLK has been specified by the interface 20.

The read data RdDt3 etc. are taken from the data collection device 35 either into one of the SRAM buffers 321, 322 of 2 or transmitted via a data bypass directly to the read multiplexer 36, as already described in 2 shown and mentioned previously.

In this context, the telegram generator 34 ensures that read data RdDt3 etc. are always available in the FIFO buffer 351 in a timely manner, since the microcontroller 10 (SPI master) will fetch these in the SPI clock DF_CLK specified by it. To fetch the first read data (commands MainMemoryPageRead, ContinuousArrayRead) and to ensure that the read data RdDt3 etc. are available in a timely manner, the telegram generator 34 is designed as follows with regard to the transaction request received with the signal word “CmdCtrl”. This means that in addition to the higher data throughput and the lower latency of the interface 37 to the CF memory module 40, the telegram generator 34 uses the transmission time of the DF opcode 101, DF memory address 102 and the following Don't Care Bytes 103 as a time buffer. The Don't Care Bytes are also called dummy bits or bytes. Opcode 101 is also called op code or operation code. Opcode 101 specifies the number of a DF flash command for the DF memory chip 50. All opcodes 101 together form the command set of the DF flash memory chip 50 or the corresponding DF flash memory family.

The device 300 must send the first data bit to the microcontroller 10 ( 1 ). If a QSPI interface 41 is used, the command can be emulated using a QSPI-based CF memory chip 40, for example by a FastReadQuad_I/O_(OxEB) command, whereby the CF memory chip 40 delivers the first data bit after just 20 QSPI clock cycles.

The telegram generator 34 therefore always loads the subsequent data into the FIFO buffer 351 in advance.

The previously mentioned program and/or erase commands (Program, Erase), on the other hand, are less time-critical for the telegram generator 34. The reason for this is that the emulated DF status register 311 signals their execution in the CF memory module 40 to the microcontroller 10. The signaling is done with a Ready/NotBusy bit in the DF status register 311.

The processes described below are controlled by the state machine 341, which can also be referred to as a Finite State Machine (FSM). In 5 For reasons of clarity, control signals from the state machine 341 to the other components of the telegram generator 34, the bus driver 345 and the data collection device 35 are omitted.

Central component of the Telegram Generator 34 of 5 is the shift register 344. In the register 344, the control telegrams for the downstream CF memory module 40 are constructed on the basis of various data and output via the serial interface 37, more precisely the signal WDt.

Based on the information “CmdCtrl”, the command allocator 343 selects the corresponding CF command and stores the associated binary code in the shift register 344. The address allocator 342 forms a CF address Addr_P0 etc. from the DF address according to the mapping scheme or allocation scheme as shown in 4 as an example and described previously. In case of write transactions from the SRAM buffers 321, 322 of 2 , the shift register 344 successively inserts the write data WrDt coming from the write multiplexer 323 into the command telegram of the CF memory module 4 and sends it, at the QSPI interface 37 of 5 , 4 -bit-parallel via the (bidirectional) output of bus driver 345 to the interface 41 of the CF memory chip 40. In other words, the content of the shift register 344 is shifted out "four-bit-parallel" via the bus driver 345 as data WDt. Four data bits are therefore shifted in parallel per clock pulse of the CF_CLK signal.

In the case of read transactions on the CF memory module 40, the state machine 341 switches the data direction of the bus driver 345 after sending the corresponding read telegram from the shift register 344 to the CF memory module 40 and clocks the read data RDt into the read FIFO buffer 351 of the data collection device 35. The clock CF_CLK is used here, while the FIFO buffer 351 is suitably controlled for storing the read data via the signals WrEna/WrAddr. The read data RDt is sent from the data collection device 35 at the clock DF_CLK ( 2 ) and output as read data RdDt3 via the read multiplexer 36 to the microcontroller 10. The FIFO buffer 351 is controlled via a second data interface by or with the signals RdEna/RdAddr. This is also already described in 1 and/or 2 shown and described more generally above.

In the case of write transactions to the CF status register 43 and in the case of program or erase operations, the DF status register 311 emulated in the command interpreter 31 is always updated. For this purpose, the state machine 341 sends a status register read command or read command to the CF memory module 40 via the shift register 344 in order to form the WriteEnable and Protection flags.

The flash status decoder 352 breaks down and decodes the response of the CF memory chip 40 to a status register read command in order to form the flash status info of the DF status register 311 in the signal FLSt_In. The busy flag 31B of the DF status register 311, however, requires special treatment. The flash status decoder 352 sets the identifier 31B in the DF status register 311 when a program or erase command is sent to the CF memory module 40. After one of these commands has been completely sent, including if necessary sending the required write data WDt to the CF memory module 40, the state machine 341 causes the CF status register 43 to be continuously read out so that the busy identifier 31B (“busy flag”) of the CF status register 43 can indicate the end of the program or erase process in the CF memory module 40.

Otherwise, device 300 according to the present embodiment is constructed as described in the previous embodiment.

According to a third embodiment, the device 30 is designed to carry out a compact storage of the data of the DF pages DP0, DP1, DP2 etc. in the CF memory module 40 instead of an address conversion of the telegram generator 34. In this case, an address mapping table is kept, which is also called a mapping table. In addition, a relocation of complete blocks B0, B1 etc. of the CF memory module 40 is to be carried out in the case of a page write command for writing a page P0, P1 to Pn-1.

However, such a design of the device 30 is more time-consuming compared to the first embodiment, since copying and remanently saving the mapping table takes a lot of time. In addition, copying and remanently saving the mapping table in DF page granularity may not be able to be implemented in a power failure-safe manner.

In this way, the device 30 can store data 4 using the CF memory chip 40 and access it for reading, even if the software 12 of the controlling microcontroller 10 is designed to store in the DF memory chip 50.

Otherwise, the device 30 according to the present embodiment can be constructed as described in one of the preceding embodiments.

All previously described embodiments of the system 1, the devices 30, 300 and the method carried out by them can be used individually or in all possible combinations. In particular, all features and/or functions of the previously described embodiments can be combined as desired. In addition, the following modifications are conceivable.

The parts shown in the figures are schematic and may differ in their exact design from the forms shown in the figures, as long as their previously described functions are guaranteed.

To further save costs, the device 30, 300 can be at least partially accommodated in an existing CPLD or FPGA, provided that this is possible for the respective application or system 1, in particular also permissible.

Of course, it is possible that the CF memory module 40 has a different memory size for the pages P0, P1 to Pn-1 and/or the DF memory module 50 has a different memory size for the pages DP0, DP1, etc. than in 4 shown as an example. In addition, the number of sides of the building blocks 40, 50 can be different than in 4 shown as an example and described above. The telegram generator 34 is designed accordingly to carry out the address conversion from the DF memory module 50 to the CF memory module 40, as described above.

System 3 may additionally or alternatively have at least one NC control (numerical control) and/or at least one CNC control (computerized numerical control).

The system 3 can be or have a motion logic control for, for example, transport systems or for guiding tools, etc.

The industrial plant 1 may additionally or alternatively have a bending tool and/or a punching tool and/or a drilling tool and/or a torque tool.

Claims (15)

Device (30) for accessing a CF memory chip (40), with a command interpreter (31) for interpreting a command from a microcontroller (10) which is provided for accessing a DF memory chip (50), and a telegram decoder (313) for determining whether a transaction requested with the command from the microcontroller (10) must act on the CF memory chip (40) which is to be accessed with the device (30) instead of the DF memory chip (50), or whether the command from the microcontroller (10) can be processed locally in the command interpreter (31). Device (30) according to claim 1 , wherein the telegram decoder (313) is designed to output a signal (CmdCtrl) to a telegram generator (34) in order to access the CF memory module (40). Device (30) according to claim 1 or 2 , further comprising an SRAM buffer memory unit (32) for temporarily storing data (4) for a write command from the microcontroller (10) to write the data (4) into the CF memory chip (40), a data collection device (35) for temporarily storing data (4) for a read command from the microcontroller (10) to read the data (4) stored in the CF memory chip (40), and a read multiplexer (36) for outputting the data (4) stored in the CF memory chip (40) or in the SRAM buffer memory unit (32) in response to a read command from the microcontroller (10). Device (30) according to claim 3 , wherein the data collection device (35) implements a FIFO queue so that data (4) which are first stored in the data collection device (35) are first taken out of the data collection device (35). Device (30) according to one of the preceding claims, further comprising a DF status register (311) for signaling a status of the DF memory chip (50) addressed by the command of the microcontroller (10), and a flash status decoder (352) for decoding a status signaled by a CF status register (43) of the CF memory chip (40), and for generating, from the signaled status of the CF status register (43), a signal (FL_St_In) for a status in the DF status register (311). Device (30) according to claim 5 , wherein the flash status decoder (352) is configured to generate the signal (FL_St_In) for writing to a bit of the DF status register (311) as an identifier (31A) indicating the ready/not busy status. Device (30) according to claim 5 or 6 , wherein the flash status decoder (352) is designed to set a busy identifier (31B) in the DF status register (311) when a program or erase command is issued to the CF memory module (40). Device (30) according to one of the preceding claims, wherein the telegram generator (34) has an address allocator (342) for allocating an address (Addr_P0, ... Addr_Pn-1) of the CF memory module (40) to an address (Addr) of the DF memory module (50) which is included in the command of the microcontroller (10). Device (30) according to claim 8 , also with a flash address register (33), wherein the command interpreter (31) is designed to extract a signal (AddrSt) for the flash address register (33) from the command telegram of the microcontroller (10), and wherein the flash address register (33) is designed to generate and output a signal (Addr) to the telegram generator (34), wherein the signal (Addr) has the address of the DF memory module (50) in which the data (4) are to be stored. Device (30) according to claim 8 or 9 , wherein the telegram generator (34) has a command allocator (343) for allocating a command for the CF memory module (40) to a command for the DF memory module (50) from a command telegram (CmdTG) received from the microcontroller (10). Device (30) according to one of the Claims 8 until 10 , wherein the telegram generator (34) has a shift register (344) for composing and sending a command telegram (WDt) for the CF memory module (40). Device (30) according to one of the preceding claims, wherein the command interpreter (31) and/or the telegram generator (34) has at least one of the following components/elements, namely AND gate, NAND gate, OR gate, NOR gate, flip-flop, a programmable logic component, and wherein the programmable logic component is a CPLD and/or a gate array, in particular an FPGA, and/or a customer-specific integrated circuit. Device (30) according to one of the preceding claims, further comprising an interface (37) for connecting the device (30) to the CF memory module (40), wherein the interface (37) has a lower latency and a higher data rate than an interface (20) between the microcontroller (10) and the device (30). System (1) with at least one technical system (3) and a control device (5) for controlling storage of data (4) from or for the at least one technical system (3), wherein the control device (5) has at least one device (30) according to one of the preceding claims, wherein the at least one technical system (3) is designed to carry out a work process and/or a manufacturing process. Method for accessing a CF memory chip (40), comprising the steps of interpreting, with a command interpreter (31), a command of a microcontroller (10) which is provided for accessing a DF memory chip (50), and determining, with a telegram decoder (313), whether a transaction requested with the command of the microcontroller (10) must act on the CF memory chip (40) which is to be accessed with the device (30) instead of the DF memory chip (50), or whether the command of the microcontroller (10) can be processed locally in the command interpreter (31).

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