DE102023201219A1 - Transmission module and method for transmitting differential signals in a serial bus system - Google Patents

Abstract

A transmission module (121; 1210; 1211; 1212) and a method for transmitting differential signals in a serial bus system (1) are provided. The transmission module (121; 1210; 1211; 1212) has a first transmission stage (121A; 121A1) for generating transmission currents (I1 to In) for a first signal (CAN_H) to be sent to a bus (40) of the bus system (1), a second transmission stage (121B; 121B1) for generating transmission currents (I1 to In) for a second signal (CAN_L) to be sent to the bus (40) as a signal differential to the first signal (CAN_H), a third transmission stage (121C; 121C1) for generating transmission currents (I1 to In) for the first signal (CAN_H), a fourth transmission stage (121D; 121D1) for generating transmission currents (I1 to In) for the second signal (CAN_L), and a control circuit (15; 15A; 15B) for adjusting a common mode voltage (VCM) for the first to fourth transmission stages (121A to 121D; 121A1 to 121D1), wherein the first to fourth transmission stages (121A to 121D; 121A1 to 121D1) are connected in a full bridge, in which the first and fourth transmission stages (121A, 121D; 121A1, 121D1) are connected in series and the third and second transmission stages (121C, 121B; 121C1, 121B1) are connected in series, wherein the control circuit (15; 15A; 15B) has a replica (152; 153; 153A) of an output stage of the transmission module (121; 1210; 1211; 1212), and wherein the replica (152; 153; 153A) is connected to the output stage of the transmission module (121; 1210; 1211; 1212).

Description

The present invention relates to a transmission module and a method for transmitting differential signals in a serial bus system, which can be used in particular for CAN XL while complying with the emission limits (EMC).

State of the art

Serial bus systems are used for message or data transmission in technical systems. For example, a serial bus system can enable communication between sensors and control units in a vehicle or a technical production system, etc.

In a CAN bus system, messages are transmitted using the CAN and/or CAN FD protocol, as described in the ISO-11898-1:2015 standard as a CAN protocol specification with CAN FD. With CAN FD, the transmission on the bus switches back and forth between a slow operating mode in a first communication phase (arbitration phase) and a fast operating mode in a second communication phase (data phase). With a CAN FD bus system, a data transmission rate of more than 1 Mbit per second (1Mbps) is possible in the second communication phase. CAN FD is used by most manufacturers in the first step in the vehicle with a 500kbit/s arbitration bit rate and 2Mbit/s data bit rate.

In order to enable even higher data rates in the second communication phase, there are successor bus systems for CAN FD, such as CAN-SIC and CAN XL. With CAN-SIC in accordance with the CiA601-4 standard of the CAN in Automation (CiA) organization, a data rate of around 5 to 8 Mbit/s can be achieved in the second communication phase. With CAN XL, a data rate of > 10 Mbit/s is required in the second communication phase. A CiA610-3 standard is currently defined for CAN XL.

To send and receive the bus signals, transmit/receive devices are usually used in a CAN bus system for the individual communication participants, which are also referred to as CAN transceivers or CAN FD transceivers, etc. The transmit function of the CAN transceiver is implemented in a block called a transmitter. The transmitter translates a sequence of digital states (HI = high or LW = low) of a digital transmit signal into a differential bus signal between bus connections CANH and CANL.

In all of the CAN-based bus systems mentioned above, a CAN_H bus signal and, ideally, a CAN_L bus signal with a predetermined bus level or bus voltage V_CAN_H, V_CAN_L are driven onto a bus separately for a transmit signal TxD. In this case, at least in the first communication phase, one bus state is actively driven in the bus signals CAN_H, CAN_L. The other bus state is not driven and is set due to a terminating resistor for bus lines or bus wires of the bus. The resulting voltage on the bus is the differential voltage VDIFF = CAN_H - CAN_L, or more precisely, the differential voltage is equal to the voltage U of the CAN_H signal minus the voltage U of the CAN_L signal.

The differential voltage VDIFF varies depending on the state to be transmitted on the bus. For the dominant state, VDIFF_dom = 2V. For the recessive state, VDIFF_rec = 0V. For the Level0 state, VDIFF_L0 = 1V. For the Level1 state, VDIFF_L1 = -1V. However, for all of the above states, the two bus levels or voltage amplitudes VCAN_H, VCAN_L of the CAN_H, CAN_L signals should remain centered around the value of a common-mode voltage V _CM = VCAN_H + VCAN_L = 5 V. This is important because variations in this common-mode voltage V _CM cause interference from the CAN transceiver. The value of 5 V corresponds to the value of the voltage Vcc, which is also called CAN supply. To comply with the CAN specifications (ISO11898-2:2016, CiA601-4, CiA610-3) and the EMC standard (IEC62228-3), the common mode voltage V _CM should always remain at exactly the same voltage, regardless of the bus signal or the differential voltage VDIFF. This also applies during switching between the different bus states.

The CAN transceivers or CAN FD transceivers must not exceed the limits for operation in the vehicle with regard to conducted radiation or emissions. In comparison to CAN FD and CAN SIC, transceivers for CAN XL must comply with even stricter limits, which are set out in the IEC62228-3 standard. This is the only way to operate the bus system at the specified higher bit rates. possible. Depending on the semiconductor technology available, compliance with these strict limits represents a major challenge.

Disclosure of the invention

It is therefore an object of the present invention to provide a transmission module and a method for transmitting differential signals in a serial bus system which solve the problems mentioned above. In particular, the transmission module and the method for transmitting differential signals in a serial bus system should enable the compensation of interference variables which affect the emission behavior of the transmission module.

The object is achieved by a transmission module for transmitting differential signals in a serial bus system with the features of claim 1. The transmission module has a first transmission stage for generating transmission currents for a first signal that is to be transmitted to a bus of the bus system, a second transmission stage for generating transmission currents for a second signal that is to be transmitted to the bus as a signal differential to the first signal, a third transmission stage for generating transmission currents for the first signal, a fourth transmission stage for generating transmission currents for the second signal, and a control circuit for adjusting a common-mode voltage for the first to fourth transmission stages, wherein the first to fourth transmission stages are connected in a full bridge in which the first and fourth transmission stages are connected in series and the third and second transmission stages are connected in series, wherein the control circuit has a replica of an output stage of the transmission module, and wherein the replica is connected to the output stage of the transmission module.

The described transmitter module is designed to always keep the common mode voltage at exactly the same voltage, regardless of a bus signal VDIFF. This also applies during the switching processes between the different bus states dom, sic and rec or L0 and L1.

In particular, the described transmitter module ensures that the common-mode voltage remains the same, even if the common-mode voltage is influenced by the temperature and process dependence of diodes and cascodes (component parameters and leakage currents) of the transmitter module. This also applies to a transmitter module in which a resistance bridge, also called a current-controlled H-bridge, has an additional dependence on the matching or mismatching of bias currents. In addition, this also applies to a transmitter module in which a resistance bridge, also called a resistive H-bridge, has an additional temperature and process dependence on a channel resistance of current-limiting transistors.

The described transmitter module thus enables the required limit values for the emission of a transmitting/receiving device for CAN XL to be achieved. The transmitter module particularly complies with the IEC62228-3 standard, which specifies the specifications for CAN XL and the limit values to be observed for the bus states dom, sic and rec on the bus, which were generated based on the transmitting states dom, sic and rec of the transmitter module.

The transmitter module thus prevents emissions and allows operation in the bus system at higher bit rates.

Advantageous further embodiments of the transmission module are described in the dependent claims.

A common mode point of the replica can be at the common mode voltage of the output of the transmission stages. According to one embodiment, the control circuit also has a differential amplifier with an input connected to the common mode point of the replica and a control transistor for controlling a common mode voltage to a predetermined value, the common mode voltage being applied to the common mode point of the replica.

It is conceivable that the replica comprises a series circuit of a transistor, a diode, a transistor, a diode, a transistor and a transistor in the order mentioned, wherein the sizes of the components of the series circuit are smaller by a predetermined factor than the sizes of the components of the output of the first and fourth transmission stages. In this case, the transistor and the transistor can each be designed as a cascode.

In the previously described transmitter module, output terminals of the full bridge can be provided for connection to a terminating resistor of the bus, wherein the replica in the series connection has a bus load which is a replica of a terminating resistor of the bus.

According to one embodiment, the bus load has two resistors, both connected to the common mode point of the replica.

According to another embodiment, the replica has a switching unit for switching the bus load on or off.

Each transmitting stage can be designed to adjust the value of the electrical current output by the transmitting stage during operation of the transmitting module using a current mirror at the input of the transmitting stage.

The current mirror at the input of each transmission stage can have two CMOS transistors, wherein the CMOS transistors of the current mirror at the input of the first transmission stage are PMOS transistors, wherein the CMOS transistors of the current mirror at the input of the second transmission stage are NMOS transistors, wherein the CMOS transistors of the current mirror at the input of the third transmission stage are PMOS transistors, and wherein the CMOS transistors of the current mirror at the input of the fourth transmission stage are NMOS transistors.

Each transmission stage can have at least two current stages that are connected in parallel to one another. The at least two current stages can have at least one current sink. It is possible that a number n of the at least two current stages is the same for each of the first to fourth transmission stages, where n is a natural number greater than 1.

The transmitter module may also have a first resistor having one end connected to the first transmitter stage and the other end connected to the third transmitter stage, and a second resistor having one end connected to the second transmitter stage and the other end connected to the fourth transmitter stage.

The transmission module can also have a control circuit for controlling switchable components of the first to fourth transmission stages depending on a digital transmission signal and on an operating mode set for the transmission module. The control circuit may be designed for the time-staggered and controlled switching of the resistance values of the at least two current stages.

The previously described transmitting module can be part of a transmitting/receiving device for a subscriber station for a serial bus system, which also has a receiving module for receiving signals from the bus.

The transmitting/receiving device can be part of a subscriber station for a serial bus system, which also has a communication control device for controlling the communication in the bus system and for generating a digital transmission signal for controlling the first to fourth transmission stages.

The subscriber station may be designed for communication in a bus system in which exclusive, collision-free access of a subscriber station to the bus of the bus system is guaranteed at least temporarily.

The aforementioned object is also achieved by a method for transmitting differential signals in a serial bus system having the features of claim 20. The method is carried out with a transmission module which has a first to fourth transmission stage and a control circuit, the method comprising the steps of generating, with the first transmission stage, transmission currents for a first signal which is to be sent to a bus of the bus system, generating, with the second transmission stage, transmission currents for a second signal which is to be sent to the bus as a signal differential to the first signal, generating, with the third transmission stage, transmission currents for the first signal, generating, with the fourth transmission stage, transmission currents for the second signal, and balancing, with the control circuit, a common-mode voltage for the first to fourth transmission stages, the first to fourth transmission stages being connected in a full bridge in which the first and fourth transmission stages are connected in series and the third and second transmission stages are connected in series, the control circuit having a replica of an output stage of the transmission module, and the replica being connected to the output stage of the transmission module.

The method offers the same advantages as previously mentioned with regard to the transmitter module.

Further possible implementations of the invention also include combinations of features or embodiments described above or below with respect to the exemplary embodiments that are not explicitly mentioned. The person skilled in the art will also add individual aspects as improvements or additions to the respective basic form of the invention.

Drawings

• 1 ein vereinfachtes Blockschaltbild eines Bussystems gemäß einem ersten Ausführungsbeispiel;
• 2 ein Schaubild zur Veranschaulichung des Aufbaus einer Nachricht, die von einer Teilnehmerstation des Bussystems gemäß dem ersten Ausführungsbeispiel gesendet werden kann;
• 3 ein Beispiel für den idealen zeitlichen Verlauf von Bussignalen CAN_H, CAN_L in dem Bussystem von 1;
• 4 den zeitlichen Verlauf einer Differenzspannung VDIFF, die sich auf dem Bus des Bussystems infolge der Bussignale von 3 ausbildet;
• 5 ein Beispiel für einen zeitlichen Verlauf eines digitalen Sendesignals, welches in der Arbitrationsphase (SIC-Betriebsart) in Bussignale CAN_H, CAN_L für einen Bus des Bussystems von 1 umgesetzt werden soll;
• 6 den zeitlichen Verlauf der Bussignale CAN_H, CAN_L beim Wechsel zwischen einem rezessiven Buszustand zu einem dominanten Buszustand und zurück zu dem rezessiven Buszustand, die in der Arbitrationsphase (SIC-Betriebsart) aufgrund des Sendesignals von 5 auf den Bus gesendet werden;
• 7 ein Beispiel für einen zeitlichen Verlauf eines digitalen Sendesignals, welches in der Datenphase in Bussignale CAN_H, CAN_L für den Bus des Bussystems von 1 umgesetzt werden soll;
• 8 den zeitlichen Verlauf der Bussignale CAN_H, CAN_L, die in der Datenphase aufgrund des Sendesignals von 7 auf den Bus gesendet werden;
• 9 ein Schaltbild eines Sendemoduls für eine Teilnehmerstation des Bussystems gemäß dem ersten Ausführungsbeispiel;
• 10 ein Zeitdiagramm zur Darstellung der Einschaltung verschiedener Stromstufen einer Sendestufe für ein erstes spezielles Beispiel des Sendemoduls von 9;
• 11 ein Detail einer Sendestufe für ein zweites spezielles Beispiel des Sendemoduls von 9;
• 12 ein Schaltbild eines Sendemoduls für eine Teilnehmerstation des Bussystems gemäß einem zweiten Ausführungsbeispiel;
• 13 ein Schaltbild eines Sendemoduls für eine Teilnehmerstation des Bussystems gemäß einem dritten Ausführungsbeispiel; und
• 14 ein Schaltbild eines Sendemoduls für eine Teilnehmerstation des Bussystems gemäß einem vierten Ausführungsbeispiel.

The invention is described in more detail below with reference to the accompanying drawings and exemplary embodiments. They show:

• 1 a simplified block diagram of a bus system according to a first embodiment;
• 2 a diagram illustrating the structure of a message that can be sent by a subscriber station of the bus system according to the first embodiment;
• 3 an example of the ideal timing of bus signals CAN_H, CAN_L in the bus system of 1 ;
• 4 the time course of a differential voltage VDIFF, which occurs on the bus of the bus system as a result of the bus signals from 3 trains;
• 5 an example of a time course of a digital transmission signal, which in the arbitration phase (SIC operating mode) is converted into bus signals CAN_H, CAN_L for a bus of the bus system of 1 should be implemented;
• 6 the time course of the bus signals CAN_H, CAN_L when changing between a recessive bus state to a dominant bus state and back to the recessive bus state, which in the arbitration phase (SIC operating mode) due to the transmission signal from 5 sent to the bus;
• 7 an example of a time course of a digital transmission signal, which in the data phase is converted into bus signals CAN_H, CAN_L for the bus of the bus system of 1 should be implemented;
• 8 the time course of the bus signals CAN_H, CAN_L, which in the data phase are generated due to the transmission signal from 7 sent to the bus;
• 9 a circuit diagram of a transmitter module for a subscriber station of the bus system according to the first embodiment;
• 10 a timing diagram showing the activation of different current levels of a transmitting stage for a first specific example of the transmitting module of 9 ;
• 11 a detail of a transmitting stage for a second special example of the transmitting module of 9 ;
• 12 a circuit diagram of a transmitter module for a subscriber station of the bus system according to a second embodiment;
• 13 a circuit diagram of a transmitter module for a subscriber station of the bus system according to a third embodiment; and
• 14 a circuit diagram of a transmitter module for a subscriber station of the bus system according to a fourth embodiment.

In the figures, identical or functionally equivalent elements are provided with the same reference symbols unless otherwise stated.

Description of the embodiments

1 shows a bus system 1, which can be, for example, at least in sections, a CAN bus system, a CAN-FD bus system, etc. The bus system 1 can be used in a vehicle, in particular a motor vehicle, an aircraft, etc., or in a hospital, etc.

In 1 The bus system 1 has a large number of subscriber stations 10, 20, 30, each of which is connected to a bus 40 or bus line with a first bus wire 41 and a second bus wire 42. The bus wires 41, 42 can also be called CAN_H and CAN_L for the signals on the bus 40. Messages 45, 46, 47 in the form of signals can be transmitted between the individual subscriber stations 10, 20, 30 via the bus 40. The subscriber stations 10, 20, 30 can be, for example, control units or display devices of a motor vehicle.

As in 1 As shown, the subscriber stations 10, 30 each have a communication control device 11 and a transmitting/receiving device 12. The transmitting/receiving device 12 has a transmitting module 121 and a receiving module 122.

The subscriber station 20 has a communication control device 21 and a transmitting/receiving device 22. The transmitting/receiving device 22 has a transmitting module 221 and a receiving module 222.

The transmitting/receiving devices 12 of the subscriber stations 10, 30 and the transmitting/receiving device 22 of the subscriber station 20 are each directly connected to the bus 40, even if this is not the case in 1 is not shown.

The communication control devices 11, 21 each serve to control communication of the respective subscriber station 10, 20, 30 via the bus 40 with at least one other subscriber station of the subscriber stations 10, 20, 30 that are connected to the bus 40.

The communication control devices 11 create and read first messages 45, 47, which are, for example, modified CAN messages 45, 47. The modified CAN messages 45, 47 are constructed, for example, on the basis of the CAN SIC format or the CAN XL format. The transmitting/receiving device 12 is used to send and receive the messages 45, 47 from the bus. The transmitting module 121 receives a digital transmit signal TxD created by the communication control device 11 for one of the messages 45, 47 and converts this into signals on the bus 40. The receiving module 121 receives signals sent on the bus 40 corresponding to the messages 45 to 47 and generates a digital receive signal RxD from them. The receiving module 122 sends the receive signal RxD to the communication control device 11.

The communication control device 21 can be designed like a conventional CAN controller according to ISO 11898-1:2015, i.e. like a CAN FD tolerant Classical CAN controller or a CAN FD controller. The communication control device 21 creates and reads second messages 46, for example CAN FD messages 46. The transmitting/receiving device 22 is used to send and receive the messages 46 from the bus 40. The transmitting module 221 receives a digital transmit signal TxD created by the communication control device 21 and converts this into signals for a message 46 on the bus 40. The receiving module 221 receives signals sent on the bus 40 corresponding to the messages 45 to 47 and generates a digital receive signal RxD from them. Otherwise, the transmitting/receiving device 22 can be designed like a conventional CAN transceiver.

To send messages 45, 47 with CAN XL or CAN SIC, proven properties are adopted that are responsible for the robustness and user-friendliness of CAN and CAN FD, in particular the frame structure with identifier and arbitration according to the well-known CSMA/CR method. The CSMA/CR method means that there must be so-called recessive states on the bus 40, which can be overwritten by other subscriber stations 10, 20, 30 with dominant levels or dominant states on the bus 40.

With the two subscriber stations 10, 30, a formation and then transmission of messages 45 with different CAN formats, in particular the CAN FD format or the CAN SIC format or the CAN XL format, as well as the reception of such messages 45 is possible, as described in more detail below.

2 shows a frame 450 for the message 45, which is in particular a CAN XL frame, as provided by the communication control device 11 for the transmitting/receiving device 12 for sending to the bus 40. In this case, the communication control device 11 creates the frame 450 in the present embodiment as compatible with CAN FD. Alternatively, the frame 450 is compatible with CAN SIC.

According to 2 the frame 450 for the CAN communication on the bus 40 is divided into different communication phases 451, 452, namely an arbitration phase 451 (first communication phase) and a data phase 452 (second communication phase). The frame 450 has, after a start bit SOF, an arbitration field 453, a control field 454, a first switching field 455, a data field 456, a checksum field 457, a second switching field 458 and a frame termination field 459. The checksum field 457, the second switching field 458 and the frame termination field 459 form a frame end phase 457, 458, 459 of the frame 450.

In the arbitration phase 451, with the help of an identifier (ID) in the arbitration field 453, it is negotiated bit by bit between the subscriber stations 10, 20, 30 which subscriber station 10, 20, 30 wants to send the message 45, 46 with the highest priority and therefore receives exclusive access to the bus 40 of the bus system 1 for the next time for sending in the subsequent data phase 452. In the arbitration phase 451, a physical layer is used as in CAN and CAN-FD. The physical layer corresponds to the bit transmission layer or layer 1 of the well-known OSI model (Open Systems Interconnection model).

An important point during phase 451 is that the well-known CSMA/CR method is used, which allows simultaneous access of the subscriber stations 10, 20, 30 to the bus 40 without destroying the higher priority message 45, 46. This makes it relatively easy to add additional bus subscriber stations 10, 20, 30 to the bus system 1, which is very advantageous.

The CSMA/CR method means that there must be so-called recessive states on the bus 40, which can be overwritten by other subscriber stations 10, 20, 30 with dominant levels or dominant states on the bus 40. In the recessive state, high-impedance conditions prevail at the individual subscriber station 10, 20, 30, which, in combination with the parasitics of the bus circuit, results in longer time constants. This leads to a limitation of the maximum bit rate of today's CAN FD physical layer to currently around 2 megabits per second in real vehicle use.

At the end of the arbitration phase 451, the first switching field 455 is used to switch to the data phase 452.

In the data phase 452, in addition to a part of the first switching field 455, the payload data of the CAN-XL frame 450 or the message 45 from the data field 456 as well as the checksum field 457 and a part of the second switching field 458 are sent. At the end of the data phase 452, the system switches back to the arbitration phase 451 using the second switching field 458.

An end field of the frame termination field 459 can contain at least one acknowledge bit. In addition, a sequence of 11 identical bits can be present, which indicate the end of the CAN XL frame 450. The at least one acknowledge bit can be used to indicate whether or not a receiver has discovered an error in the received CAN XL frame 450 or the message 45.

A sender of the message 45 begins sending bits of the data phase 452 to the bus 40 only when the subscriber station 10 as the sender has won the arbitration and the subscriber station 10 as the sender thus has exclusive access to the bus 40 of the bus system 1 for sending.

Thus, in the arbitration phase 451 as the first communication phase, the subscriber stations 10, 30 partially use, in particular up to the FDF bit (inclusive), a format known from CAN/CAN-FD in accordance with ISO11898-1:2015. However, compared to CAN or CAN FD in the data phase 452 as the second communication phase, an increase in the net data transmission rate is possible, in particular to over 10 megabits per second. In addition, an increase in the size of the payload data per frame is possible, in particular to around 2 kbyte or any other value.

As in 3 As shown, the transmitting/receiving devices 12 use a physical layer 451_P in the arbitration phase 451 to generate a transmit signal TxD ( 1 ) over time t as signals CAN_H, CAN_L on the bus 40. The same applies to the transmitting/receiving device 22. In contrast, the transmitting/receiving device 12 can use a physical layer 452_P in the data phase 452 that differs from the physical layer 451_P to transmit the transmit signal TxD ( 1 ) as signals CAN_H, CAN_L on the bus 40, as already described above. There are two operating modes for the physical layer 452_P, namely FAST_TX and FAST RX, as described in more detail below.

3 shows on the left that the subscriber stations 10, 20, 30 in the arbitration phase 451 each send signals CAN_H, CAN_L over time t to the bus 40, which have a first bit duration t_bt1. The signals CAN_H, CAN_L are serial signals and alternately have at least one dominant State 401, where VCAN_H = 3.5 V and VCAN_L = 1.5 V, or at least one recessive state 402, where VCAN_H = VCAN_L = 2.5. Dominant states 401 are driven in phase 451 with NRZ coding of the transmit signal TXD if TXD = 0 or L (LOW). Recessive states 402 are generated or arise in phase 451 with NRZ coding of the transmit signal TXD if TXD = 1 or H (HIGH). After arbitration in arbitration phase 451, one of the subscriber stations 10, 20, 30 is determined to be the winner.

If the subscriber stations 10, 20, 30 detect the signaling in the first switching field 455 of 3 For switching from the first to the second communication phase 451, 452, the respective transmitting/receiving device 12 switches its physical layer 451_P at the end of the arbitration phase 451 from a first operating mode (SLOW), which can also be implemented as a SIC operating mode, to the physical layer 452_P of the data phase 452. For this purpose, the operating modes of the data phase 452 are switched on.

If, for example, the first subscriber station 10 has won the arbitration, the transmitting/receiving device 12 of the subscriber station 10 switches, in particular due to a signal in the first switching field 455 from 2 , converts its physical layer 451_P at the end of the arbitration phase 451 from the first operating mode (SLOW) to the physical layer 452_P of the data phase 452 for a second operating mode (FAST_TX) of the transmitting/receiving device 12, since the subscriber station 10 is the sender of the message 45 in the data phase 452. As in 3 shown, the transmitting module 121 then generates the states L0 or L1 with the physical layer 452_P for the signals CAN_H, CAN_L on the bus 40 in the data phase 452 or in the second operating mode (FAST_TX) depending on a transmitting signal TxD one after the other and thus serially. In contrast, the transmitting/receiving device 12 of the subscriber station 30 switches its physical layer 451 _P at the end of the arbitration phase 451 from the first operating mode (SLOW or SIC) to the physical layer 452_P of the data phase 452 for a third operating mode (FAST_RX) of the transmitting/receiving device 12, since the subscriber station 30 is only a receiver, i.e. not a transmitter, of the frame 450 in the data phase 452.

The frequency of the signals CAN_H, CAN_L can be increased in the data phase 452. In the example of 3 For this purpose, the bit time or bit duration t_bt2 in the data phase 452 is shorter or less than the bit time or bit duration t_bt1 in the arbitration phase 451. Thus, the net data transmission rate in the data phase 452 in the example of 3 increased compared to the arbitration phase 451.

If the transmitting/receiving device 12, in particular with the signaling in the second switching field 458 of 2 that a switchover from the data phase 452 back to the arbitration phase 451 is to be made, the transmitting/receiving device 12 is switched from transmitting (operating mode FAST_TX) (and)or receiving (operating mode FAST_RX) signals with the physical layer 452_P to transmitting and/or receiving signals with the physical layer 451_P. Thus, after the end of the data phase 452, all transmitting/receiving devices 12 switch their operating mode to the first operating mode (SLOW or SIC). Thus, all transmitting/receiving devices 12 can not only switch between the bit durations t_bt1, t_bt2, but also switch their physical layer, as previously described.

According to 4 In the arbitration phase 451, a difference signal VDIFF = CAN_H - CAN_L with values of VDIFF = 2V for dominant states 401 and VDIFF = 0V for recessive states 402 is ideally formed on the bus 40 over time t. The course of VDIFF in phase 451 is shown on the left side in 4 In contrast, in the data phase 452, a difference signal VDIFF = CAN_H - CAN_L is formed on the bus 40 over time t, corresponding to the states L0, L1 of 4 as shown on the right in 4 shown. The state L0 has a value VDIFF = 1V. The state L1 has a value VDIFF = -1V.

The receiving module 122 can distinguish the states 401, 402 with two of the receiving thresholds T1, T2, T3, which lie in the ranges TH_T1, TH_T2, TH_T3. For this purpose, the receiving module 122 samples the signals from 3 or 4 at times t_A, as in 4 shown. To evaluate the sampling result, the receiving module 122 in the arbitration phase 451 uses the receiving threshold T1 of, for example, 0.7 V and the receiving threshold T2 of, for example, -0.35 V. In contrast, the receiving module 122 in the data phase 452 only uses signals that were evaluated with the receiving threshold T3. When switching between the first to third operating modes (SLOW or SIC, FAST_TX, FAST_RX), which were previously defined with respect to 3 described, the receiving module 122 switches the receiving thresholds T2, T3 respectively.

The reception threshold T2 is used to detect whether the bus 40 is free when the subscriber station 12 is newly connected to the communication on the bus 40 and attempts to integrate itself into the communication on the bus 40.

Upon receipt of the corresponding signals from the bus 40, each transmitting/receiving device 12 generates the associated receive signal RxD, as shown in 1 shown. The received signal RxD ideally has no time offset to the transmitted signal TxD.

5 shows an example of a part of the digital transmission signal TxD, which the transmission module 121 receives in the arbitration phase 451 from the communication control device 11, and from which it generates the signals CAN_H, CAN_L for the bus 40. In 5 the transmit signal TxD changes from a state LW (Low) to a state HI (High) and back to the state LW (Low).

As in 6 As shown in more detail, the transmitting module 121 generates the transmit signal TxD of 5 the signals CAN_H, CAN_L for the bus wires 41, 42 such that a state 403 (sic) is also present. The state 403 (sic) can have different lengths, as shown with the state 403_0 (sic) during the transition from the state 402 (rec) to the state 401 (dom) and the state 403_1 (sic) during the transition from the state 401 (dom) to the state 402 (rec). The state 403_0 (sic) is shorter in time than the state 403_1 (sic). In order to transmit signals according to 6 To generate the signal, the transmitter module 121 is switched to a SIC operating mode (SIC mode).

Passing through the short sic state 403_0 is not required in CiA610-3 and the state depends on the type of implementation. The duration of the "long" state 403_1 (sic) is specified for CAN-SIC as well as for the SIC operating mode in CAN-XL as t_sic < 530ns, starting with the rising edge on the transmit signal TxD of 5 .

In the "long" state 403_1 (sic), the transmitter module 121 should adapt the impedance between the bus wires 41 (CANH) and 42 (CANL) as closely as possible to the characteristic wave impedance Zw of the bus line used. In this case, Zw=100 Ohm or 1200 hm. This adaptation prevents reflections and thus allows operation at higher bit rates. For simplicity, the following always refers to state 403 (sic) or sic state 403.

The transmitter module 121 can be used to generate signals for the bus 40 for the following CAN types: CAN-FD, CAN-SIC and CAN-XL. Table 1: CAN types for transmitter module 121 CAN type Communication phases/bit rate Bus states Transmitter module states CAN FD Arbitration dom, rec dom, sic, rec CAN-SIC Arbitration dom, sic, rec dom, sic, rec CAN-XL Arbitration or arbitration and data field in case no switch to fast mode occurs dom, sic, rec dom, sic, rec CAN-XL Data phase L0, L1 L0, L1

Thus, the transmit module state sic can be generated not only with CAN-SIC or CAN-XL (xl_sic). The transmit module state sic can also be generated with CAN-FD. In CAN-FD, however, the time for the transmit module state sic can be shorter than with CAN-SIC or CAN-XL.

7 shows an example of another part of the digital transmission signal TxD, which the transmission module 121 receives in the data phase 452 from the communication control device 11, and from which it generates the signals CAN_H, CAN_L for the bus 40. In 7 the transmit signal TxD changes several times from the HI state (high = high) to a LW state (low = low) and back to a HI state (high = high) and so on.

As in 8 As shown in more detail, the transmitting module 121 generates the transmit signal TxD of 7 the signals CAN_H, CAN_L for the bus wires 41, 42 such that the state L0 is formed for a state LW (Low). In addition, the state L1 is formed for a state HI (High).

9 shows the basic structure of the transmitter module 121 for one of the subscriber stations 10, 30. The transmitter module 121 can transmit signals CAN_H, CAN_L according to 3 with the states 401, 402, 403 and with the states L0, L1. Alternatively, the transmitter module 121 can generate signals CAN_H, CAN_L according to 6 with the states 401, 402, 403 and according to 8 with the states L0, L1. The transmitter module 121 has a control circuit 15 for adjusting a common-mode voltage V _CM for the low-impedance recessive state sic.

The transmission module 121 has four transmission stages, namely a first transmission stage 121A, a second transmission stage 121B, a third transmission stage 121C and a fourth transmission stage 121D. The transmission stages 121A to 121D are connected as an H-bridge or full bridge. The components of the transmission stages 121A to 121D, which are described in more detail below, are controlled via at least one control device 124. The at least one control device 124 sends at least one signal to control connections 125 to which the components of the transmission stages 121A to 121D are connected.

The transmitter module 121 is connected to the bus 40, more precisely via a CANH connection for the first bus wire 41 for CAN_H and via a CANL connection for its second bus wire 42 for CAN_L. Each of the transmitter stages 121A to 121D is connected to the bus 40.

The voltage supply for supplying the CANH, CANL connections for the first and second bus wires 41, 42 with electrical energy, in particular with the CAN supply voltage of usually 5V, is provided via at least one connection 43 of the transmitter module 121. The connection to ground or CAN_GND is realized via a connection 44.

The first and second bus wires 41, 42 are terminated with a terminating resistor 49. The terminating resistor 49 is connected in the full bridge as an external load resistor. The resistor 49 is connected in the bridge branch between the connections for the bus wires 41, 42.

The control circuit 15 is connected to the transmission stages 121A to 121D. The control circuit 15 is not directly connected to the bus 40, but via the transmission stages 121A to 121D.

The control circuit 15 of 9 For the low-impedance recessive state, sic carries out a control with which a common-mode voltage V _CM is independent of the bus signal or the differential voltage VDIFF of, for example, 4 on the bus 40 always remains at exactly the same value. This reduces the interference caused by the transmitter module 121, which would be caused by a variation in this common mode voltage V _CM . This makes it possible to meet the CAN specifications (ISO11898-2:2016, CiA601-4, CiA610-3) and the EMC standard (IEC62228-3).

For this purpose, the control circuit 15 has a differential amplifier 151, a replica 152 of the output stage of the transmitter stage 121 and a control transistor MN _CTRL . According to 9 the replica 152 has a series circuit of a transistor MP _R , a diode MN _DIOPR , a transistor MP _CASPR , a diode MN _DIONR , a transistor MP _CASNR and a transistor MN _R . The replica 152 is a replica of the output stage of the transmitter stage 121, which has a transistor MP ₀ , a diode MN _DIOPH , a transistor MP _CASPH , a diode MN _DIONH , _a transistor MP _CASNH and a transistor MN ₀ . The above-mentioned components of the output stage of the transmitter stage 121 are components for the transmitter stages 121A, 121D, which are described in more detail below.

According to 9 the differential amplifier 151 compares the common-mode voltage V _CM with a target common-mode voltage V _REF . The common-mode voltage VCM is tapped at a common-mode point or tapping point 157 of the replica 152. A comparison voltage ΔV = V _REF - V _CM is thus present at the input of the differential amplifier 151. The required adjustment voltage for the currents I _CTRL , I _BIAS results from the comparison voltage ΔV. In particular, V _REF = 2.5 V = 5 V/ 2 = CAN_SUPPLY/2.

In order to keep the power consumption in the replica 152 of the control circuit 15 low, all components in the replica 152, i.e. the transistor MP _R , the diode MN _DIOPR , the transistor MP _CASPR , the diode MN _DIONR , the transistor MP _CASNR and the transistor MN _R , should be or have scaled sizes of the components of the output stage of the transmission stage 121. In particular, the sizes of the components in the replica kum 152 is a factor of 100 smaller than the sizes of the components of the output stage of the transmitting stage 121. Of course, a different factor can be selected. It is important that the replica 152 consists of the same component types as those used in the output stage of the transmitting stage 121. In addition, the replica 152 should match the output stage of the transmitting stage 121 both thermally and in terms of alignment. The term "alignment", which can also be referred to as orientation, is to be understood here as the spatial alignment in the layout on the chip in or with which the transmitting stage 121 is constructed. Influences such as temperature or a piezo effect, which cause elastic deformation, can require that the control circuit 15 should be in the same alignment as the output stage of the transmitting stage 121. In particular, the replica 152 and the output stage of the transmitting stage 121 have the same temperature and the same alignment or orientation. The control transistor MN _CTRL can be chosen to be identical in size and orientation to the transistor MN _MIR , which results in the balancing current or bias current I _BIAS . The transistor MN _MIR can also be referred to as the mother transistor MN _MIR of the bias current I _BIAS .

When switching 9 Thus, the common mode point or tapping point 157 of the replica 152 obtained with the control circuit 15 is at the common mode voltage of the output of the transmission stages 121A, 121D, i.e. the common mode voltage V _CM , and can be compared with the reference voltage V _REF . For example, the common mode voltage V _CM of the output of the transmission stages 121A, 121D is the common mode voltage V _cm = (VCAN_H + VCAN_L) / 2. The gate voltage of the control transistor MN _CTRL , which can be selected to be identical to the mother transistor MN _MIR of the bias current I _BIAS in terms of size and alignment or orientation, then results in the regulated bias current I _CTRL = I _BIAS + g ΔV on the CANH side, where g is the gain of the differential amplifier 151.

The bandwidth of the control loop of the control circuit 15, in particular the bandwidth of the differential amplifier 151, is selected such that within the bit duration t_bt1 or t_bt2, which 3 shown, an adjustment of the common mode voltage V _CM for the low-impedance recessive state sic is carried out.

The replica 152 makes it possible to determine the (undisturbed) common mode voltage V _CM , which also reflects the process and temperature dependencies of the outputs of the transmitter stage 121.

With the control circuit 15 of 9 In the current-controlled H-bridge of the transmitter stage 121, the common-mode voltage V _CM is obtained by matching the current I _CTRL on the CANH side, which can also be referred to as the high side, and the current I _BIAS on the CANL side, which can also be referred to as the low side. Particularly in the low-impedance recessive state (SIC state), the precise matching of the currents I _CTRL , I _BIAS requires a very fine and possibly even temperature-dependent tuning of the currents I _CTRL , I _BIAS , taking into account the leakage currents due to temperature and process fluctuations. The tuning can be derived from a temperature sensor and stored tuning data.

This means that it is not necessary to determine the common mode voltage V _CM by tapping the bus 40. However, such a tapping would have the disadvantage that the tapping would again have to meet the requirements for overvoltages and currents at the tapping point. However, meeting these requirements is very difficult because the actual common mode (V_CANH+V_CANL)/2 can have considerable amplitudes (up to +/- 60V) in the case of irradiation (DPI) on the bus 40.

To send the signals CAN_H, CAN_L according to 3 or the signals CAN_H, CAN_L according to 6 or according to 8 The transmitting stages 121A, 121B, 121C, 121D are constructed as follows.

The first transmitter stage 121A of 9 has n current step switches which can be switched between a first position 0 and a second position 1 and are connected to the drain terminal of transistors MP _MIR , MP _R , MP,0 MP ₁ , MP ₂ to MP _n . n is a natural number > 1. The n current step switches can be switched at a frequency f _MAIN . The n current step switches can be connected in their position 1 to the anode of a polarity reversal diode MN _DIOPH . A source terminal of a transistor MP _CASPH is connected to the cathode of the polarity reversal diode MN _DIOPH . The drain terminal of the transistor MP _CASPH is connected to the CANH terminal for the bus wire 41. The gate terminal of the transistor MP _CASPH is connected to a control terminal 125 to which the control device 124 can apply a control voltage V _PCAS . The transistors MP _MIR , MP _R form a current mirror for a first to a-th current stage S1 to Sn, which supply electrical currents I1 to In via the n current stage switches of the first transmission stage 121A, as can be seen in more detail from 10 In addition, a control circuit T_A is available, which controls the n current step switches using the transmission signal TxD ( 1 ) which is fed from a TXD terminal. The Control circuit T_A controls the n current step switches according to the transmission signal TxD and the set operating mode SIC, FAST_TX of the transmission module 121.

The transistors MP _MIR , MP _R , MP,0 MP ₁ , MP ₂ to MP _n can be CMOS transistors, in particular PMOS transistors. The transistors MP _MIR , MP _R , MP,0 MP ₁ , MP ₂ to MP _n , are in the example of 1 normally blocking p-channel transistors. The transistor MP _CASPH can be a CMOS transistor, in particular a PMOS transistor. The transistor MP _CASPH is in particular a cascode to meet the requirements for feedback resistance in the event of overvoltages or undervoltages at the CANH terminal. The abbreviation "CMOS" refers to a semiconductor element in which both p-channel and n-channel MOSFETs are used on a common substrate. The abbreviation CMOS stands for "complementary metal-oxide semiconductor". The abbreviation "MOSFET" stands for metal-oxide field-effect transistor.

The second transmitter stage 121B of 9 has n current step switches which can be switched between a first position 0 and a second position 1 and are connected to the drain connection of transistors MN _MIR , MN _R , MN ₀ , MN ₁ , MN ₂ to MN _n . n is the natural number > 1. The n current step switches can be switched with a frequency f _COMPL . The n current step switches can be connected in their position 1 to the source connection of a transistor MN _CASNH . The drain connection of the transistor MN _CSANH is connected to the cathode of a polarity reversal diode MN _DIONH . The connection CANH for the bus wire 41 is connected to the anode of the polarity reversal diode MN _DIONH . The gate connection of the transistor MN _CASNH is connected to a control connection 125 to which the control device 124 can apply a control voltage V _NCAS . The transistors MN _MIR , MN _R form a current mirror for a first to n-th current stage S1 to Sn, which supply the electrical currents I1 to In via the n current stage switches of the second transmission stage 121B, as can be seen in more detail from 10 In addition, a control circuit T_B is available, which controls the n current step switches using the transmission signal TxD ( 1 ) which is fed from a connection TXD. The control circuit T_B controls the n current step switches according to the transmission signal TxD and the set operating mode SIC, FAST_TX of the transmission module 121.

The transistors MN _MIR , MN _R , MN ₀ , MN ₁ , MN ₂ to MN _r , can be CMOS transistors, in particular NMOS transistors. The transistors MN _MIR , MN _R , MN ₀ , MN ₁ , MN ₂ to MN _r , are in the example of 1 normally blocking n-channel transistors. The transistor MN _CASNH can be a CMOS transistor, in particular an NMOS transistor. The transistor MN _CSANH is in particular a cascode to meet the requirements for feedback immunity in the event of over- or undervoltages at the CANH terminal.

The third transmitter stage 121C of 9 has n current step switches which can be switched between a first position 0 and a second position 1 and are connected to the drain connection of the transistors MP _MIR , MP _R , MP,0 MP ₁ , MP ₂ to MP _n . The n current step switches can be switched at a frequency f _COMPL . The n current step switches can be connected in their position 1 to the anode of a polarity reversal diode MN _DIOPL . A source connection of a transistor MP _CASPLH is connected to the cathode of the polarity reversal diode MN _DIOPL . The drain connection of the transistor MP _CASPL is connected to the CANL connection for the bus wire 42. The gate connection of the transistor MP _CASPL is connected to the control connection 125 to which the control device 124 can apply the control voltage V _PCAS . The transistors MP _MIR , MP _R form a current mirror for a first to n-th current stage S1 to Sn, which supply the electrical currents I1 to In via the n current stage switches of the third transmission stage 121C, as can be seen in more detail from 10 In addition, a control circuit T_C is available, which controls the n current step switches using the transmission signal TxD ( 1 ) which is fed from a connection TXD. The control circuit T_C controls the n current step switches according to the transmission signal TxD and the set operating mode SIC, FAST_TX of the transmission module 121.

The transistor MP _CASPL can be a CMOS transistor, in particular a PMOS transistor. The transistor MP _CASPL is in particular a cascode for meeting the requirements for feedback immunity in the event of overvoltages or undervoltages at the CANL terminal.

The fourth transmitter stage 121D of 9 has n current step switches that can be switched between a first position 0 and a second position 1 and are connected to the drain terminal of the transistors MN _MIR , MN _R , MN ₀ , MN ₁ , MN ₂ to MN _r . n is the natural number > 1. The n current step switches can be switched with a frequency f _MAIN . The n current step switches can be connected in their position 1 to the source terminal of a transistor MN _CASNL . The drain terminal of the transistor MN _CASNL is connected to the cathode of a polarity reversal diode MN _DIONL . The CANL terminal for the bus wire 42 is connected to the anode of the polarity reversal diode MN _DIONL . The gate terminal of the transistor MN _CASNL is connected to the control terminal 125, to which the control device 124 can apply the control voltage V _NCAS . The transistors MN _MIR , MN _R form a current mirror for a first to n-th current stage S1 to Sn, which supply the electrical currents I1 to In via the n current stage switches of the fourth transmission stage 121D, as can be seen in more detail from 10 In addition, a control circuit T_D is available, which controls the n current step switches using the transmission signal TxD ( 1 ) which is fed from a connection TXD. The control circuit T_B controls the n current step switches according to the transmission signal TxD and the set operating mode SIC, FAST_TX of the transmission module 121.

The transistor MN _CASNL can be a CMOS transistor, in particular an NMOS transistor. The transistor MN _CASNL is in particular a cascode for meeting the requirements for feedback immunity in the event of overvoltages or undervoltages at the CANL terminal.

The number n can be chosen arbitrarily. In particular, the number n and thus the number of stages or number of current step switches can be selected between 1 and 60.

Alternatively, however, n can be chosen to be a number greater than 60 or a number smaller than 60, in particular 30.

A resistor R_H is connected between the transmitting stages 121A, 121C. One end of the resistor R_H is connected to the anode of the polarity reversal diode MN _DIOPH and can be connected to the drain terminal of the transistors MP _MIR , MP _R , MP,0 MP ₁ , MP ₂ to MP _n via the current step switches of the transmitting stage 121A. The other end of the resistor R_H is connected to the anode of the polarity reversal diode MN _DIOPL and can be connected to the drain terminal of the transistors MP,0 MP ₁ , MP ₂ to MP _n via the current step switches of the transmitting stage 121C.

A resistor R_L is connected between the transmission stages 121D, 121B. One end of the resistor R_L is connected to the source terminal of the transistor MN _CASNH and can be connected to the drain terminal of the transistors MN _R , MN ₀ , MN ₁ , MN ₂ to MN _r , via switches of the fourth transmission stage 121D. The other end of the resistor R_L is connected to the source terminal of the transistor MN _CASNL and can be connected to the drain terminal of the transistors MN _R , MN ₀ , MN ₁ , MN ₂ to MN _r , via the current level switches of the second transmission stage 121B.

Each of the polarity reversal diodes MN _DIOPH , MN _DIONL , MN _DIOPL , MN _DIONH protects the associated transmitting stage 121A, 121B, 121C, 121D against positive feedback to connection 43 (CAN supply) and negative feedback to connection 44 (CAN_GND). Each of the polarity reversal diodes MN _DIOPH , MN _DIONL , MN _DIOPL , MN _DIONH can also be referred to as a blocking diode.

Each of the transmission stages 121A, 121B, 121C, 121D, or more precisely their current step switch with the associated control circuit T_A, T_B, T_C, T_D, sets a transmission current value for the associated transmission stage 121A, 121B, 121C, 121D depending on the operating mode for the arbitration phase 451 or data phase 452 of the transmission module 121 and the transmission signal TxD. Explanations for this are also included in the preceding Table 1. The transmission current value of the individual transmission stage 121A, 121B, 121C, 121D can thus be set depending on the operating mode, such as arbitration (SLOW or SIC) or data phase (FAST_TX or FAST_RX) of the transmission module 121 and the transmission signal TxD. Each transmission stage 121A to 121D is thus designed to set the value of the electrical current IA1 to IAn etc. output by the transmission stage 121A to 121D during operation of the transmission module 121 at the input of the current mirror that is present in the respective transmission stages 121A to 121D. The electrical currents IA1 to IAn etc. can also be referred to briefly as I1 to In. The setting of the transmission current values is explained in more detail below using 10 and 11 for the electrical currents I1 to In the individual step circuits 121A1, 121B1, 121C1, 121D1 and Table 2.

Each of the transistors MN _CASPH , MN _CASNL , MN _CASPL , MN _CSANH may also be called an HV standoff device. Each of the transistors MN _CASPH , MN _CASPL protects the CMOS transistors MP _MIR , MP _R , MP ₀ MP ₁ , MP ₂ through MP _n of the current mirror for the transmit stages 121A, 121C by having the transistors MN _CASPH , MN _CASPL absorb high voltage drops. Each of the transistors MN _CASNH , MN _CASNL protects the CMOS transistors MN _MIR , MN _R , MN ₀ , MN ₁ , MN ₂ through MN _r , of the current mirror for the transmit stages 121D, 121B by having the transistors MN _CASPH , MN _CASPL absorb high voltage drops. The HV cascodes or transistors MN _CASPH , MN _CASNL , MN _CASPL , MN _CASNH enable compliance with limit values (maximum rating parameters), such as voltage at CANH and CANL -27V to +40V.

In the transmitter module 121, the transmitter stage 121A is connected between the connection 43 for the power supply and the connection 41 (CANH) for the CAN_H signal. The transmitter stage 121C is connected between the connection 43 for the power supply and the connection 42 (CANL). The transmitter stage 121D is connected between the connection 41 (CANH) for the CAN_H signal and the connection 44 for ground or the connection 44 (CAN_GND). The transmitter stage 121B is connected between the connection 42 (CANL) for the CAN_L signal and the connection 44 for ground or the connection 44 (CAN_GND). In the transmitter module 121, the transmitter stage 121A is thus connected to the CANH path. The transmitter stage 121D is also connected to the CANH path. On the one hand, the transmitting stage 121C is connected to the CANL path. On the other hand, the transmitting stage 121B is connected to the CANL path.

Thus, the transmitting module 121 has parallel connections of a specific number of switchable currents of the transmitting stages 121A, 121B, 121C, 121D in the CANH path and in the CANL path. The current value of the transmitting stages 121A, 121B, 121C, 121D is determined by the number of current step switches of the transmitting stages 121A, 121B, 121C, 121D switched to position 1.

10 shows as an example the structure of the first to n-th current step switch S1 to Sn of the transmitting stage 121D. Accordingly, the first current step switch S1 has a current source IrefD1. The second current step switch S2 has a current source IrefD2. The n-th current step switch Sn has a current source IrefDn. Optionally, at least one of the current sources IrefD1 to IrefDn is a current sink.

The current step switches of the transmitting stages 121A, 121B, 121C are constructed in the same way.

The functionality of the circuit of 9 , which circuits according to 10 is explained in the following Table 2 depending on the operating mode of the transmitting module 121 and the bus state 401 (dom), 403 (sic), 402 (rec) in the SIC operating mode (arbitration phase 451) and the bus state L0, L1 in the data phase 452. Depending on the state of the transmitting module 121 and the operating mode of the transmitting module 121 in the phases 451, 452, Table 2 indicates the required impedance as well as the impedance of the transmitting stages 121A/121B and impedance of the transmitting stages 121C/121D. In addition, depending on the state of the transmitter module 121 and the operating mode of the transmitter module 121, the driver current of the transmitter stages 121A/121B and the transmitter stages 121C/121D is specified in the phases 451, 452. The driver current of the transmitter stages 121A/121B and the transmitter stages 121C/121D is supplied by the associated current step switches S1 to Sn.

If the impedance is “infinite”, the transmitter module 121 or the respective transmitter stage 121A, 121B, 121C, 121D is switched off or not conductive.

In the transmitter stage 121, the resistors R_H and R_L are used to set the differential resistance between the CANH, CANL connections during the transmitter module state (SIC state). The resistors R_H, R_L each have the value 240 ohms, for example. The aim is to set an impedance of 120 ohms according to the characteristic impedance Zw of the bus wires 41, 42. In contrast, the impedance of the current mirrors of all four transmitter stages 121A, 121B, 121C, 121D can be selected to be significantly greater than 240 ohms. In simple terms, this leads to a parallel connection of the two 240 ohm resistors and thus to an adjusted impedance of 120 ohms.

In addition, the transmitter stage 121 can be used to set a differential resistance between the CANH, CANL connections even in state 401 (dom), which matches the characteristic impedance of the bus wires 41, 42, each of typically 120 ohms. This avoids reflections in state 401 (dom).

The described design of the transmitting stage 121 prevents a supply voltage of > 5V from being necessary at the connection 43, which is not possible due to system requirements or requirements of the CAN specifications. However, this would be necessary if the advantageous behavior described above were to be achieved with a solution with a resistance concept in the transmitting stages 121A, 121B, 121C, 121D.

An additional advantage of the described design of the transmitting stage 121 is that the current which flows in the two paths of the transmitting stages 121A/D and 121B/C during the state 403 (sic) can be set arbitrarily or “freely”, as indicated in Table 1.

The division of each transmission stage 121A, 121B, 121C, 121D of 9 into n parts or the n current stages of the current step switches allows a time-staggered and controlled switching process between the bus states 401, 402, 403 in the arbitration phase (SIC operating mode) 451 or the bus states L0, L1 of the data phase 452. In particular, the current values of the n current stages of the current step switches are set as with 11 illustrated in a specific example.

11 shows an example of the current level per switching stage or the current stage switches S1 to S12. Thus, in the example shown, twelve of the current stages or current stage switches S1, S2 to S6 to S12 are used for each of the transmission stages 121A, 121B, 121C, 121D. The current stages or current stages switches S1, S2 to S6 to S12 are connected to the corresponding transistors MP _MIR , MP _R , MP ₀ MP ₁ , MP ₂ to MP _n of the current mirror for the transmitting stages 121A, 121C of 9 or the associated transistors MN _MIR , MN _R , MN ₀ , MN ₁ , MN ₂ to MN _r , of the current mirror for the transmitting stages 121D, 121B of 9 can be switched on or off. In the example of 11 so n = 12.

The value of the current I (vertical axis in 11 ) or I1, I2, I6, I12 etc. is set by selecting the value of the electrical current of the respective current stage or current stage switch S1 to S12. The individual current stages or current stage switches S1 to S12 (horizontal axis in 12 ) thus have current sources IrefD1, IrefD2 to IrefDn, which supply an electric current with different current values.

To generate the bus states 401, 402, 403 in the arbitration phase 451 or the bus states L0, L1 of the data phase 452 according to Table 2, the individual current stages S1 to S12 are switched on or off at different times using the control circuits T_A, T_B, T_C, T_D of the transmission stages 121A, 121B, 121C, 121D. As a result, a corresponding electrical current I flows in the CANH path or CANL path into which the transmission stage 121A, 121B, 121C, 121D is connected.

In general, it is advantageous to design the staggering stages per switching stage or current stage S1 to S12 in such a way that the shape of the difference signal VDIFF follows the Gaussian error function. This produces the lowest possible emission analytically.

For example, for the transition from a state 402 (recessive) to a state 401 (dominant), which corresponds to a rising edge of the differential voltage VDIFF of 4 corresponds to the time-staggered switching on of the current stages of the transmitting stages 121A, 121B, 121C, 121D, the current in the CANH path and in the CANL path can be increased step by step to generate a dominant level on the bus 40. The transition from a state 401 (dominant) to a state 402 (recessive), which corresponds to a falling edge of the differential voltage VDIFF of 4 is carried out by switching off the current stages of the transmit stages 121A, 121B, 121C, 121D at different times, whereby the current in the CANH and CANL path is gradually reduced. The total current, which is given by the sum of the currents I1 to I12 or I1 to In of all current stages S1 to Sn, flows during state 401 (dominant). Here, all current stages S1 to Sn of the transmit stages 121A, 121B, 121C, 121D are switched on and the total current for generating the dominant level of nominal VDIFF = 2V flows through the bus resistor or terminating resistor 49.

By means of the time control it is possible to adjust the signal shape of CAN_H and CAN_L as per 6 required. Targeted shaping of the signal curves for CAN_H and CAN_L is possible. Overall, the bus states 401, 402, 403 in the arbitration phase 451 or the bus states L0, L1 of the data phase 452 can be shaped depending on the specifications.

The currents of the individual current stages S1 to Sn of the transmission stages 121A, 121B, 121C and thus their respective share of the total current can be selected in different ways in order to achieve the lowest possible emission, in particular a low emission of the transmission module 121. It is advantageous for low emission to switch little current on or off at the beginning and end of a switching process between bus states 401, 402 and to switch a lot of current on or off in the middle of the switching process. Therefore, the 11 shown setting of the currents I1, I2 to In the current stages S1 to S12 is very advantageous.

In contrast to an implementation with identical current sources in the current stages S1 to Sn of the transmission stages 121A, 121B, 121C, the configuration according to 9 to 11 a current increase during switch-off, the transition from state 401 (dominant) to state 402 (recessive).

The granularity of the temporal staggering for switching the individual current stages S1 to S12 on or off is in a range of about 2 ns. Such small stages or steps for the temporal staggering cause a low common mode interference and have a small negative impact on the emission. The current steps, which are set via the current stages S1, S2 to S6 to S12, are kept fixed and the temporal staggering is varied so that the behavior during the switch-on process is as smooth as possible (according to the Gaussian error function). The variation of the time steps or time stages also prevents the occurrence of a narrow-band frequency line in the emission frequency spectrum.

Alternatively, the staggering steps can be carried out using fixed time steps and varied current steps.

The structure of the transmitter module 121 shown enables symmetrical switching of the bus signals CAN_H and CAN_L ( 6 ) with steep switching edges between the bus states 401, 402, 403 in the arbitration phase (SIC operating mode) 451 or the bus states L0, L1 of the data phase 452.

On the one hand, the structure of the transmitter module 121 shown, due to the use of fast CMOS switches or CMOS transistors, enables much steeper switching edges between the bus states 401, 402, 403 in the arbitration phase (SIC operating mode) 451 or the bus states L0, L1 of the data phase 452. On the other hand, the symmetry of the temporal progression of the bus signals CAN_H and CAN_L required to comply with the emission limits is achieved during the switching processes. Matching of the characteristic curves is achieved by selecting or using the current sources of the step circuits 121A1, 121B1, 121C1, 121D1. The matching of the characteristic curves is therefore less dependent on the parameters of the transistors used in the step circuits 121A1, 121B1, 121C1, 121D1.

The dominant state 401 (dom) is determined by matching the step circuit 121A1 with the step circuit 121B1. Here and also in the following, the term "matching" means an active trimming step according to one possibility. According to another possibility, "matching" means that the values of the current sources of the step circuits 121A1, 121B1 match as well as possible, which is done by default without a matching step or trimming step.

The Sic state (sic) is determined by matching the step circuit 121A1 with the step circuit 121C1 and matching the step circuit 121D1 with the step circuit 121B1.

In the XL-Fast operating mode, the state L0 is determined by matching the step circuit 121A1 with the step circuit 121B1. The state L1 is determined by matching the step circuit 121C1 with the step circuit 121D1.

The following Table 3 shows an example of the values a, b, c, d, z that are used for the transmitter module 121 of 9 to generate the respective transmission module states. The value a indicates how many current step switches of the first transmission stage 121B are switched to conductive. The value b indicates how many current step switches of the second transmission stage 121B are switched to conductive. The value c indicates how many current step switches of the third transmission stage 121C are switched to conductive. The value d indicates how many current step switches of the fourth transmission stage 121D are switched to conductive. The value z indicates how many transistors of the transistors MP ₁ to MP _n , and how many transistors of the transistors MN ₁ to MN _r , are switched to conductive. Table 3 thus shows an example of how many parallel-connected current step switches of each transmission stage 121A, 121B, 121C, 121D are each conductive in order to set the corresponding states of the transmission module 121 (transmitter states). As can be seen from Table 3, for example, in the arbitration phase to drive a state 401 (dom), a number of 60 transistors MP and a number of 60 transistors MN as well as a number of 60 current step switches of the first transmission stage 121A and a number of 60 current step switches of the second transmission stage 121B are switched to conductive. Table 3: Required number of parallel-connected switching transistors for the transmission stages 121A, 121B, 121C, 121D depending on the state of the transmission module 121 (transmitter state). Operating mode of the transmitter module 1210 Transmitter module status VDIFF transmit level (V) e a b c d Arbitration phase operating mode (SIC, xl_sic) cathedral 2 60 60 60 0 0 sic 0 60 30 30 30 30 Rec 0 60 0 0 0 0 Data phase operating mode (Fast-TX, xl_fasttx) level0 1 60 30 30 0 0 level1 -1 60 0 0 30 30

The described transmitting module 121 enables a time-staggered and controlled switching process by dividing its four transmitting stages 121A, 121B, 121C, 121D into n parts. Switching on according to the Gaussian error function can be implemented. This enables a smooth behavior to be set during the switch-on process. In addition, the possible variation of time stages during switch-on prevents the occurrence of a narrow-band frequency line in the emitted frequency spectrum.

Alternatively, it is possible to carry out a staggered and controlled switching process using fixed time steps and varied voltage steps using the described transmitter module 121. This can also influence the emission behavior of the transmitter module 121 in such a way that the specified limit values are adhered to.

In addition, the described transmission module 121 can reduce effects due to asymmetrical behavior of the transmission stages 121A, 121B, 121C, 121D, which can occur in the transmission states dom, sic, rec and degrade the emission. The transmission module 121 prevents unequal behavior of components in transmission stages 121A, 121B (effect 1) of a full bridge, so that in the dom state a change in the common mode voltage is minimized or prevented compared to the rec state. In addition, the transmission module 121 can prevent unequal behavior of components in transmission stages 121A/121D and 121C/121B of the full bridge (effect 2), so that in the sic state a change in the common mode voltage is minimized or prevented compared to the rec state. This is particularly advantageous because only if, starting from the common mode level of the rec state, the common levels in the dom state and in the sic state match those of the rec state, a sufficient emission result can be achieved, but the causes leading to the behavior of effect 1 may be different from those leading to effect 2.

All previously described design variants of the transmission module 121 can also be used with a modified circuit topology of the full bridge. For example, the diodes can be arranged at a different location in the path to the connection 43. The cascodes can then be omitted and more voltage-resistant current step switches can be used in the transmission stages 121A, 121B, 121C, 121D.

12 shows the basic structure of a transmission module 1210 according to a second embodiment, which can be used for one of the subscriber stations 10, 30 instead of a transmission module 121 of the previous embodiment. The transmission module 1210 according to the present

The embodiment is constructed identically to the transmission module 121 of the previous embodiment except for the following differences.

The transmitter module 1210 has a control circuit 15A for adjusting the common mode voltage V _CM for bus states where VDIFF is not equal to 0V. Such bus states are, for example, the state VDIFF = 2V, which corresponds to the state 401 (dom), or the state VDIFF = 1V, which corresponds to the state level0 or L0, or the state VDIFF = -1V, which corresponds to the state level1 or L1, as previously described with respect to 3 and 4 as well as 6 and 8 described.

The control circuit 15A has a replica 153 in which a scaled bus load 1531 with two resistors R _DL1 , R _DL2 is arranged. The scaled bus load 1531 has a scaled size of the terminating resistor 49 of the bus 40. The scaled bus load 1531 has a size that is in particular smaller than the size of the terminating resistor 49 by a factor of 100 or another factor. In particular, the scaled bus load 1531 is an adjustable resistor.

Between the resistors R _DL1 , R _DL2 the replica 153 has a central tapping point which is equal to the common mode point or tapping point 157. The resistors R _DL1 , R _DL2 have the same size, more precisely the same resistance value.

The replica 153 is otherwise constructed as previously described for the replica 152 of the transmission module 121 of the previous embodiment.

The bandwidth of the control loop of the control circuit 15A, in particular the bandwidth of the differential amplifier 151, is selected such that within the bit duration t_bt1 or t_bt2, which is 3 shown, an adjustment of the common mode voltage V _CM is carried out for bus states where VDIFF is not equal to 0V.

The replica 153 makes it possible to determine the (undisturbed) common mode voltage V _CM , which also reflects the process and temperature dependencies of the outputs of the transmitter stage 1210.

According to a first modification of the transmitter module 1210 of 12 At least two replicas 153 or at least two replicas 152, 153 are connected in parallel in the control circuit 15. In this way, for the adjustment in at least two of the possible bus states, in particular all possible bus states 401 (dom), 402 (rec), 403 (sic), L0, L1 of 3 until 4 or 6 and 8 , several replicas can be used. In particular, a different replica 152 can be used for each bus state to be adjusted.

According to a second modification of the transmitter module of 12 At least two replicas are connected in parallel in the control circuit 15, whereby the replica is not only the output stage of the transmission stages 121A, 121D, but a replica of the entire full bridge. Such a replica is the output stage of the transmission stages 121A, 121B, 121C, 121D connected to the H-bridge (full bridge). In this way, too, for the adjustment in at least two of the possible bus states, in particular all possible bus states 401 (dom), 402 (rec), 403 (sic), L0, L1 of 3 until 4 or 6 and 8 , multiple replicas can be used.

13 shows the basic structure of a transmission module 1211 according to a third embodiment, which can be used for one of the subscriber stations 10, 30 instead of a transmission module 121, 1210 of the previous embodiments. The transmission module 1211 according to the present embodiment is constructed identically to the transmission module 1210 of the previous embodiment, except for the following differences.

The transmission module 1211 has a control circuit 15B with switchable bus load 1531 in a replica 153A. For this purpose, the replica 153A has a switching unit 1532 and a connection 1533 into which a control signal sic can be input to control the switching unit 1532. The control signal sic can be output, for example, by the control device 124.

In the state with bus voltage VDIFF =0V, which corresponds to the SIC state 403 of 6 , the logic signal sic=1 is switched to terminal 1534. This short-circuits the scaled bus load 1531.

What is important in this implementation is a smooth switching between the control states, in particular on the signal sic at the terminal 1534. This smooth switching can be achieved, for example, by less steep edges in the signal sic. Additionally or alternatively, the soft switching can be brought about by an appropriate bandwidth of the differential amplifier 151.

The replica 153A is otherwise constructed as previously described for the replica 153 of the transmit module 121 of the previous embodiment.

Thus, the control circuit 15B can be used to adjust the common mode voltage V _CM for bus states in which VDIFF is equal to 0V or not equal to 0V. Such bus states are, for example, the sic state (VDIFF = 0 V) or the state VDIFF = 2V, which corresponds to the state 401 (dom), or the state VDIFF = 1V, which corresponds to the state level0 or L0, or the state VDIFF = -1V, which corresponds to the state level1 or L1, as previously described with respect to 3 and 4 as well as 6 and 8 described.

The replica 153A can be used to determine the (undisturbed) common mode voltage V _CM , which also reflects the process and temperature dependencies of the outputs of the transmitter stage 1211. This applies to all previously mentioned bus states in which VDIFF is equal to or not equal to 0V.

Also in the case of the transmitting stage 1211, several replicas 152, 153, 153A are possible, as previously described with respect to the transmitting stage 1210.

14 shows the basic structure of a transmission module 1212 according to a fourth embodiment, which can be used for one of the subscriber stations 10, 30 instead of a transmission module 121, 1210, 1211 of the preceding embodiments. The transmission module 1212 according to the present embodiment is constructed identically to the transmission module 121 of the first embodiment, except for the following differences.

The transmitting module 1212 has transmitting stages 121A1, 121B1, 121C1, 121D1, each of which is constructed as a resistive transmitting stage. As a result, only transistors MP _CURR and MN _CURR are present as current limiters. However, the control circuit 15 is constructed as previously described with respect to the transmitting module 121.

The transistor MP _CURR causes a current I _HS that flows from the transistor MP _CURR into the full bridge to the transmitting stages 121A, 121C to be smaller than a predetermined value. In particular, I _HS < 115 mA applies. The transistor MN _CURR causes a current I _LS that flows from the full bridge from the transmitting stages 121D, 121B into the transistor MN _CURR to be smaller than a predetermined value. In particular, I _LS < 115 mA applies.

The first transmitter stage 121A1 has resistors R_M_HS, which are each connected to the current step switches of the transmitter stage 121A1, as shown in 14 shown. The second transmission stage 121B1 has resistors R_M_LS, each of which is connected to the current step switches of the transmission stage 121B1. The third transmission stage 121C1 has resistors R_C_LS, each of which is connected to the current step switches of the transmission stage 121C1. The fourth transmission stage 121D1 has resistors R_C_HS, each of which is connected to the current step switches of the transmission stage 121D1.

Otherwise, the structure and function of the transmitter module 1212 for generating the bus states are the same as those described in 3 until 8 are described.

In the transmitter module 1212, which is constructed with a resistive H-bridge (full bridge), the common-mode voltage V _CM is determined primarily by the matching of the resistors of the transmitter stages 121A1, 121B1, 121C1, 121D1. Therefore, in the transmitter module 1212, the common-mode voltage V _CM can be small depending on the design of the transmitter stages 121A1, 121B1, 121C1, 121D1. If the leakage currents of the diodes of the transmitter module 1212 are not negligible, the channel resistance of the current limiters, in particular the transistors M _PCURR , MN _NCURR , can be adjusted by adjusting the limiting currents (I_CTRL and I_BIAS), and thus the common-mode voltage V _CM can be adjusted up and down.

Also in the case of the transmitting stage 1212, several replicas 152, 153, 153A are possible, as previously described with respect to the transmitting stages 1210, 1211.

Thus, with the previously described transmitter modules 121, 1210, 1211, 1212 and their control circuits 15, 15A, 15B, an adjustment of the common mode voltage V _CM can be achieved, so that the emission even during the switching processes between the different bus states 401, 402, 403, L1, L0 of 3 , 6 and 8 can be minimized.

All previously described embodiments of the transmission modules 121, 1210, 1211, 1212, the transmission/reception devices 12, 22, the control circuits 15, 15A, 15B of the subscriber stations 10, 20, 30, the bus system 1 and the method implemented therein according to the first and second embodiments and their modifications can be used individually or in all possible combinations. In addition, the following modifications are particularly conceivable.

The previously described bus system 1 according to the first and second embodiments is described using a bus system based on the CAN protocol. The bus system 1 according to the first and/or second embodiments can, however, alternatively be a different type of communications network in which the signals are transmitted as differential signals. It is advantageous, but not an essential requirement, that in the bus system 1 exclusive, collision-free access of a subscriber station 10, 20, 30 to the bus 40 is guaranteed at least for certain periods of time.

The bus system 1 according to the first and/or second embodiment and their modifications is in particular a CAN bus system or a CAN HS bus system or a CAN FD bus system or a CAN SIC bus system or a CAN XL bus system. However, the bus system 1 can be another communication network in which the signals are transmitted as differential signals and serially via the bus.

Thus, the functionality of the previously described embodiments can be used, for example, in transmitting/receiving devices 12, 22 that can be operated in a CAN bus system or a CAN HS bus system or a CAN FD bus system or a CAN SIC bus system or a CAN XL bus system.

In the bus system 1, subscriber stations 10, 30 may be present, of which at least one subscriber station has a transmitter module 121 according to 9 used and at least one subscriber station has a transmitter module 1210 according to 12 or a transmitter module 1211 according to 13 or a transmitter module 1212 according to 14 used.

The number and arrangement of the subscriber stations 10, 20, 30 in the bus system 1 according to the first to fourth embodiments and their modifications is arbitrary. In particular, only subscriber stations 10 or only subscriber stations 30 are present in the bus systems 1 of the first or second embodiment.

Claims (20)

Transmission module (121; 1210; 1211; 1212) for transmitting differential signals in a serial bus system (1), with a first transmission stage (121A; 121A1) for generating transmission currents (I1 to In) for a first signal (CAN_H) to be transmitted to a bus (40) of the bus system (1), a second transmission stage (121B; 121B1) for generating transmission currents (I1 to In) for a second signal (CAN_L) to be transmitted to the bus (40) as a signal differential to the first signal (CAN_H), a third transmission stage (121C; 121C1) for generating transmission currents (I1 to In) for the first signal (CAN_H), a fourth transmission stage (121D; 121D1) for generating transmission currents (I1 to In) for the second signal (CAN_L), and a control circuit (15; 15A; 15B) for adjusting a common mode voltage (V _CM ) for the first to fourth transmission stages (121A to 121D; 121A1 to 121D1), wherein the first to fourth transmission stages (121A to 121D; 121A1 to 121D1) are connected in a full bridge, in which the first and fourth transmission stages (121A, 121D; 121A1, 121D1) are connected in series and the third and second transmission stages (121C, 121B; 121C1, 121B1) are connected in series, wherein the control circuit (15; 15A; 15B) has a replica (152; 153; 153A) of an output stage of the transmission module (121; 1210; 1211; 1212), and wherein the replica (152; 153; 153A) is connected to the output stage of the transmission module (121; 1210; 1211; 1212). Transmitter module (121; 1210; 1211; 1212) according to Claim 1 , wherein a common mode point (157) of the replica (152; 153; 153A) is at the common mode voltage (V _CM ) of the output of the transmitting stages (121A, 121D; 121A1, 121D1). Transmitter module (121; 1210; 1211; 1212) according to Claim 2 , wherein the control circuit (15; 15A; 15B) further comprises a differential amplifier (151) having an input connected to the common mode point (157) of the replica (152; 153; 153A), and a control transistor (MN _CTRL ) for controlling a common mode voltage (V _CM ) to a predetermined value (ΔV), wherein the common mode voltage (V _CM ) is present at the common mode point (157) of the replica (152; 153; 153A). Transmission module (121; 1210; 1211; 1212) according to one of the preceding claims, wherein the replica (152; 153; 153A) comprises a series circuit of a transistor (MP _R ), a diode (MN _DIOPR ), a transistor (MP _CASPR ), a diode (MN _DIONR ), a transistor (MP _CASNR ) and a transistor (MN _R ) in the order mentioned, and wherein the sizes of the components of the series circuit are smaller by a predetermined factor than sizes of the components of the output of the first and fourth transmission stages (121A, 121D; 121A1, 121D1). Transmitter module (121; 1210; 1211; 1212) according to Claim 4 , wherein the transistor (MP _CASPR ) and the transistor (MP _CASNR ) are each designed as a cascode. Transmission module (121; 1210; 1211; 1212) according to one of the preceding claims, wherein output terminals (41, 42) of the full bridge are provided for connection to a terminating resistor (49) of the bus (40), and wherein the replica (153; 153A) in the series connection has a bus load (1531) which is a replica of a terminating resistor (49) of the bus (40). Transmitter module (121; 1210; 1211; 1212) according to Claim 6 , wherein the bus load (1531) comprises two resistors (R _DL1 , R _DL2 ), both connected to the common mode point (157) of the replica (152; 153; 153A). Transmitter module (121; 1210; 1211; 1212) according to Claim 6 or 7 , wherein the replica (153A) has a switching unit (1532) for switching on or off the bus load (1531). Transmission module (121; 1210; 1211; 1212) according to one of the preceding claims, wherein each transmission stage (121A to 121D; 121A1 to 121D1) is designed to adjust the value of the electrical current (I1 to In) output by the transmission stage (121A to 121D; 121A1 to 121D1) during operation of the transmission module (121) with a current mirror at the input of the transmission stage (121A to 121D; 121A1 to 121D1). Transmission module (121; 1210; 1211; 1212) according to one of the preceding claims, wherein the current mirror at the input of each transmission stage (121A to 121D; 121A1 to 121D1) has two CMOS transistors, wherein the CMOS transistors of the current mirror at the input of the first transmission stage (121A; 121A1) are PMOS transistors, wherein the CMOS transistors of the current mirror at the input of the second transmission stage (121B; 121B1) are NMOS transistors, wherein the CMOS transistors of the current mirror at the input of the third transmission stage (121C; 121C1) are PMOS transistors, and wherein the CMOS transistors of the current mirror at the input of the fourth transmission stage (121D; 121D1) NMOS transistors are. Transmission module (121; 1210; 1211; 1212) according to one of the preceding claims, wherein each transmission stage (121A to 121D; 121A1 to 121D1) has at least two current stages (S1 to Sn) which are connected in parallel to one another. Transmitter module (121; 1210; 1211; 1212) according to Claim 11 , wherein the at least two current stages (S1 to Sn) have at least one current sink. Transmitter module (121; 1210; 1211; 1212) according to Claim 11 or 12 , wherein a number n of the at least two current stages (S1 to Sn) is the same for each of the first to fourth transmission stages (121A to 121D; 121A1 to 121D1), where n is a natural number greater than 1. Transmission module (121; 1210; 1211; 1212) according to one of the preceding claims, further comprising a first resistor (R_H), one end of which is connected to the first transmission stage (121A; 121A1) and the other end of which is connected to the third transmission stage (121C; 121C1), and a second resistor (R_L), one end of which is connected to the second transmission stage (121B; 121B1) and the other end of which is connected to the fourth transmission stage (121D; 121D1). Transmission module (121; 1210; 1211; 1212) according to one of the preceding claims, further comprising a control circuit (T_A; T_B; T_C; T_D) for controlling switchable components of the first to fourth transmission stages (121A to 121D; 121A1 to 121D1) as a function of a digital transmission signal (TxD) and of an operating mode (SIC; FAST_TX) set for the transmission module (121; 1210; 1211; 1212). Transmitter module (121; 1210) according to Claim 15 , wherein the control circuit (T_A; T_B; T_C; T_D) is designed for the time-staggered and controlled switching of the currents of at least two current step switches (S1 to Sn) of the first to fourth transmission stages (121A to 121D; 1210A to 1210D). Transmitting/receiving device (12; 22) for a subscriber station (20) for a serial bus system (1), with a transmitting module (121; 1210; 1211; 1212) according to one of the preceding claims, and a receiving module (122) for receiving signals from the bus (40). Subscriber station (10; 20; 30) for a serial bus system (1), with a transmitting/receiving device (12; 22) according to Claim 17 , and a communication control device (11; 21) for controlling the communication in the bus system (1) and for generating a digital transmission signal (TxD) for controlling the first to fourth transmission stages (121A to 121D; 121A1 to 121D1). Subscriber station (10; 20; 30) after Claim 18 , wherein the subscriber station (10; 20; 30) is designed for communication in a bus system (1) in which at least temporarily exclusive, collision-free access of a subscriber station (10, 20, 30) to the bus (40) of the bus system (1) is ensured. Method for transmitting differential signals in a serial bus system (1), wherein the method is carried out with a transmission module (121; 1210; 1211; 1212) which has a first to fourth transmission stage (121A to 121D; 1210A to 1210D) and a control circuit (15; 15A; 15B), and wherein the method comprises the steps of generating, with the first transmission stage (121A; 121A1), transmission currents (I1 to In) for a first signal (CAN_H) which is to be transmitted to a bus (40) of the bus system (1), generating, with the second transmission stage (121B; 121B1), transmission currents (I1 to In) for a second signal (CAN_L) which is to be transmitted to the bus (40) as a signal differential to the first signal (CAN_H). is, generating, with the third transmission stage (121C; 121C1), transmission currents (I1 to In) for the first signal (CAN_H), and generating, with the fourth transmission stage (121D; 121D1), transmission currents (I1 to In) for the second signal (CAN_L), adjusting, with the control circuit (15; 15A; 15B), a common mode voltage (V _CM ) for the first to fourth transmission stages (121A to 121D; 121A1 to 121D1), wherein the first to fourth transmission stages (121A to 121D; 121A1 to 121D1) are connected in a full bridge, in which the first and fourth transmission stages (121A, 121D; 121A1, 121D1) are connected in series and the third and second transmission stages (121C, 121B; 121C1, 121B1) are connected in series, wherein the control circuit (15; 15A; 15B) has a replica (152; 153; 153A) of an output stage of the transmission module (121; 1210; 1211; 1212), and wherein the replica (152; 153; 153A) is connected to the output stage of the transmission module (121; 1210; 1211; 1212) is connected.

Images