DE102023200908A1 - Method for producing an electrical line arrangement and electrical line arrangement - Google Patents

Abstract

The invention relates to a method for producing an electrical line arrangement, especially for the microwave and/or millimeter wave frequency range, as well as an electrical line arrangement preferably produced using this method. The method for producing the electrical line arrangement comprises the following steps:
a) producing a carrier structure (20), wherein at least a first partial region (120) of the carrier structure (20) is produced by means of a three-dimensional structuring method, wherein at least a second partial region (220) of the carrier structure (20) comprises an electrically insulating material, and wherein the carrier structure (20) has at least one undercut (20a, 20b, 20c, 20d, 20e, 20f, 20g, 20h) with respect to a projection direction (100); and
b) producing at least one electrical conductor structure (1) by coating the carrier structure (20) with at least one electrically conductive material, wherein the coating comprises at least one spatially directed coating process which is oriented along the projection direction (100) aligned with the at least one undercut (20a, 20b, 20c, 20d, 20e, 20f, 20g, 20h).
The present invention makes it possible to provide a carrier structure (20) with integrated undercuts (20a, 20b, 20c, 20d, 20e, 20f, 20g, 20h), in particular to produce electrical line structures (1) on substrates (40, 41) of high-frequency (HF) chips or electrical line transitions (60a-60c, 61a-61c) to already existing electrical line structures (50a-50c, 51a-51c).

Description

Field of the invention

The present invention is in the field of microwave technology and relates to a method for producing an electrical line arrangement, especially for the microwave and/or millimeter wave frequency range, as well as an electrical line arrangement preferably produced using this method. The present invention makes it possible to provide a carrier structure with integrated undercuts, in particular to produce electrical line structures on substrates of high frequency (HF) chips, or electrical line transitions to existing electrical line structures. By designing the carrier structure accordingly, a large number of differently designed electrical line arrangements can be produced.

State of the art

Standaert et al., Three techniques for the fabrication of high precision, mm-sized metal components based on two-photon lithography, applied for manufacturing horn antennas for THz transceivers, J. Micromech. Microeng. 28, 035008, 2018 , describe the current state of the art in the manufacture of RF components using two-photon lithography. In one of the processes presented, carrier structures are first produced using two-photon lithography, the entire surfaces of which are then vapor-deposited using a PVD process. Then, a thicker copper layer. This process does not allow the production of isolated electrically conductive structures, as the entire surface of the structure is covered by the vapor deposition, in particular in order to uniformly coat the entire structure by providing a “seed layer” for the subsequent electroplating. to wet. After production, the structures are positioned manually or mechanically; it is not possible to produce corresponding components on substrates with other conductive structures.

M. Sterner et al., Electrochemically Assisted Maskless Selective Removal ofMetal Layers for Three-Dimensional Micromachined SOI RF MEMS Transmission Lines and Devices", J. Microelectromechanical Systems 20 (4), pp. 899-908, 2011 , describe a method for producing an electrical line arrangement by vapor deposition of a silicon cover layer that is initially selectively etched using a mask and by subsequently undercutting a silicon dioxide intermediate layer that is arranged between a silicon wafer and the silicon cover layer. In this process, the electrical Line arrangements on the surfaces of the silicon cover layer with direct “visual contact” to the vapor deposition source and remain electrically isolated from each other, since the undercutting of the intermediate layer can create a shadow from the silicon cover layer on the silicon wafer. This makes it possible to produce isolated electrically conductive structures is possible; however, the conductive structures that are still unintentionally created on the surface of the silicon wafer by the direct “visual contact” with the vapor deposition source are located in close proximity to the actual conductive structures on the surfaces due to the fixed and low height of the silicon dioxide intermediate layer. the silicon cover layer and can, for example, electrically couple. Therefore, it is imperative to remove these unwanted structures in order to ensure the electrical isolation of the electrically conductive structures. In addition, this process is due to the use of a planar layer structure consisting of silicon and silicon dioxide and subsequent selective etching of the silicon cover layer using a mask on planar line arrangements and in particular cannot provide line transitions.

Object of the invention

Proceeding from this, the object of the present invention is to provide a method for producing an electrical line arrangement and an electrical line arrangement which at least partially overcome the disadvantages and limitations of the prior art.

The object of the present invention is in particular to enable the production of a component which has electrically conductive structures which are insulated from one another within a cross-sectional plane, without the need to remove the additional conductive structures which are inadvertently generated by the direct "visual contact" with a vapor deposition source in order to ensure the electrical insulation of the line arrangement. Furthermore, the present invention should not be limited to the production of planar line arrangements.

Disclosure of the invention

This object is achieved by a method for producing an electrical line arrangement and an electrical line arrangement with the features of the independent patent claims. Advantageous further developments, which are individually or in any combination are set out in the dependent claims.

1. a) Herstellen einer Trägerstruktur, wobei zumindest ein erster Teilbereich der Trägerstruktur mittels eines dreidimensionalen Strukturierungsverfahrens erzeugt wird, wobei zumindest ein zweiter Teilbereich der Trägerstruktur ein elektrisch isolierendes Material umfasst, und wobei die Trägerstruktur mindestens einen Unterschnitt bezüglich einer Projektionsrichtung aufweist; und
2. b) Herstellen mindestens einer elektrischen Leitungsstruktur durch Beschichtung der Trägerstruktur mit mindestens einem elektrisch leitfähigen Material, wobei die Beschichtung mindestens einen räumlich gerichteten Beschichtungsprozess umfasst, der entlang der auf den mindestens einen Unterschnitt ausgerichteten Projektionsrichtung orientiert ist.

In a first aspect, the present invention relates to a method for producing an electrical line arrangement. The steps of the method are as follows:

1. a) producing a carrier structure, wherein at least a first partial region of the carrier structure is produced by means of a three-dimensional structuring process, wherein at least a second partial region of the carrier structure comprises an electrically insulating material, and wherein the carrier structure has at least one undercut with respect to a projection direction; and
2. b) producing at least one electrical conductor structure by coating the carrier structure with at least one electrically conductive material, wherein the coating comprises at least one spatially directed coating process which is oriented along the projection direction aligned with the at least one undercut.

The term “electrical line arrangement” refers to an arrangement that is designed to transport and/or modify electromagnetic waves. The electrical line arrangement proposed here comprises a carrier structure that was produced in at least a first partial area of the carrier structure using a three-dimensional structuring process, consists of an electrically insulating material in at least a second partial area of the carrier structure, and an electrical line structure is applied to the carrier structure. The electrical line structure comprises one or more electrically conductive structures, which can in particular also be designed as electrical lines or as waveguides. A totality or a subset of the electrically conductive structures that are electrically separated from one another or electrically connected to one another in a defined manner within one or more cross-sectional planes forms the desired electrical line structure. By specifically designing the majority of the electrically conductive structures, in particular by a connection outside a specific cross-sectional plane, a plurality of different electrical line structures can thus be produced on the carrier structure, which together with the electrical line structure forms the electrical line arrangement.

• - von 3 µm ≤ λ ≤ 3 mm, die auch als „Terahertz-Wellen“ oder „THz-Wellen“ bezeichnet werden; und/oder
• - von 300 µm ≤ λ ≤ 1 cm, die als „Millimeterwellen“ bezeichnet werden; und/oder
• - von 1 mm ≤ λ ≤ 1 m, die als „Mikrowellen“ bezeichnet werden,

verwendet werden.The present invention relates to any type of electromagnetic waves, as long as they can be guided in an electrical line designed as a waveguide. However, electromagnetic waves that have a wavelength λ of 3 µm ≤ λ ≤ 1 m are preferred. Electromagnetic waves

• - of 3 µm ≤ λ ≤ 3 mm, also known as ‘terahertz waves’ or ‘THz waves’; and/or
• - of 300 µm ≤ λ ≤ 1 cm, which are referred to as ‘millimeter waves’; and/or
• - of 1 mm ≤ λ ≤ 1 m, which are referred to as ‘microwaves’,

be used.

According to process step a), the carrier structure is produced at least in a first partial area using a three-dimensional structuring process. The term “freeform microstructuring process” refers to a subtractive or additive manufacturing process by means of which three-dimensional structures, preferably freeform structures, can be produced. In this context, a “freeform structure” is understood to mean a structure that - within the framework of technical limitations in terms of resolution and accuracy - can have arbitrarily curved surfaces at least in some areas. A freeform structure therefore differs in particular from structural geometries that can be produced using classic planar microstructuring processes, i.e. in particular using a combination of thin-film deposition processes, two-dimensional lithography processes (e.g. projection lithography) and etching processes on flat substrates. A combination of these processes usually leads to prism-like three-dimensional structure geometries, each of which has a base and top surface that are essentially parallel to the substrate surface, which are identical or very similar in shape to one another, and which - depending on the deposition and etching processes used - are connected to one another by side walls that are perpendicular or inclined to the substrate surface and/or curved inwards or outwards. The shape of the base and top surface is essentially determined by a mask that is often lithographically structured and used for local etching or deposition. By repeating the deposition and etching processes several times with different masks, multilayer structures comprising several prism-like substructures can be built up. However, the additional effort associated with this repetition is considerable and in many cases also limited by the overlay accuracy, so that the number of layers that can be produced in practice is often limited to a few, e.g. just three. This leads to geometric restrictions on the number of layers that can be produced with reasonable effort using known microstructuring processes. manufacturable structures and thus to functional limitations of the components formed thereby.

In contrast, freeform structures produced by freeform microstructuring processes are not subject to these restrictions or not to the same extent, since their structural geometry is not restricted to a combination of a comparatively small number of flat, prism-like substructures. This makes it possible in particular to use the partial area of the support structure defined by a freeform structure to design an electrical line arrangement that no longer necessarily has to be planar. It should be noted here that in many cases the freeform structures are also produced from a large number of individual layers - in particular by means of a multi-layer material application in 3D printing or by curing different layers in 3D lithography processes. However, freeform microstructuring processes make it possible to choose the number of these layers with reasonable manufacturing effort so large that a good approximation of the freeform structure is achieved and that the discretization into individual layers no longer represents a practically functionally relevant restriction of the structural geometries that can be produced. The structures are preferably made up of more than 10, particularly preferably more than 20, in particular more than 40 or 50 layers. When producing an electrical line arrangement that is set up for a vacuum operating wavelength of approximately 1 mm, the thickness of a layer is preferably between 100 nm and 10 µm, particularly preferably between 500 nm and 5 µm, in particular between 100 nm and 1 µm. This makes it possible to produce electrical line structures with an accuracy of preferably better than 10 µm, particularly preferably better than 5 µm, in particular better than 1 µm. The resolution of the freeform microstructuring process is preferably better than 20 µm, particularly preferably better than 5 µm, in particular better than 1 µm. The numerical values mentioned above refer to the production of an electrical line arrangement that is set up for a vacuum operating wavelength of approximately 1 mm. For other vacuum operating wavelengths, the dimensions of the structures and thus the requirements for the accuracy and resolution of the microfabrication process used for production can be scaled accordingly, in particular taking into account the refractive indices of the materials used. Depending on the design, different or the same freeform microstructuring processes can be used to produce the partial area of the support structure produced by a microstructuring process, optional additional shading structures and optional mechanical protective structures or protective layers, whereby all structures can be produced in a common operation when using the same freeform microstructuring process.

In a preferred embodiment, the freeform microstructuring method and/or a freeform microstructuring unit set up for such a method can be based on a lithographic method that uses in particular stereolithography or direct-writing, preferably three-dimensional direct-writing, lithography methods. Additive or subtractive manufacturing methods can be used, whereby the term “additive manufacturing method” refers to a manufacturing method in which material is gradually applied to or onto a structure, while the term “subtractive manufacturing method” describes an alternative manufacturing method in which material is gradually removed from a structure. In a preferred embodiment, the material application or material removal can be achieved with lithographic methods using suitable photoresists, in particular negative or positive resists. In a preferred embodiment, surface light modulators that allow rapid structuring can be used in a stereolithography method. In a preferred embodiment, multiphoton lithography methods, in particular using pulsed laser sources, can be used as direct-writing lithography methods. Light pulses with a pulse duration of at most 10 ps, preferably at most 1 ps, particularly preferably at most 200 fs, in particular at most 100 fs, at a repetition rate of preferably at least 1 MHz, preferably 10 MHz, particularly preferably at least 25 MHz, in particular at least 80 MHz, can be used. Laser light sources selected from fiber-based femtosecond lasers or pulsed solid-state lasers, preferably titanium: sapphire lasers or diode lasers, which can be combined with frequency conversion units, which are particularly designed for frequency multiplication, for generating sum frequencies or for generating difference frequencies, are particularly suitable for this purpose. Depending in particular on the lithography process used for this purpose, wavelengths in the near-infrared, visible or ultraviolet spectral range or in the range of extreme UV radiation (EUV) or X-ray wavelengths can preferably be used. In a particularly preferred embodiment, the wavelengths can be in a range from 150 nm to 1700 nm, in particular in a range from 300 nm to 1100 nm. In the case of pulsed lasers, two-, three- or multi-photon absorption effects can be achieved by selecting the pulse duration and pulse energy. Emission wavelengths between 360 nm and 550 nm, especially around 365 nm, 385 nm, 405 nm, 550 nm and 532 nm, are suitable for lithography processes based on ton absorption using continuous wave lasers or LEDs. To increase the resolution of lithography processes, the principle of "Stimulated Emission Depletion" (STED) can be used with suitable photoinitiators, based on corresponding microscopy methods.

In a specific embodiment, it may happen that the partial area of the carrier structure produced by a microstructuring process, the additional shading structures, the mechanical protective structures or the protective layers are larger than the available writing field size of the machine used for production by means of the structuring process. In these cases, the structures in question can be divided into individual sections, each of which lies within a writing field and which are produced by precisely stitching these sections together. The selection of the writing field size can be made in particular by considering the achievable resolution, which typically improves with smaller writing fields, and stitching errors at writing field boundaries, the number of which can be reduced by large writing fields. The writing field size is preferably between 50 × 50 µm ² and 5 × 5 mm ² , particularly preferably between 100 × 100 µm ² and 3 × 3 mm ² , and very particularly preferably between 200 × 200 µm ² and 1 × 1 mm ² . The alignment accuracy of the individual writing fields to one another is preferably better than 5 µm, particularly preferably better than 1 µm, in particular better than 500 nm or 100 nm. In a particular embodiment, a two-photon lithography system is used for production. In this case, the available writing field for lenses with a numerical aperture of 1.4 and a magnification of 40 can, for example, take the form of a circular area with a diameter of 400 µm.

In certain embodiments, the first partial region of the carrier structure produced by a three-dimensional microstructuring process can also comprise conductive materials. In this case, methods for 3D printing metals can preferably be used, which can be based in particular on material extrusion, powder bed fusion, material jetting, binder jetting, replica molding, selective laser melting, laser metal deposition or electron beam melting. In a particularly preferred embodiment, a polymer with a high proportion of particles (slurry), selected from e.g. copper, stainless steel or other conductive materials, can be produced. By subsequently baking the component in an oven, the polymer compounds are opened and burned out (debinding and sintering), so that a conductive workpiece remains that reflects the properties of the material from which the particles are made to a high extent.

In addition to the partial area produced by the three-dimensional structuring process, the carrier structure can also comprise further partial areas that are not structured or are structured by other processes. Cases are possible in which the carrier structure comprises an essentially flat substrate on which a further partial area of the carrier structure is produced by the three-dimensional structuring process, which, either alone or together with the substrate, has the undercut defined below. Particularly suitable substrates are silicon (Si), gallium arsenide (GaAs), indium phosphide (InP), aluminum oxide (Al ₂ O ₃ ), beryllium oxide, quartz glass, sapphire, (woven) PTFE/glass, polyolefin, ferrite/granite or a ceramic. Furthermore, the substrate can also comprise an electrically conductive partial area. When coating a carrier structure comprising a substrate, it may be possible in particular for the at least one free area defined by the at least one undercut in the carrier structure, which is designed to insulate the electrically conductive structures adjacent thereto, to be arranged on the substrate and, for example, not to be arranged on the partial area produced by the three-dimensional structuring process or the partial area of the carrier structure consisting of an insulating material.

• - einerseits eine mechanisch stabile und eine zumindest bereichsweise elektrisch isolierende Grundlage für eine anschließende, gemäß Verfahrensschritt b) erfolgende Beschichtung mit dem mindestens einen elektrisch leitfähigen Material bietet; und
• - andererseits in eine gewünschte geometrische, nicht notwendigerweise planare Form gebracht werden kann, auf welcher sich durch die gemäß Verfahrensschritt b) erfolgende Beschichtung die gewünschte elektrische Leitungsstruktur ausbildet.

The carrier structure produced according to process step a) further comprises at least a second partial region comprising an electrically insulating material which

• - on the one hand, it provides a mechanically stable and at least partially electrically insulating basis for a subsequent coating with the at least one electrically conductive material according to process step b); and
• - on the other hand, it can be brought into a desired geometric, not necessarily planar, shape on which the desired electrical conduction structure is formed by the coating carried out according to process step b).

For the purposes of the present invention, an “electrically insulating material” is a substance whose electrical conductivity σ is at most 10 ^-4 S/m, preferably at most 10 ^-7 S/m, in particular at most 10 ^-10 S/m. In addition, In addition, the electrically insulating material preferably has a high dielectric strength and preferably low losses, in particular in the form of a low loss factor tanδ of at most 0.1; preferably at most 0.05; in particular at most 0.01 at the respective operating frequency of the electrical line structure. Here, the term "operating frequency" refers to a frequency of the electromagnetic wave for which a selected electrical line arrangement is preferably designed. In an analogous manner, the term "operating wavelength" is given as the wavelength of the electromagnetic wave for which a selected electrical line arrangement is preferably designed. Materials suitable for the at least one electrically insulating partial area of the carrier structure are preferably ceramics, glasses, polymers or other organic compounds or appropriately doped semiconductors as well as composite materials made of the materials mentioned. Materials that can be structured three-dimensionally using appropriate methods are particularly suitable, with the methods and the associated materials being selected in a preferred embodiment so that the production of free-form structures is possible. In a preferred embodiment, polymer-based materials are used to produce the carrier structure, which preferably contain an optically additive or subtractive structurable polymer, e.g. from the class of acrylates, an epoxy resin or a fluoropolymer. If a lithography process is used in process step a) to structure a polymer-based material, polymers can preferably be used, which can in particular be fluorinated or can have polysiloxane-based components.

In a particularly preferred embodiment, the first partial region produced in method step a) by a three-dimensional structuring process can be identical to the second partial region comprising the electrically insulating material. However, the two regions can also be disjoint or non-overlapping or can fully or partially encompass each other. An example in which the second partial region completely encompasses the first partial region arises when an electrically conductive region of the substrate is replaced by an insulating substrate, so that only the insulating second partial region was produced by 3D printing. In a further example in which the two regions are disjoint, the carrier structure has a metallic core comprising a metallic substrate and an insulating coating. The core filling the first partial region is produced in the first partial region of the carrier structure by a three-dimensional structuring process, while an insulating coating in the second partial region of the carrier structure can be applied independently afterwards, in particular by an isotropic coating process. In this example, the two partial regions are therefore disjoint.

According to process step a), the support structure is manufactured in such a way that it has at least one undercut with respect to a projection direction. The terms “undercut”, “undercutting”, “undercut” or “undercutting” refer to an overhang defined with respect to a projection direction, which is introduced into the surface of the support structure. A geometric definition of the term “undercut” is given by way of example in 3 illustrated, which shows a support structure with an undercut defined with respect to a projection direction p with an associated shaded area. The shaded area here comprises the totality of all points P on the surface of the support structure for which a half-line g starting from the point P and oriented opposite to the projection direction p cuts through the support structure. The totality of the sections of all such half-lines g lying inside the support structure defines the partial area of the support structure referred to as the overhang. The overhang defines a shaded area which comprises the totality of the connecting lines PP ` of the points P lying outside the support structure with the closest entry point P ` of the associated half-line g into the support structure opposite to the projection direction p.

The at least one undercut is designed to create a shadow when the carrier structure is coated with at least one electrically conductive material in a spatially directed manner along the projection direction. The term “shadow” refers to a result of the coating of the carrier structure with the at least one electrically conductive material, whereby at least one free area on the surface of the carrier structure remains uncoated and is not covered by the electrically conductive material. Depending on the design of the coating process according to method step b) and depending on the direction of the spatially anisotropic material flow, the uncoated area can be identical to the area shaded in the geometric sense, can encompass the shaded area at least in part, or can be part of the shaded area.

According to process step b), the electrical conductor structure is produced by coating the carrier structure with at least one electrically conductive material. In a particular embodiment, the coating of the carrier structure can comprise several coating methods and/or materials, wherein at least one Coating process is spatially directed and wherein at least one material must be electrically conductive in the sense defined herein. In a preferred embodiment, the at least one electrically conductive material is applied in a directed coating process.

For coating the support structure, a coating process suitable for this purpose can be used. The coating process can preferably be selected from a physical vapor deposition (PVD) process, in particular thermal evaporation, electron beam evaporation, laser beam evaporation, arc evaporation, molecular beam epitaxy, ion plating or sputter deposition, where the sputter deposition comprises DC sputtering, RF sputtering, magnetron sputtering, reactive sputtering, ion beam sputtering or atom beam sputtering; or from a chemical vapor deposition (CVD) process including plasma-enhanced chemical vapor deposition (PECVD), thermal spraying or electroplating. In these processes, the degree of spatial anisotropy, i.e. the directionality of the material transport during the coating process, can be adjusted by various parameters, in particular by the pressure under which the coating takes place. In addition to spatially anisotropic, i.e. directional coating processes, isotropic processes can also be used in which the structures are coated on all sides. A large number of processes are conceivable here, such as dipping or spraying processes, spin coating, atomic layer deposition (ALD) or galvanic processes. In a special embodiment, after a directional coating with a metal, an isotropic coating with an inert protective material can be applied, in particular to prevent oxidation of the metal areas. In a special embodiment, a thickness of the electrically conductive structures of the electrical line structure applied from the at least one electrically conductive material can be increased by galvanic growth in order to increase the robustness of the coating, in particular under mechanical stress. The achieved thickness of the electrical line structure can preferably be greater than 1 µm, particularly preferably greater than 10 µm, in particular greater than 20 µm or 50 µm. The thickness achieved can be adjusted for the respective material, in particular by setting the process parameters such as current density, temperature and time.

For the purposes of the present invention, an “electrically conductive material” refers to a substance whose electrical conductivity σ is preferably at least 10 ⁶ S/m, particularly preferably at least 10 ⁷ S/m, in particular at least 5 × 10 ⁷ S/m. Materials particularly suitable for this purpose include silver, copper, gold and aluminum; however, the use of other metals is also possible. The electrical conduction structure can have a uniform region made of a single electrically conductive material, a mixed phase made of at least two different electrically conductive materials, in particular an alloy made of at least two different metals, and/or a layer structure made of at least two different layers, each of which comprises a uniform phase or a mixed phase.

In a preferred embodiment, a sequence of layers in the layer structure can be selected in a preferred manner. A preferred layer sequence can in particular comprise a first layer directly or indirectly adjacent to the carrier structure, which has an adhesion promoter with good adhesion properties in relation to a substrate arranged underneath and/or a layer arranged above, wherein the first layer can in particular comprise titanium, a core made of a material with high conductivity, preferably copper or gold, and an outer layer adjacent to the environment for passivation made of a chemically resistant material that does not tend to oxidize, preferably gold, silicon nitride or silicon dioxide. In addition, at least one further layer, preferably titanium, can be introduced between the material of the core and the passivation to provide diffusion protection. The use of other materials is also possible. The electrical conduction structure can thus be designed simultaneously for particularly high charge transport and for particularly high resistance to the environment in which substances that are aggressive to the electrically conductive material, in particular oxygen, can occur. The application of these layers does not necessarily have to be done in a spatially directed process. For the passivation layer in particular, it can be helpful to use an isotropic process that protects the electrical conductor arrangement from several sides, preferably from all sides, in particular atomic layer deposition or vapor deposition under high pressure.

A conductive layer thickness γ of the electrical conduction structure can be estimated approximately in many cases, based on the skin effect and taking into account the vacuum operating frequency, in particular using equation (1): $$\gamma =\frac{1}{\sqrt{\mu \pi }}\frac{1}{\sqrt{\sigma e}}$$

The conductive layer thickness γ is defined as the resulting wall thickness of a fictitious round conductor which has the same resistance for direct current as a solid conductor due to the skin effect at a frequency f. The absolute permeability µ = µ ₀ µ _r is made up of the permeability constant µ ₀ = 1.256 · 10 ^-6 N/A ² and the relative permeability number µ _r of the electrically conductive material used for the round conductor. The electrical conductivity of the electrically conductive material is designated σ. For example, for copper with a vacuum operating wavelength of approx. 1 mm and an electrical conductivity σ = 5.8 · 10 ⁶ S/m, the conductive layer thickness is γ = 0.12 µm. When using the coating process, the layer thickness of the electrically conductive material is therefore preferably selected to be at least so large that the layer thickness is preferably three times, particularly preferably five times, in particular ten times, the conductive layer thickness at the desired operating frequency or the desired operating wavelength. For other operating wavelengths, the layer thicknesses can be scaled proportionally to the square root of the wavelength, particularly taking into account the conductivity of the electrically conductive materials used.

According to method step b), the coating of the carrier structure comprises at least one spatially directed coating process that is oriented along the projection direction aligned with the at least one undercut. This results in the electrically conductive material being applied to the carrier structure as an electrical conduction structure in the form of one or more electrically conductive structures that are electrically separated from one another or electrically connected to one another in a defined manner within a cross-sectional plane, the direction of the coating corresponding to a projection direction related to the undercut. The at least one undercut introduced into the carrier structure causes, as already described above, the formation of at least one uncoated open area on the surface of the carrier structure, which provides electrical insulation between the electrically conductive structures adjacent to the at least one open area at desired locations on the surface of the carrier structure. In this way, the desired electrical conduction structure is formed on the surface of the carrier structure, which comprises the majority of electrically conductive structures that are electrically separated from one another or electrically connected to one another in a defined manner within a cross-sectional plane. In this case, it is particularly advantageous if the at least one undercut is already produced during process step a) in such a way with knowledge of the projection direction desired during process step b), in particular that the final shape of the desired electrical conduction structure, which comprises the majority of electrically conductive structures that are electrically separated from one another or electrically connected to one another in a defined manner, is freely defined in space via the shape of the carrier structure and the at least one undercut introduced therein, taking into account the direct line of sight between each point P to be coated on the carrier structure and the location of the vapor deposition source from which the electrically conductive material used to coat the carrier structure is provided.

In a preferred embodiment, the method of physical vapor deposition (PVD), in particular electron or laser beam evaporation, can be used. By selecting a sufficient working distance between the location of the vapor deposition source and the carrier structure to be coated, a vapor deposition direction defined by the connecting line between the vapor deposition source and the carrier structure to be coated can be set to a good approximation, which corresponds to the desired projection direction related to the undercut according to the invention. The distance between the vapor deposition source and the carrier structure to be coated is preferably more than 25 cm, particularly preferably more than 50 cm, in particular more than 75 cm or 100 cm, so that the flow of the vapor deposition beams emanating from the vapor deposition source has a divergence of preferably less than 10°, particularly preferably less than 5°, in particular less than 2° around the defined projection direction at the location of the carrier structure to be coated. The term "divergence" at the location of the carrier structure to be coated is understood to mean the variance or standard deviation of the directions in which the rays emanating from a vapor deposition source impinge on a specific point on the carrier structure. The variance can be determined in particular from a ratio of the lateral extent of the vapor deposition source to a distance of the vapor deposition source from the carrier structure to be coated. A high variance in the direction of the impinging rays can generally lead to a corresponding blurring of the edge of the shadow created by the at least one undercut, which can have adverse effects on the properties of the electrical line arrangement to be created. A deviation between the actual vapor deposition direction and a desired projection direction related to the undercut according to the invention can preferably be at most 20°, particularly preferably at most 10°, and in particular at most 5° or 2°. A working pressure in the chamber of the coating system can preferably be selected so that a mean free path of the particles transferred during vapor deposition exceeds the distance between the vapor deposition source and the carrier structure to be coated. The term “mean free path” refers to a path length that a particle, in particular selected from an atom, molecule, ion or electron, travels on average in a given material before it collides with another particle. If a particle stream in a material has passed through the mean free path, a fraction 1/e of the particle stream has not yet experienced a collision with another particle. The mean free path preferably exceeds the distance between the vapor deposition source and the carrier structure to be coated by a factor of at least 3, particularly preferably by a factor of at least 8 or 20, in particular by a factor of at least 100 or 200. The pressure can typically assume a value of 10 ^-7 Pa to 10 ^-3 Pa, in particular depending on the material selected in each case.

In a particular embodiment, when carrying out method step b), not only can the desired electrical line structure be formed, but at least one further electrically conductive structure can also be produced, which is not necessarily a functionally relevant component of the desired electrical line structure. It is therefore desirable for the at least one undercut to be designed in such a way that the at least one further electrically conductive structure can be arranged at a sufficiently large distance from the desired electrical line structure. In such an arrangement, an influence of the additionally generated electrically conductive structure on the electromagnetic wave guided in the desired electrical line structure, which can also be referred to as a "mode", can preferably be minimized. In particular, in order to avoid coupling of a mode guided in the desired electrical conduction structure with at least one other electrically conductive structure, a distance between the two structures can be specified which is chosen to be at least large enough that it exceeds a penetration depth ε of the electromagnetic wave guided in the desired electrical conduction structure into the surrounding spatial area, preferably by at least twice, particularly preferably five times, in particular ten times, the penetration depth ε. The term "penetration depth ε" here refers to a depth at which an evanescent electric field associated with a mode guided in an electrical conduction structure has dropped by a factor of 1/e.

The method described here can be used to produce a variety of different electrical conductor structures on a carrier structure.

In a preferred embodiment, the electrical line structure can comprise a single microstrip line, which is formed from an electrically conductive structure that is electrically insulated from the environment in all cross-sectional planes along the electrical line structure. Electrical insulation of the electrically conductive structure from the environment can preferably be achieved by the at least one free area on the surface of the carrier structure, which remains uncoated due to the shadow cast by the at least one undercut during the coating step. The electrically conductive structure can in particular be designed as an electrical line or as a waveguide on the carrier structure.

In a further preferred embodiment, the electrical line structure can have at least two electrically conductive structures which, spatially separated from one another, can be arranged at a distance on the support structure and at the same time can be electrically insulated from one another in all cross-sectional planes along the electrical line structure. In this case, the at least two electrically conductive structures can preferably be spatially separated from one another and electrically insulated from one another in that the at least one free area created by the at least one undercut is arranged between the at least two electrically conductive structures.

In this embodiment, the electrical line structure can comprise several individual, electrically conductive structures in the form of a plurality of microstrip lines that are electrically insulated from one another. The at least two insulated microstrip lines can be at the same electrical potential or at different electrical potentials. The microstrip lines can be arranged parallel to one another, for example. However, other embodiments of the microstrip lines are conceivable.

In this embodiment, the electrical line structure can in particular be or comprise a slot line, wherein the slot line has two electrically conductive structures which are spatially separated from one another and electrically insulated from one another in all cross-sectional planes along the electrical line structure, wherein the two electrically conductive structures are at the same electrical potential.

In this embodiment, the electrical line structure (1) can be or comprise a coplanar line, wherein the coplanar line has three electrically conductive structures which are spatially separated from one another and electrically insulated from one another in all cross-sectional planes along the electrical line structure, wherein two of the electrically conductive structures are at the same electrical potential, while a third of the electrically conductive structures is at a different electrical potential.

In a further preferred embodiment, the electrical line structure can be designed in the form of an antenna. In this embodiment, the electrical line structure can preferably comprise several individual, electrically conductive structures that are electrically insulated from one another within a cross-sectional plane, which can be changed in a defined manner along the line structure and in particular can also be electrically connected in a defined manner within at least one further cross-sectional plane of the electrical line structure. In this embodiment, at least one free area created by the at least one undercut can be designed in particular to enable a transition of a line-bound electrical signal to a free-space wave.

In a further preferred embodiment, the electrical line structure can comprise, in addition to the desired electrically conductive structures within a cross-sectional plane, at least one further electrically conductive structure described in more detail above, in particular to enable certain functions. In this embodiment, the electrical line structure can be designed in particular in the form of an electrical line coupler. The electrical line coupler can have two electrically conductive structures in the form of two waveguides, which can be arranged at a distance on the support structure and can be electrically insulated from one another in all cross-sectional planes along the line structure, wherein the two waveguides carry different signals and are spaced apart from one another, so that a desired coupling of an electrical field from one electrically conductive structure to the other electrically conductive structure can be set via at least one further electrically conductive structure.

In a further preferred embodiment, the electrical conductor structure can be designed in the form of an electrical probe tip, which is suitable for contacting electrical circuits, in particular high-frequency (HF) circuits, and which can preferably have at least one contact element for this purpose. The at least one contact element can be designed as a contact tip by appropriately shaping the carrier structure to be coated or can be based on suitable structural elements protruding in a direction perpendicular to the coated surface, which allow geometrically precise contacting of corresponding contact surfaces (pads or probe pads) on a chip or a flat substrate.

The production of further electrical conductor structures which have special geometries or may be suitable for special purposes is conceivable using the method described here.

A particular advantage of the method described herein is that the at least one undercut can make it possible to design the support structure for the electrical line structure in such a way that, based on the electrically conductive material of the electrical line structure and the geometry of the support structure, an effective permittivity of the mode guided in the electrical line structure can be set and varied along the line structure or the propagation direction of the electromagnetic field present in the line structure. Such a type of design can be particularly advantageous for reducing the influence of a high dielectric constant, for example of a substrate, for an antenna by gradually guiding the mode guided in the electrical line structure away from the substrate, in particular by varying the at least one undercut along the line structure. This can make it possible to adapt the permittivity effectively captured by the mode to the local conditions in order to reduce line losses or to gradually adjust the line impedance. Here, the term “gradual” refers to a continuous transition of a characteristic value of a mode, in particular the impedance, preferably starting from a substrate with a high dielectric constant to a partial region of the carrier structure based on a material with a lower dielectric constant, in particular by a linear transition of the geometries at the transitions.

In a further embodiment, the method described herein can be used to provide at least one electrical line transition to at least one existing electrical line structure, which was previously produced by means of the method described herein and/or by means of conventional manufacturing methods, on a substrate. For this purpose, the carrier structure can be aligned with the existing electrical line structure in such a way that the coating of the carrier structure with the at least one electrically conductive material along the projection direction, which is aligned with the at least one undercut, such that the at least one electrical line transition is produced from the already existing electrical line structure to the electrically conductive structure of the electrical line structure that is being formed. The carrier structure can ensure, by means of the at least one undercut, that the existing electrical line structure remains electrically insulated in all cross-sectional planes along the line structure.

However, with this type of coating, a global coverage of the substrate outside the partial area of the carrier structure produced by a three-dimensional structuring process by means of the electrically conductive material can occur, whereby the already existing electrical conductor structure as well as other components or circuits present on the substrate can be coated in an undesirable manner. In order to prevent such an undesirable coating, at least one additional shading structure can be aligned on the at least one electrical conductor transition between the already existing electrical conductor structure and the electrical conductor structure newly produced by means of the method described here in such a way that when the coating is applied under the projection direction, the already existing electrical conductor structure can remain electrically insulated in all cross-sectional planes along the conductor structure. This also makes it possible to prevent global short circuits of the electrical conductor structure to electrically conductive structures that continue to fall off.

In a preferred embodiment, the at least one additional shading structure can cover further areas of the substrate in such a way that these further areas of the substrate remain protected from global coverage with the electrically conductive material. For this purpose, it is particularly conceivable to completely cover these further areas with a protective structure, in particular in the form of a protective layer, and thus to minimize the influence of the electrical conduction structure that is being formed on the electrical conduction structure already present on the substrate by means of a sufficient thickness of the protective structure, in particular the protective layer. Alternatively, additional protective structures or shading structures, in particular a protective layer, can optionally be removed after coating, in particular by simply pulling them off using a suitable tool, preferably tweezers, or by means of a lift-off process that makes it possible to prevent global coverage with the electrically conductive material by allowing the additional electrically conductive structure formed as a by-product to be removed again. For this purpose, the areas to be protected can preferably be selectively covered with a protective layer before coating. In a preferred embodiment, the protective layer can be selectively applied using inkjet printing, using a dispenser and/or by lithographic structuring. After the electrically conductive material has been applied, the protective layer can be removed again, and with it the additional electrically conductive structure formed on the protective layer, in order to expose the existing electrical conduction structure again. It is advantageous if neither the protective materials used nor any substances used to remove them, such as solvents, damage the carrier structure, in particular the partial area produced by a three-dimensional structuring process, during prolonged exposure or otherwise have a negative effect. In a preferred embodiment, PMMA (polymethyl methacrylate) or another suitable substance can be used as a protective material for the protective layer, which can be removed again using PGMEA (propylene glycol monomethyl acetate) without attacking other areas of the carrier structure that were produced using two-photon lithography. Advantages of such lift-off processes include faster global coverage of the substrate, in particular by means of a deposition process, if the production of the protective structure or shading structures cannot be carried out by means of a microstructuring process due to the size of the area to be covered.

In a further preferred embodiment, the electrical line structure can comprise at least two electrical line transitions and thus be designed as a connecting element between at least two line structures arranged on separate substrates, wherein the line structures were previously produced by means of the method described herein and/or by means of conventional manufacturing methods. The carrier structure can comprise at least two substrates mounted on a common base plate and at least one partial area produced by means of a three-dimensional structuring method, which can connect via the electrical line transitions to the existing line structures on the two substrates, which have the at least one undercut according to the invention with respect to the projection direction. To protect the surfaces of the two substrates, these can again be covered at least in regions with corresponding, temporary or permanent protective structures, in particular shielding, during the coating process in method step b). ing structures or protective layers.

In a further preferred embodiment, the electrical line structure can be designed in the form of an interdigital capacitance. The electrical line structure in the form of the electrical interdigital capacitance can comprise a plurality of electrically conductive structures, whereby these can be arranged essentially alternately in two different planes running parallel to one another, and whereby these can be at different potentials. Preferably, the electrically conductive structures can lie in a common first plane defined by depressions in the carrier structure, while the remaining electrically conductive structures can lie in a second plane that is defined by webs between the depressions. To produce the electrical line arrangement, at least one undercut is introduced into the carrier structure with respect to the projection direction, which can ensure electrical insulation of the electrically conductive structures applied to the two different planes by means of the at least one free surface. In a preferred embodiment, a divergence of the vapor deposition beams emanating from the vapor deposition source around the defined projection direction at the location of the carrier structure to be coated can be used to increase a width of the strip-shaped electrically conductive structures produced in the first plane, so that these can overlap with the electrically conductive structures in the second plane in a projection along the projection direction. This can in particular contribute to increasing the electrical capacitance between the structures on the two planes. Electrically conductive structures lying in a common plane can be electrically connected to one another in a further cross-sectional plane of the electrical line structure and thus form a common electrical supply line. Due to the design of the partial area of the carrier structure as a 3D free-form structure, this design can offer more degrees of freedom in the arrangement compared to prior art methods, particularly with improved resolution.

• - eine Trägerstruktur, umfassend
  • ◯ zumindest einen, als dreidimensionale Freiformstruktur ausgestalteter und mittels eines dreidimensionalen Strukturierungsverfahrens erzeugter erster Teilbereich, und
  • ◯ einen, ein elektrisch isolierendes Material umfassender zweiter Teilbereich,
  wobei die Trägerstruktur mindestens einen Unterschnitt bezüglich einer Projektionsrichtung aufweist; und
• - mindestens eine, auf der Trägerstruktur als Beschichtung mittels mindestens einem räumlich gerichteten Beschichtungsprozess mit mindestens einem elektrisch leitfähigen Material entlang der auf den mindestens einen Unterschnitt ausgerichteten Projektionsrichtung aufgebrachte, elektrische Leitungsstruktur.

In a further aspect, the present invention relates to an electrical line arrangement, in particular an electrical line arrangement which was produced by means of the method also described herein. The electrical line arrangement comprises:

• - a support structure comprising
  • ◯ at least one first sub-area designed as a three-dimensional free-form structure and produced by means of a three-dimensional structuring process, and
  • ◯ a second sub-area comprising an electrically insulating material,
  wherein the support structure has at least one undercut with respect to a projection direction; and
• - at least one electrical conduction structure applied to the carrier structure as a coating by means of at least one spatially directed coating process with at least one electrically conductive material along the projection direction aligned with the at least one undercut.

For further details regarding the present electrical line arrangement, reference is made to the description of the method for producing an electrical line arrangement also described herein and to the embodiments.

Herein, the terms "have", "have", "comprise" or "include" or any grammatical forms thereof are used in a non-exclusive manner. Accordingly, these terms can refer both to situations in which, in addition to the features introduced by these terms, no further features are present, and to situations in which one or more further features are present. For example, the expression "A has B", "A has B", "A comprises B" or "A includes B" can refer both to the situation in which, apart from B, no other element is present in A (i.e., to a situation in which A consists exclusively of B), and to the situation in which, in addition to B, one or more other elements are present in A, for example element C, elements C and D, or other elements.

It should also be noted that the terms "at least one" and "one or more" and grammatical forms of these terms, when used in connection with one or more elements or features and intended to express that the element or feature may be provided once or multiple times, are generally used only once, for example when the feature or element is first introduced. When the feature or element is subsequently mentioned again, the corresponding term "at least one" or "one or more" is generally no longer used, without limiting the possibility that the feature or element may be provided once or multiple times.

Furthermore, the terms "preferred", "preferably", "in particular", "for example" or similar terms are used herein in connection with optional features, without limiting alternative embodiments. Thus, features introduced by these terms are optional features, and these features are not intended to limit the scope of the claims and in particular the independent claims. Thus, as the person skilled in the art will recognize, the invention can also be carried out using other embodiments. Similarly, features introduced by "in an embodiment of the invention" or by "in an embodiment of the invention" are understood to be optional features, without limiting alternative embodiments or the scope of the independent claims. Furthermore, these introductory expressions are intended to leave untouched all possibilities of combining the features introduced by them with other features, be they optional or non-optional features.

Advantages of the invention

In contrast to known methods for producing electrical line arrangements, which are often based on the use of masks and are therefore essentially limited to planar carrier structures and the production of different heights of the electrical line arrangements, the present method does not require masks for production, which in particular enables the production of 3D free-form line structures. By using 3D printing techniques to produce the carrier structures, complex three-dimensional carrier structures can be produced that are particularly suitable for increasing the coupling efficiency and the bandwidth between transmission lines compared to known methods. By using three-dimensional structuring methods to produce free-form carrier structures, no mask is required for production, and the electrical line arrangements can also be produced in situ, i.e. directly on site on chips, for example. This allows the electrical line arrangements to be aligned directly to existing circuits and connected electrically with, for example, a large bandwidth and low losses, whereby in particular the precise assembly steps that are usually necessary are eliminated. This enables the implementation of a large number of components, including connecting elements between several chips or antennas, which are designed as a free-form structure and are spaced from the surface for more efficient radiation.

The present manufacturing method also allows microwave components, in particular antennas, chip-chip connecting elements or electrical probe tips, to be produced directly on existing substrates as carrier structures. Printing the sub-areas of the carrier structure that define the electrical line structures or on a substrate contained in the carrier structure and protecting the carrier structure or the substrate by shading structures, in particular protective layers, enables a large variety of structures with 3D free-form geometries to be realized and in particular allows the electrical line structures to be adapted to the conditions of existing structures. This is particularly important in high-frequency technology, since changes to electrical line structures on chips are typically complex and costly, while the function and design of the electrical line structures according to the invention can be flexibly varied by appropriately shaping the sub-area of the carrier structure produced by means of a three-dimensional structuring process. The possibility of a three-dimensional design of the carrier structure means that electromagnetic waves can be guided away from the substrate, for example, and the influence of a high dielectric constant of the substrate or the carrier structure can be easily adapted to the local requirements within a cross-sectional area if necessary. In a similar way, electrical probe tips with a wide variety of geometries can be flexibly implemented on standardized and therefore cost-effective carrier substrates.

The present manufacturing process is particularly flexible in its application and can therefore make a significant contribution to solving problems in the field of packaging in the next generation of high-frequency components, especially in the millimeter wave and THz frequency range.

Short description of the characters

• 1 und 2 jeweils ein bevorzugtes Ausführungsbeispiel eines erfindungsgemäßen Verfahrens zur Herstellung einer elektrischen Leitungsanordnung als schematische Querschnitts-Darstellung;
• 3 schematisch eine geometrische Definition des auf die Projektionsrichtung bezogenen erfindungsgemäßen Unterschnitts in der erfindungsgemäßen Trägerstruktur;
• 4 bis 10 jeweils ein Ausführungsbeispiel der erfindungsgemäßen elektrischen Leitungsanordnung als schematische Querschnitts-Darstellung;
• 11 bis 14 schematisch einen Verfahrensablauf zur Herstellung einer weiteren erfindungsgemäßen elektrischen Leitungsanordnung;
• 15 und 16 jeweils ein bevorzugtes Ausführungsbeispiel der erfindungsgemäßen elektrischen Leitungsanordnung;
• 18 ein weiteres Ausführungsbeispiel des Verfahrensablaufs zur Herstellung einer weiteren erfindungsgemäßen elektrischen Leitungsanordnung als mikroskopische Aufnahmen; und
• 19 und 20 jeweils ein weiteres Ausführungsbeispiel der erfindungsgemäßen elektrischen Leitungsanordnung als mikroskopische Aufnahmen.

Further details and features of the present invention emerge from the following description of preferred embodiments, in particular in conjunction with the dependent claims. The respective features can be implemented alone or in combination with one another. The invention is not limited to the embodiments. The embodiments are shown schematically in the following figures. The same reference numbers in the figures designate the same or functionally identical elements or elements that correspond to one another in terms of their functions. In detail:

• 1 and 2 each shows a preferred embodiment of a method according to the invention for producing an electrical line arrangement as a schematic cross-sectional representation;
• 3 schematically a geometric definition of the undercut according to the invention related to the projection direction in the support structure according to the invention;
• 4 to 10 each shows an embodiment of the electrical line arrangement according to the invention as a schematic cross-sectional representation;
• 11 to 14 schematically shows a process sequence for producing a further electrical line arrangement according to the invention;
• 15 and 16 each shows a preferred embodiment of the electrical line arrangement according to the invention;
• 18 another embodiment of the process sequence for producing another electrical line arrangement according to the invention as microscopic images; and
• 19 and 20 each show a further embodiment of the electrical line arrangement according to the invention as microscopic images.

Description of the embodiments

The 1 and 2 show, each in the form of a schematic cross-sectional representation, a preferred embodiment of a method according to the invention for producing an electrical line arrangement. 1 schematic process step a) and 2 schematically illustrates process step b). The representations chosen for this purpose and the shapes used, in particular for the support structure 20, are to be understood as examples; according to expert considerations, a large number of other arrangements and shapes are possible.

1 schematically shows method step a), which comprises the production of the carrier structure 20, wherein a first partial region 120 of the carrier structure 20 is produced by means of a three-dimensional structuring process, wherein a second partial region 220 of the carrier structure 20 comprises an electrically insulating material, and wherein the carrier structure 20 has undercuts 20a, 20b, 20c, 20d with respect to a projection direction 100. In the case outlined, the partial regions 120, 220 are identical and form the carrier structure 20.

2 schematically represents method step b), which relates to the production of at least one electrical line structure 1 by coating the carrier structure 20 with at least one electrically conductive material along a projection direction 100 aligned with the undercuts 20a, 20b, 20c, 20d. In this case, the coating of the carrier structure 20, including the undercuts 20a, 20b, 20c, 20d encompassed by the carrier structure 20, takes place from the projection direction 100. The areas 30a, 30b, 30c, 30d shaded by the undercuts 20a, 20b, 20c, 20d present in the carrier structure 20 result from the defined projection direction 100 known in advance and are not or only insignificantly affected by the spatially directed coating of the carrier structure 20 by means of the electrically conductive material. The wording “only insignificantly” means in this context that edge regions of the shaded regions 30a, 30b, 30c, 30d can be covered by the electrically conductive material, for example as a result of a non-vanishing divergence 105 of the vapor deposition beams emanating from the vapor deposition source around the defined projection direction 100, but that an open area 30a, 30b, 30c, 30d uncovered by the electrically conductive material still remains, which leads to an electrical insulation of the electrically conductive structures 10a, 10b, 10c in the outlined cross-sectional area of the line structure 1.

As in 2 As shown schematically, several electrically conductive structures 10a, 10b, 10c, which are insulated from one another, and further electrically conductive structures 11a, 11b are formed on the surface of the carrier structure 20 by the coating with the electrically conductive material within a cross-sectional plane. In the present embodiment according to 2 Three electrically conductive structures 10a, 10b, 10c are located at a common height and each have a shape that is predetermined by the three-dimensional shape of the surface of the carrier structure 20. Due to the undercuts 20a, 20b, 20c, 20d encompassed by the carrier structure 20, open areas 30a, 30b, 30c, 30d are also formed on the surface of the carrier structure 20 in relation to the projection direction 100 by coating the surface of the carrier structure 20 with the electrically conductive material. The free surfaces 30a, 30b, 30c, 30d insulate the electrically conductive structures 10a, 10b, 10c from each other and are further designed so that the electrically conductive structures 10a, 10b, 10c remain electrically insulated within a cross-sectional plane from the further electrically conductive structures 11a, 11b, which have inevitably formed in the recesses of the carrier structure 20 during the implementation of method step b). By appropriately shaping the carrier structure 20, a configuration can be achieved in which the further electrically conductive structures 11a, 11b are so far away from the electrically conductive structures ren 10a, 10b, 10c are removed so that an electrical signal guided through the electrically conductive structures 10a, 10b, 10c does not interact with the other electrically conductive structures 11a, 11b, see also 6 and the associated description. In this case, the three electrically conductive structures 10a, 10b, 10c form the desired electrical line structure 1. The electrical line structure 1, together with the support structure 20 and the free areas 30a, 30b, 30c, 30d present here, forms the electrical line arrangement.

3 shows schematically the inventive definition of the projection direction p 100 as well as the inventive undercut 20a related thereto and the associated shaded region 30a in the carrier structure 20 according to the invention. In the case outlined, the two partial regions 120, 220 are identical and form the carrier structure 20. The shaded region 30a comprises the totality of all points P 1015 on the surface of the carrier structure 20 for which a half-line g 1016 starting from the point P 1015 and oriented opposite to the projection direction p 100 cuts through the carrier structure 20. The totality of the sections 1030 of all such half-lines g 1016 located inside the support structure 20 defines the partial area of the support structure 20 referred to as overhang 1020. The overhang 1020 defines a shaded area 1040 - this includes the totality of the connecting lines PP' 1031 of the points P 1015 located outside the support structure 20 with the entry point P' of the associated half-lines g 1016 into the support structure 20 that is closest to the projection direction p 100.

4 shows an embodiment of the electrical line arrangement according to the invention in the form of a schematic cross-sectional representation, in which the carrier structure 20 comprises a substrate 40. The first partial areas 120 of the carrier structure are produced from an electrically insulating material by means of a three-dimensional structuring process. An electrically insulating carrier material is used as the substrate 40, which is not produced in the same production process as the first partial areas 120 of the carrier structure 20. The electrically insulating second partial area 220 of the carrier structure 20 in this embodiment comprises both the substrate 40 and the first partial areas 120 of the carrier structure 20, which are produced by means of the three-dimensional structuring process. The carrier structure 20 is - analogous to the representation in 2 - coated with at least one electrically conductive material in relation to the projection direction 100. The coating forms - also analogous to 2 - the electrically conductive structures 10a, 10b, 10c which are isolated from each other and the further electrically conductive structures 11a, 11b. In contrast to the representation according to 2 However, the further electrically conductive structures 11a, 11b and the free surfaces 30a, 30b, 30c, 30d are arranged here on the surface of the substrate 40 and not (or not exclusively; not shown here) on the surface of the first partial region 120 of the carrier structure 20 produced by a three-dimensional structuring process.

5 shows a further embodiment of the electrical line arrangement according to the invention in the form of a schematic cross-sectional representation, in which an isotropic coating with an inert protective material 26 is applied to the carrier structure 20, the electrically conductive structures 10a, 10b, 10c forming the electrical line structure 1 and the further electrically conductive structures 11a, 11b. The production of the exemplary in 5 The line arrangement outlined can be used analogously to the 1 and 2 described procedure. In the 5 In the embodiment shown, the two partial areas 120, 220 are identical and form the support structure 20. After production, the inert protective material 26 can be applied by an isotropic process in which the structure is coated on all sides. The inert protective material 26 can, for example, be designed to prevent oxidation of the metal areas 10a, 10b, 10c, 11a, 11b.

6 shows schematically the cross section of another electrical line arrangement according to the invention, which can be produced using the present method. In the 6 In the embodiment shown, the two sections 120, 220 are identical and form the support structure 20. The electrical line structure 1 according to 6 forms a coplanar line which comprises the three electrically conductive structures 10a, 10b, 10c, which are each electrically insulated from one another in all cross-sectional planes along the line structure 1, wherein the two electrically conductive structures 10a, 10c can be at the same potential, for example in the case of a so-called "ground-signal-ground" configuration. In order to prevent short circuits between the resulting electrically conductive structures 10a, 10b, 10c and the other electrically conductive structures 11a, 11b during the directed coating of the surface of the carrier structure 20 along the projection direction 100, slots made in the carrier structure 20 between the areas to be coated have the undercuts 20a, 20b, 20c, 20d, which are designed to provide the open spaces 30a, 30b, 30c, 30d intended for insulation. The undercuts 20a, 20b, 20c, 20d in the In the present embodiment, the support structure 20 is designed to be so deep that the signal routing in the desired electrical line structure 1, which comprises the electrically conductive structures 10a, 10b, 10c, cannot be influenced by the electrically conductive structures 11a, 11b that inevitably continue to occur on the support structure 20. This is explained in 6 indicated by field lines of an electric field 80, the course of which is not affected by the further electrically conductive structures 11a, 11b, in particular due to a sufficient distance. The further electrically conductive structures 11a, 11b produced as a "by-product" can thus remain in place on the surface of the carrier structure 20 (or alternatively on the surface of the substrate 40; not shown here) in this exemplary embodiment and therefore do not have to be removed.

7 shows schematically the cross section of another electrical line arrangement according to the invention, which can also be produced using the present method. In the 7 In the embodiment shown, the two sub-areas 120, 220 are identical and form the carrier structure 20. Here, the electrical line structure 1 is designed in the form of an electrical line coupler. The electrical line structure 1 in the form of the electrical line coupler comprises the three electrically conductive structures 10a, 10b, 10c, wherein two of the electrically conductive structures 10a, 10c are electrically insulated from one another in all cross-sectional planes along the line structure 1 and are at different electrical potentials from one another. The distance between the two electrically conductive structures 10a, 10c is selected such that a coupling of the electrical field 80 from one electrically conductive structure 10a to the other electrically conductive structure 10c (or vice versa) via the third electrically conductive structure 10b, which is located in a 7 schematically illustrated incision in the carrier structure 20. A width of the third electrically conductive structure 10b is determined by means of the undercuts 20b, 20c inserted into the carrier structure 20, which are designed as shading structures with respect to the projection direction 100, and the free areas 30b, 30c defined by these shading structures. This design is particularly advantageous in the case of strong overcoupling, for which small distances between the two electrically conductive structures 10a, 10c are required, which are more difficult to produce using planar lithography processes with limited lateral resolution. By means of the third electrically conductive structure 10b, which can be produced by coating the electrically conductive material, the strength of the overcoupling can be increased while maintaining the same distance. An undesirable influence on the electrical line structure 1 by the further electrically conductive structures 11a, 11b produced as a “by-product” on the two outer sides of the carrier structure 20 can be prevented by the further undercuts 20a, 20d inserted into the carrier structure 20. These two undercuts 20a, 20d are in the embodiment according to 7 deeper than the undercuts 20b, 20c, which is why the further electrically conductive structures 11a, 11b defined on the basis of the defined free areas 30a, 30d have a greater distance from the electrically conductive structures 10a, 10c of the electrical line structure 1. In this way, overcoupling of the electrical field 80 from the electrical line structure 1 to the further electrically conductive structures 11a, 11b can be prevented.

8th shows schematically the cross section of another electrical line arrangement according to the invention, which can also be produced using the present method. In the 8th In the embodiment shown, the two sub-areas 120, 220 are identical and form the carrier structure 20. Here, the electrical line structure 1 is designed in the form of an electrical interdigital capacitance. The electrical line structure 1 in the form of the electrical interdigital capacitance comprises, for example, the seven electrically conductive structures 10a, 10b, 10c, 10d, 10e, 10f, 10g, which are arranged essentially alternately in two different planes 35, 36 running parallel to one another, and which can be at different potentials. The four electrically conductive structures 10a, 10c, 10e, 10g lie, for example, in a common first plane 35 defined by depressions in the carrier structure 20, while the remaining three electrically conductive structures 10b, 10d, 10f lie in a second plane 36 which is defined by webs between the depressions. To produce the electrical line arrangement 1, undercuts 20a, 20b, 20c, 20d, 20e, 20f are introduced into the carrier structure 20 with respect to the projection direction 100, which, by means of the free surfaces 30a, 30b, 30c, 30d, 30e, 30f, ensure electrical insulation of the electrically conductive structures 10a, 10b, 10c, 10d, 10e, 10f, 10g applied to the two different levels 35, 36. In the case outlined, the flow of the vapor deposition beams emanating from the vapor deposition source has a divergence 105 around the defined projection direction 100 at the location of the carrier structure 20 to be coated, which is why the width of the strip-shaped electrically conductive structures 10a, 10c, 10e, 10g produced in the first plane 35 is increased, so that they overlap in a projection along the projection direction 100 with the electrically conductive structures 10b, 10d, 10f located in the second plane 36. This can be used in particular to increase the electrical capacitance between the structures on the two planes 35, 36. The electrically conductive structures 10a, 10c, 10e, 10g and 10b, 10d, 10f lying in a common plane 35, 36 can be electrically connected to one another in a further cross-sectional plane of the electrical line structure 1 and thus form a common electrical supply line.

9 shows an embodiment of the electrical line arrangement according to the invention in the form of a schematic cross-sectional representation, in which the carrier structure 20 comprises a substrate 40, which comprises an upper electrically conductive partial region 320 and a lower electrically insulating second partial region 220. The first partial regions 120 of the carrier structure 20 are produced from an electrically insulating material by means of a three-dimensional structuring process. The electrically insulating second partial region 220 of the carrier structure 20 consists in this case of several elements and comprises both the lower second partial region 220 of the substrate 40 and all first partial regions 120 of the carrier structure 20, which are produced by means of the three-dimensional structuring process. The carrier structure 20 is - analogous to the representation in 4 - coated with the at least one electrically conductive material in relation to the projection direction 100. The coating forms - also analogous to 4 - the electrically conductive structures 10a, 10b, 10c which are isolated from each other and the further electrically conductive structures 11a, 11b. In contrast to the representation according to 4 However, further first partial regions 120 of the carrier structure 20 can be produced on the substrate 40 by means of a three-dimensional structuring process in such a way that during the coating a through-connection 15 is produced between at least one of the electrically conductive structures 10a, 10c and at least one further conductive structure present in the arrangement by means of the electrically conductive partial region 320 of the substrate 40. This can be achieved, for example, via corresponding ramp structures in the first partial region 120 produced by means of the three-dimensional structuring process.

10 shows an embodiment of the electrical line arrangement according to the invention in the form of a schematic cross-sectional representation, wherein the carrier structure 20 comprises an electrically conductive or insulating substrate 40, a first partial area 120 applied thereon and produced by a three-dimensional structuring process, and an insulating coating 25 that essentially homogeneously surrounds the substrate 40 and the first partial area 120, wherein the insulating coating 25 forms the insulating second partial area 220 of the carrier structure 20 and is applied, for example, by an isotropic coating process. In this case, the two partial areas 120, 220 are therefore disjoint, ie they do not overlap. The carrier structure 20 shown can then - analogously to 2 - coated with at least one electrically conductive material along the projection direction 100 in order to form the electrical line structure 1 consisting of the electrically conductive structure 10a. In contrast to the representation according to 2 However, the further electrically conductive structures 11a, 11b and the open areas 30a, 30b are arranged here on the surface of the insulating coating 25 and not on the surface of the first partial region 120 of the carrier structure 20 produced by a three-dimensional structuring process.

In a special embodiment (not shown), the electrically conductive structures 10a, 10b, 10c, etc. as well as the other electrically conductive structures 11a, 11b, etc. of the 2 , 4 , 5 , 6 , 7 , 8th , 9 and 10 schematically illustrated electrical line structures 1 vary in cross-section and/or follow a non-planar trajectory along the direction of propagation of the electromagnetic signal, which in the cases outlined runs essentially perpendicular to the respective drawing plane. This non-planar trajectory can be predetermined by a corresponding non-planar shape of the carrier structure 20, wherein in particular the use of a three-dimensional structuring method according to the invention opens up new scope for embodiments. In a further embodiment, the substrate 40 contained in the carrier structure 20 can also have a non-planar shape, by which the trajectory of the line course is defined or significantly influenced. In addition, for example, a cross-section of the electrical line structure 1 can change along the direction of propagation of the electromagnetic wave. This makes it possible to locally adapt a line impedance in accordance with the changing cross-section or to create line transitions 60a, 61a adapted on both sides in electrical connecting elements. Alternatively, certain components defined by the respective shape of the electrical conductor structure 1, in particular with a capacitive, resistive or inductive effect, can be produced.

The 11 to 14 show schematically a method sequence for producing a further electrical line arrangement according to the invention, which is designed as a non-planar electrical connection element between the two separate substrates 40, 41, according to the manufacturing method described herein using additional shading structures 70, 71.

11 shows a schematic of an initial situation in which the two insulating substrates 40, 41 are approximately aligned with one another. Each of the two substrates 40, 41 comprises existing line structures 50a, 50b, 50c; 51a, 51b, 51c, sketched here as an example as a conventional coplanar line, wherein the line structures were previously produced using the method described here and/or using conventional manufacturing methods. The coplanar lines each comprise three electrically conductive structures which are electrically insulated from one another in all cross-sectional planes along the line structure, wherein the two existing electrically conductive structures 50a, 50c; 51a, 51c are each at the same potential.

12 shows schematically a first method step, according to which the first partial region 120 of the carrier structure 20 is produced using a three-dimensional structuring process from an electrically insulating material. In this embodiment, the first partial region 120 of the carrier structure 20 forms a connection between the conventional coplanar lines and bridges at least one gap that may be present between the two substrates 40, 41.

By using a three-dimensional structuring process according to the invention, it is possible to 11 to 14 shown structures, it is particularly possible to adapt the geometry of the first partial region 120 of the carrier structure 20 to the positioning of the two substrates 40, 41, which cannot always be precisely controlled. In particular, it is thus possible to first assemble these substrates 40, 41 using a cost-effective method with comparatively large positioning tolerances, then to determine the exact position of the ends of the existing line structures 50a, 50b, 50c; 51a, 51b, 51c that are to be connected, and to use this information to design the first partial region 120 of the carrier structure 20 that is to be produced using the 3D microstructuring method. The first partial region 120 adapted to the position of the line ends to be connected can then be realized with high precision on the substrates 40, 41, thus creating a precisely defined, for example broadband and/or low-loss electrical line transition 60a, 60b, 60c; 61a, 61b, 61c between the existing line structures 50a, 50b, 50c; 51a, 51b, 51c. To precisely detect the position of the ends of the existing line structures 50a, 50b, 50c; 51a, 51b, 51c to be connected and to precisely align the first sub-area 120 on the substrates 40, 41, which is adapted to the position of the line ends to be connected, the device used to implement the 3D microstructuring process can have additional image capture functions with which, for example, markers or structural elements on the substrates 40, 41 can be precisely captured. In the case of two-photon lithography processes, such functions can be based, for example, on camera-based 2D or 3D imaging processes or on scanning processes, for example based on the principle of confocal microscopy. The precision with which structures on the substrates 40, 41 can be detected and corresponding first partial regions 120 can be placed on these substrates 40, 41 is preferably better than 100 µm, particularly preferably better than 10 µm, especially preferably better than 1 µm, 300 nm, or 100 nm.

To prevent the 13 In order to create short circuits between the resulting electrically conductive structures 10a, 10b, 10c; 11a, 11b, 11c, 11d, 11e, 11f during the coating of the carrier structure 20 with the electrically conductive material along the projection direction 100, corresponding open spaces 30a, 30b, 30c, 30d, 30e, 30f are created between these structures with the aid of suitable undercuts 20a, 20b, 20c, 20d, 20e, 20f. The undercuts 20a, 20b, 20c, 20d, 20e, 20f are designed so deep in the cross section of the electrical line structure 1 that - analogous to the representation in 6 - the electrically conductive structures 10a, 10b, 10c are not influenced, only insignificantly influenced, or only locally and in a desired manner influenced by the electrically conductive structures 11a, 11b, 11c, 11d, 11e, 11f produced as a “by-product”.

In order to further prevent the already existing electrically conductive structures 50a, 50b, 50c; 51a, 51b, 51c from being short-circuited by the coating, additional shading structures 70, 71 in the form of several protruding arms are used. The additional shading structures 70, 71 are aligned at the transitions between the already existing electrically conductive structures 50a, 50b, 50c; 51a, 51b, 51c and the electrical line structure 1 in such a way that when the coating is applied under the defined projection direction 100, no connection can be created between the already existing electrically conductive structures 50a, 50b, 50c; 51a, 51b, 51c in all cross-sectional planes along the line structure 1.

The additional shading structures 70, 71 can preferably be produced using the same microstructuring process in process step a) together with the first partial region 120 of the carrier structure 20. As a result of the coating in the projection direction 100 in process step b), 13 and 14 schematically show, on the one hand, first electrical line transitions 60a, 60b, 60c between the already existing electrical electrically conductive structures 50a, 50b, 50c on the first substrate 40 and the electrically conductive structures 10a, 10b, 10c of the electrical line structure 1, and on the other hand further electrical line transitions 61a, 61b, 61c between the further already existing electrically conductive structures 51a, 51b, 51c on the further substrate 41 and the electrically conductive structures 10a, 10b, 10c of the electrical line structure 1. The further electrically conductive structures 11a, 11b, 11c, 11d, 11e, 11f formed as a “by-product” on the substrates 40, 41 of the carrier structure 20 do not influence the electrical line structure 1, only insignificantly, or in a precisely known manner that can therefore be taken into account in the design.

14 shows schematically the completed electrical line arrangement after the additional shading structures 70, 71 have been removed. The additional shading structures 70, 71 can preferably be removed by simply pulling them off using tweezers or by means of a lift-off process already mentioned above.

In addition to the additional shading structures 70, 71 described above, the two substrates 40, 41 can be provided at least in some areas with corresponding temporary or permanent protective layers 75 (not shown here), which prevent unwanted coating of the substrate surfaces or corresponding sub-areas during the coating process in process step b). These protective layers can be produced, for example, by suitable lithography, printing or dispensing processes and removed again with suitable solvents after the process step b) has been carried out.

15 shows schematically a further embodiment of the electrical line arrangement according to the invention, which is designed here in the form of a non-planar dipole antenna. The electrical line arrangement comprises the insulating substrate 40, which has a conventionally manufactured coplanar line made up of three already existing electrically conductive structures 50a, 50b, 50c, wherein two of the already existing electrically conductive structures 50a, 50c can be at the same electrical potential. In this embodiment, the electrical line structure 1 initially comprises three individual electrically conductive structures 10a, 10b, 10c that are electrically insulated from one another within a cross-sectional plane, which are varied in their respective geometry along the line structure 1 in a defined manner and in particular are also electrically connected within at least one further cross-sectional plane of the electrical line structure 1.

Method step a) comprises producing the first partial region 120 of the carrier structure 20, produced by a three-dimensional structuring process, from an electrically insulating material according to 15 In order to be able to coat surfaces at an angle of 90° to the surface of the substrate 40, the projection direction 100 is set to an angle of, for example, 45° to the surface of the substrate 40. Both the side walls of the slots between the structures to be coated and the outer walls of the first partial area 120 of the support structure 20 have 15 shown ramp structure via undercuts 20a, 20b, 20c, 20d, 20e, 20f, which are designed to produce the open spaces 30a, 30b, 30c, 30d, 30e, 30f along the ramp structure. The undercuts 20a, 20b, 20c, 20d, 20e, 20f are designed so deep that the electrical line structure 1, which includes the electrically conductive structures 10a, 10b, 10c, - analogous to the representation in 6 - cannot be influenced by the electrically conductive structures 11a, 11b, 11c produced as a "by-product", can only be influenced in an insignificant manner, or in a precisely known manner that must be taken into account during execution. The further undercuts 20g, 20h introduced into the feet and wings of the first partial region 120 of the support structure 20 produced by a three-dimensional structuring process are designed to produce the open areas 30g, 30h, which effect the electrical insulation of the electrically conductive structures 10a, 10b, 10c encompassed by the electrical line structure 1 from the substrate 40 and/or the electrically conductive structures 11c formed as a "by-product" on the substrate 40.

By coating the carrier structure 20 with the electrically conductive material along the projection direction 100, the electrical line transitions 60a, 60b, 60c are formed between the already existing electrically conductive structures 50a, 50b, 50c on the substrate 40 and the electrically conductive structures 10a, 10b, 10c of the electrical line structure 1. The electrically conductive structures 10a, 10b, 10c, which are insulated from one another within a cross-sectional plane A (section in (x, z) plane) sketched as an example, are guided upwards via the ramp structure, where the two outer electrically conductive structures 10a, 10c are brought together in the middle with the middle electrically conductive structure 10b, which is set up as a signal conductor, within at least one further cross-sectional plane B (section in (x, z) plane) sketched as an example, whereby a dipole antenna is formed. If correctly implemented, this can result in an efficient adaptation of the line impedance of the electrical line structure 1 to the wave impedance of the free space and thus a radiation of the dipole signals generated thereby. Antenna without a possible increased permittivity of the substrate 40 becoming a problem.

In this embodiment, analogous to the In the arrangements shown, additional shading structures 70 (not shown) can be used to enable an electrical connection of the electrically conductive structures 10a, 10b, 10c to the already existing electrically conductive structures 50a, 50b, 50c without creating a short circuit between the electrically conductive structures 10a, 10b, 10c or the already existing electrically conductive structures 50a, 50b, 50c to the substrate 40 and/or the electrically conductive structures 11a, 11b, 11c formed as a “by-product” on the substrate 40.

16 shows schematically a further embodiment of the electrical line arrangement according to the invention, which is designed here in the form of an electrical probe tip, which can be particularly suitable for contacting HF circuits. The 16 The electrical line arrangement shown schematically can preferably be carried out analogously to the process steps according to the 11 to 14 and the 15 schematically shown electrical line arrangement. For further details, please refer to the description of the 11 to 15 referred to.

In 16 the projection direction 100 is set to an angle of 90° to the surface of the insulating substrate 40. By coating the carrier structure 20 with the electrically conductive material along the projection direction 100, the electrical line transitions 60a, 60b, 60c are formed between the already existing electrically conductive structures 50a, 50b, 50c on the substrate 40 and the electrically conductive structures 10a, 10b, 10c of the electrical line structure 1. The electrically conductive structures 10a, 10b, 10c that remain isolated in all cross-sectional planes along the line structure 1 are also connected here via the 16 schematically illustrated ramp structure and converge there at a fixed distance in order to form three contact elements 500. The inventive production of the first partial area 120 with the aid of a three-dimensional structuring process also allows a very precise alignment with structures already present on the substrate 40, see explanations of the 11 to 15 , as well as a very dimensionally accurate production of the electrical line structures 1 with flexibly adjustable electrical parameters such as the impedance of the line arrangement and the transition defined by the contact elements 500 to another test substrate (not shown).

In the 16 The structure shown further comprises contact elements 500 which were produced by appropriate shaping of the carrier structure 20 to be coated and with which a geometrically precise contacting of corresponding contact surfaces on a chip or a flat substrate is possible. In the 16 In the embodiment outlined, the contact elements 500 are based on structural elements that protrude in a direction perpendicular to the coated surface and that, in the case outlined, take the form of truncated pyramids. Other geometric configurations of the contact elements 500 are conceivable.

Also in this embodiment, as in the 12 and 13 shown, additional shading structures 70 (not shown) can be used to enable an electrical connection of the electrically conductive structures 10a, 10b, 10c to the already existing electrically conductive structures 50a, 50b, 50c in all cross-sectional planes along the line structure 1, without creating a short circuit between the electrically conductive structures 10a, 10b, 10c or the already existing electrically conductive structures 50a, 50b, 50c to the substrate 40 and/or the electrically conductive structures 11a, 11b, 11c, 11d formed as a “by-product” on the substrate 40.

The carrier structure 20 can in particular be designed such that the three contact elements 500 - as in 16 indicated - protrude to the right beyond the edge of the substrate 40 and thus remain visible for contacting even in a rotated arrangement of the electrical line structure 1, in which the contact elements 500 point downwards and a camera image taken from above is used for positioning. The diverse possibilities for designing the first partial area 120 of the carrier structure 20 produced by a three-dimensional structuring process also allow mechanical protective structures 600 to be produced with the aid of the method used in method step a) or with the aid of another three-dimensional structuring process, which prevent unwanted mechanical damage to the electrical probe tip, for example due to a collision or when placed at an angle on an underlying test substrate. The mechanical protective structures 600 can, as in 16 shown, be designed as solid protective structures 600, which prevent an unwanted approach of the electrical probe tip to an object that could damage it. Alternatively or additionally, the protective structures 600 can be designed in such a way that an approach of the electrical probe tip or the contact elements 500 to an object that could damage it damaging object, for example a substrate 41, leads to a detectable elastic or partially elastic deformation of the protective structure 600 or a part thereof, see 17 For this purpose, dedicated monitor structures 2000 with display structures 2200 can be used, via which an approach 2300 of the electrical probe tip to the object potentially damaging it, which occurs essentially along a viewing direction 2100, can be converted into a deformation 2400 of the monitor structure 2000 that occurs laterally to the viewing direction 2100 and is thus visually recognizable. In a preferred embodiment, the monitor structures 2000 or parts thereof can be produced together with the first partial region 120 of the carrier structure 20 using a three-dimensional microstructuring process.

In 18 is another embodiment of the process sequence according to the 11 to 14 for producing a further electrical line arrangement according to the invention in the form of microscopic images. For further details, please refer to the above description of the 11 to 14 referred to.

18(a) shows the further electrical line arrangement according to the invention, which comprises the two substrates 40, 41, each of which has an existing electrical line structure, which has the already existing electrically conductive structures 50a, 50b, 50c; 51a, 51b, 51c, wherein two of the two already existing electrically conductive structures 50a, 50c; 51a, 51c are at the same potential. The substrates 40, 41 comprise - analogously to the outlined structure in 9 - in each case in a second partial region 220 an insulating carrier body made of aluminum oxide (Al ₂ O ₃ ) with a layer thickness of 625 µm, as well as a conductive region 320, which was produced by means of a gold layer with a layer thickness of 3 µm on the insulating carrier body. The already existing electrically conductive structures 50a, 50b, 50c; 51a, 51b, 51c were produced by structuring this gold layer, for example with the aid of a conventional lithography process or with the aid of a laser ablation process.

The existing electrically conductive structures 50a, 50b, 50c; 51a, 51b, 51c are to be connected in an electrically conductive manner to their respective counterparts. For this purpose, the 18(b) The first partial region 120 of the carrier structure 20 shown is produced from an insulating material using a two-photon lithography process. The electrically insulating second partial region 220 of the carrier structure 20 in this example comprises both the lower second partial region 220 of the substrates 40, 41 and the first partial regions 120 of the carrier structure 20, which are produced using the three-dimensional structuring process. Due to limitations in the size of the writing field, the electrical line arrangement was divided into several parts and manufactured in several steps.

In order to ensure that the carrier structure is coated with the electrically conductive material in 18(c) In order to avoid creating short circuits between the resulting electrically conductive structures 10a, 10b, 10c; 11a, 11b, 11c, 11d, 11e, 11f using a PVD process along the projection direction 100 at an angle of 90° to the surface of the substrates 40, 41, the first partial region 120 of the carrier structure 20 has slots in the side walls of which the undercuts 20a, 20b, 20c, 20d, 20e, 20f are made, which are designed to produce the open areas 30a, 30b, 30c, 30d, 30e, 30f. The undercuts 20a, 20b, 20c, 20d, 20e, 20f are designed so deep that the electrical line structure 1, which includes the electrically conductive structures 10a, 10b, 10c - analogous to the representation in 6 - is not influenced, only insignificantly influenced, or influenced in a known manner which must be taken into account during execution by the electrically conductive structures 11a, 11b, 11c, 11d, 11e, 11f produced as a “by-product”.

Due to the coating in the projection direction 100, first electrical line transitions 60a, 60b, 60c are formed between the already existing electrically conductive structures 50a, 50b, 50c on the 18(b) shown left substrate 40 and the electrically conductive structures 10a, 10b, 10c of the electrical line structure 1 produced according to the invention, and on the other hand further electrical line transitions 61a, 61b, 61c between the further already existing electrically conductive structures 51a, 51b, 51c on the substrate 40 shown in the 18(b) shown right substrate 41 and the electrically conductive structures 10a, 10b, 10c of the electrical line structure 1. The coating produced in this way on the carrier structure 20 has a total layer thickness of approximately 600 nm along the projection direction 100, which largely comprises a copper layer due to the high electrical conductivity. A thin titanium layer serves as an adhesion promoter between the carrier structure 20 and the copper layer; a thin gold layer is also applied as an outer layer to passivate against the environment. In order to prevent gold from diffusing from the gold layer into the copper layer, another thin titanium layer can be inserted between the copper layer and the gold layer.

However, in order to avoid that the coating also damages the already existing electrically conductive structures 50a, 50b, 50c; 51a, 51b, 51c are short-circuited within themselves and with the respective adjacent substrate 40, 41, additional shading structures 70, 71 in the form of several protruding arms are used, which were preferably produced beforehand using the same two-photon lithography process as the first partial region 120 of the carrier structure 20. The additional shading structures 70, 71 are aligned with the electrical line transitions 60a, 60b, 60c; 61a, 61b, 61c between the already existing electrically conductive structures 50a, 50b, 50c; 51a, 51b, 51c and the electrical line structure 1 in such a way that during coating under the defined projection direction 100 no electrically conductive connection is formed between the already existing electrically conductive structures 50a, 50b, 50c; 51a, 51b, 51c or to the substrate 40, 41. The electrically conductive structures 11a, 11b, 11c, 11d, 11e, 11f formed as a “by-product” are also electrically insulated. For this purpose, the effect of the shadow cast by the additional shading structures 70, 71 at the respective electrical line transitions 60a, 60b, 60c; 61a, 61b, 61c along the projection direction 100 is utilized. In this way, the 18 shown three-dimensional electrical connection element can be produced between the coplanar lines already present on the two substrates 40, 41, wherein the individual electrically conductive structures 10a, 10b, 10c remain electrically insulated from one another in all cross-sectional planes along the line structure 1.

The additional shading structures 70, 71 are designed according to 18 due to the limited writing field size of the printing process, only for the protection of the direct surroundings of the electrical line transitions 60a, 60b, 60c; 61a, 61b, 61c, which is why a protective layer 75 made of PMMA (polymethyl methacrylate) covers the already existing electrically conductive structures 50a, 50b, 50c; 51a, 51b, 51c over the remaining surface of the substrates 40, 41. The protective layer 75, which in the present embodiment was applied by means of an inkjet printing process, is in 18(b) to the left of the additional shading structure 70 on the left substrate 40 and to the right of the shading structure 71 on the right substrate 41. In principle, other methods are conceivable that enable a large-area covering of the substrates 40, 41 with sufficient precision, for example lithographic methods, dispensing methods, or a simple covering with an adhesive film. The protective layer is applied during the coating process according to 18(c) further covered with a metal layer. By dissolving the PMMA layer with PGMEA (propylene glycol monomethyl acetate), the metal layer can be removed from the areas previously covered with the PMMA layer in a lift-off process, so that - as in 18(d) recognizable - the already existing electrically conductive structures 50a, 50b, 50c; 51a, 51b, 51c remain electrically insulated.

In principle, as already explained above, it may be conceivable and desirable to carry out the entire covering of the substrates 40, 41 using the same microstructuring process that is also used for producing the first partial area 120 of the carrier structure 20 and the additional shading structures 70, 71, provided that the selected microstructuring process allows this. Due to writing field limitations of the two-photon lithography process used here, the complete covering of the substrates 40, 41 would, however, take too long in practice due to the large surface area of the substrates 40, 41, which is why the printing and lift-off process described here was used instead. The electrically conductive structures 11c, 11d, 11e, 11f formed as a "by-product" usually remain on the substrates 40, 41 without influencing the line structure 1, but can preferably - as can be seen from a comparison of the 18(c) and 18(d) - can be removed by pulling it off with tweezers.

The 18(e) and 18(f) show the completed electrical line arrangement after the additional shading structures 70, 71 have been removed. The shadows created using the additional shading structures 70, 71 on the carrier structure 20 during coating are shown in 18(e) clearly visible in the form of darkening at the electrical line transitions 60a, 60b, 60c; 61a, 61b, 61c.

19 shows in the form of microscopic images a further embodiment of the electrical line arrangement according to the invention according to 15 as a non-planar dipole antenna. For further details, please refer to the description of the 15 referred to.

19 shows the electrical line arrangement, comprising the substrate 40, which has a conventionally manufactured coplanar line made up of three already existing electrically conductive structures 50a, 50b, 50c, wherein two of the already existing electrically conductive structures 50a, 50c are at the same potential. The substrate 40 comprises - analogous to the outlined structure in 9 - in each case in a second partial area 220 an insulating carrier body made of aluminum oxide (Al ₂ O ₃ ) with a layer thickness of 625 µm, as well as a conductive area 320, which is attached to the iso by means of a gold layer with a layer thickness of 3 µm The already existing electrically conductive structures 50a, 50b, 50c were created by structuring this gold layer, for example using a conventional lithography process or using a laser ablation process. To produce the non-planar dipole antenna, which has a fixed distance from the substrate 40, the first partial area 120 of the carrier structure 20 was also produced using a two-photon lithography process and then coated with the electrically conductive material using a PVD process. Due to restrictions on the writing field size, the electrical line arrangement was divided into several parts and manufactured in several steps. Since the carrier structure 20 in this exemplary embodiment also has surfaces at an angle of 90° to the surface of the substrate 40 and in order to produce the desired distance of the non-planar dipole antenna from the substrate 40, coating at this angle is not useful here. Therefore, the coating was carried out with respect to a projection direction 100 according to 15 , which has an angle of, for example, 45° to the surface of the substrate 40. The side walls of the slots introduced into the support structure 20 between the surfaces to be coated have - analogously to the embodiment according to 18 - via undercuts 20a, 20b, 20c, 20d. The undercuts 20a, 20b, 20c, 20d are also designed so deep that the electrical line structure 1, which includes the electrically conductive structures 10a, 10b, 10c - analogous to the representation in 6 - cannot be influenced by the electrically conductive structures 11a, 11b produced as a "by-product", only insignificantly, or in a known manner that must be taken into account during implementation. The coating on the carrier structure 20, which is largely made as a copper layer or from a suitable sequence of different materials, also has a total layer thickness of approximately 600 nm along the projection direction 100. A thin titanium layer serves as an adhesion promoter between the carrier structure 20 and the copper layer; a thin gold layer is applied as an outer layer to passivate it against the environment, and here too another thin titanium layer can be inserted between the copper layer and the gold layer.

As in 19(c) As can be seen, the further undercuts 20e, 20f, 20g, 20h introduced into the feet and wings of the support structure 20 are also designed here to produce the open spaces 30e, 30f, 30g, 30h, which effect the electrical insulation of the electrically conductive structures 10a, 10b, 10c encompassed by the electrical line structure 1 from the substrate 40. By coating the support structure 20 with the electrically conductive material along the projection direction 100, the electrical line transitions 60a, 60b, 60c are formed between the already existing electrically conductive structures 50a, 50b, 50c on the substrate 40 and the electrically conductive structures 10a, 10b, 10c of the electrical line structure 1. Here too, the electrically conductive structures 10a, 10b, 10c are guided upwards via the ramp structure, whereby in all cross-sectional planes along the line structure 1 the electrically conductive structures 10a, 10b, 10c initially remain insulated from one another, and whereby at the peak of the ramp the two outer electrically conductive structures 10a, 10c, after the slots have been formed, are brought together in the middle with the middle electrically conductive structure 10b, which is set up as a signal conductor, within a cross-sectional plane, forming a dipole antenna. If carried out correctly, this can achieve an efficient adaptation of the line impedance of the electrical line structure 1 to the wave impedance of the free space and thus an efficient radiation of the dipole antennas created in this way.

In this embodiment, too, additional shading structures 70, 71 are used to enable an electrical connection of the electrically conductive structures 10a, 10b, 10c of the electrical line structure 1 to the already existing electrically conductive structures 50a, 50b, 50c without creating a short circuit between the electrically conductive structures 10a, 10b, 10c or the already existing electrically conductive structures 50a, 50b, 50c to the substrate 40 and/or the electrically conductive structure 11a, 11b, 11c formed as a “by-product” on the substrate 40.

19(c) shows the substrate 40 with three dipole antennas after the additional shading structures 70, 71 have been removed. In order to protect the already existing electrically conductive structures 50a, 50b, 50c over the entire surface of the substrate 40 from a short circuit, here too - as in the embodiment for 18 - a protective layer 75 made of PMMA is used, which is removed again in a lift-off process with PGMEA.

20 shows in the form of microscopic images a further embodiment of the electrical line arrangement according to the invention according to 16 as an electrical probe tip, especially for contacting HF circuits. For further details, please refer to the description of 16 referred to.

20 shows the electrical line arrangement comprising the substrate 40, which has a conventionally manufactured coplanar line made up of three existing electrically conductive structures 50a, 50b, 50c, whereby two of the existing electrically conductive structures 50a, 50c can be at the same potential. The substrate 40 comprises - analogous to the outlined structure in 9 - in each case in a second partial area 220 an insulating carrier body made of aluminum oxide (Al ₂ O ₃ ) with a layer thickness of 625 µm, as well as a conductive area 320, which was produced by means of a gold layer with a layer thickness of 3 µm on the insulating carrier body. The already existing electrically conductive structures 50a, 50b, 50c were produced by structuring this gold layer, for example with the aid of a conventional lithography process or with the aid of a laser ablation process. To produce the electrical probe tip, the first partial area 120 of the carrier structure 20 was also structured here using a two-photon lithography process. The carrier structure 20 was then coated with the electrically conductive material using a PVD process along the projection direction 100 according to 16 at an angle of 90° to the surface of the substrate 40. The side walls of the slots introduced into the support structure 20 between the surfaces to be coated have - analogously to the embodiments according to the 18 and 19 - via undercuts 20a, 20b, 20c, 20d, 20e, 20f. The undercuts 20a, 20b, 20c, 20d, 20e, 20f are also designed so deep that the electrical line structure 1, which includes the electrically conductive structures 10a, 10b, 10c, is separated from the electrically conductive structures 11a, 11b, 11c, 11d produced as a "by-product" - analogous to the representation in 6 - not influenced, only insignificantly influenced, or influenced in a known manner that must be taken into account during implementation. The coating on the carrier structure 20, which is largely implemented as a copper layer, also has a total layer thickness of approximately 600 nm along the projection direction 100. A thin titanium layer serves as an adhesion promoter between the carrier structure 20 and the copper layer; a thin gold layer is applied as an outer layer to passivate it against the environment, and here too another thin titanium layer can be inserted between the copper layer and the gold layer.

By coating the carrier structure 20 with the electrically conductive material along the projection direction 100, the electrical line transitions 60a, 60b, 60c are formed between the already existing electrically conductive structures 50a, 50b, 50c on the substrate 40 and the electrically conductive structures 10a, 10b, 10c of the electrical line structure 1. The electrically conductive structures 10a, 10b, 10c, which remain isolated in all cross-sectional planes along the line structure 1, are also guided upwards via the ramp structure and converge there at a fixed distance to form contact elements 500. The contact elements 500 are in this case designed in the form of structures similar to truncated pyramids.

In this exemplary embodiment, additional shading structures 70 are also used to enable an electrical connection of the electrically conductive structures 10a, 10b, 10c of the electrical line structure 1 to the already existing electrically conductive structures 50a, 50b, 50c without creating a short circuit between the electrically conductive structures 10a, 10b, 10c or the already existing electrically conductive structures 50a, 50b, 50c to the substrate 40 and/or the electrically conductive structure 11a, 11b, 11c, 11d formed as a "by-product" on the substrate 40. In order to protect the already existing electrically conductive structures 50a, 50b, 50c over the entire surface of the substrate 40 from a short circuit, here too - as in the exemplary embodiments for the 18 and 19 - a protective layer 75 made of PMMA is used, which is removed in a lift-off process with PGMEA.

In addition to the embodiments shown, further designs are possible. The use of a lithography process with significantly larger writing fields and at the same time sufficiently high lateral resolution in the micrometer range, such as projection micro-stereolithography (PµSL), enables complete coverage of the substrate surface 40 as protection during coating and eliminates the previously used, complex lift-off process using PMMA and PGMEA. The production of large-area protective structures directly together with the carrier structure 20 and the additional shading structures 70 - according to 12 - in the same lithography step results in a significant time saving and a considerable simplification of the process and, by dispensing with the application of chemicals to the substrate 40 and the carrier structure 20, in particular the first partial area 120, enables extensive protection of sensitive components and thus a significantly greater freedom in the choice of material for the carrier structure 20.

List of reference symbols

1

electrical wiring structure

10a-10g

electrically conductive structure

11a-11f

further electrically conductive structure

15

Through-hole plating

20

Support structure (for the electrical wiring structure)

20a-20h

Undercut (in the support structure)

25

insulating coating

26

isotropic coating with protective material

30a-30h

shaded area on support structure; “open spaces”

35, 36

planes running parallel to each other

40, 41

Substrate (part of the carrier structure)

50a-50c, 51a-51c

existing electrical wiring structure

60a-60c, 61a-61c

electrical line transition

70, 71

additional shading structure

75

Protective layer

80

Field lines of an electric field; “mode”

100

Projection direction p

105

Divergence of the vapor deposition rays emanating from the vapor deposition source around the specified projection direction p

120

First part of the carrier structure (produced by three-dimensional structuring process)

220

(electrically insulating) second part of the support structure

320

(electrically conductive) part of the substrate

500

Contact element

600

mechanical protective structure

1015

Point P on surface of the support structure

1016

Half-line g opposite to the projection direction p

1020

Overhang (part of the support structure)

1030

Sections of the half-line located inside the support structure

1031

connecting line PP' outside the support structure

1040

shaded area

2000

Monitor structure

2100

Viewing direction

2200

Display structure

2300

Approach direction

2400

deformation

QUOTES INCLUDED IN THE DESCRIPTION

This list of documents listed by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions.

Cited non-patent literature

• Standaert et al., Three techniques for the fabrication of high precision, mm-sized metal components based on two-photon lithography, applied for manufacturing horn antennas for THz transceivers, J. Micromech. Microeng. 28, 035008, 2018 [0002]
• M. Sterner et al., Electrochemically Assisted Maskless Selective Removal ofMetal Layers for Three-Dimensional Micromachined SOI RF MEMS Transmission Lines and Devices", J. Microelectromechanical Systems 20 (4), pp. 899-908, 2011 [0003]

Claims (26)

Method for producing an electrical line arrangement, comprising the following steps: a) producing a carrier structure (20), wherein at least a first partial region (120) of the carrier structure (20) is produced by means of a three-dimensional structuring process, wherein at least a second partial region (220) of the carrier structure (20) comprises an electrically insulating material, and wherein the carrier structure (20) has at least one undercut (20a, 20b, 20c, 20d, 20e, 20f, 20g, 20h) with respect to a projection direction (100); and b) producing at least one electrical conductor structure (1) by coating the carrier structure (20) with at least one electrically conductive material, wherein the coating comprises at least one spatially directed coating process which is oriented along the projection direction (100) aligned with the at least one undercut (20a, 20b, 20c, 20d, 20e, 20f, 20g, 20h). Method according to the preceding claim, wherein the coating of the carrier structure (20) comprises at least one spatially directed coating process using at least two mutually different electrically conductive materials. Method according to one of the preceding claims, wherein a thickness of the at least one electrical line structure (1) comprising the electrically conductive structures (10a, 10b, 10c, 10d, 10e, 10f, 10g) is increased by galvanic growth. Method according to one of the preceding claims, wherein the production of the at least one electrical line structure (1) is carried out in such a way that at least one electrically conductive structure (10a, 10b, 10c, 10d, 10e, 10f, 10g) is formed, which, by means of at least one free surface (30a, 30b, 30c, 30d, 30e, 30f, 30g, 30h) generated by the at least one undercut (20a, 20b, 20c, 20d, 20e, 20f, 20g, 20h), is arranged opposite a further electrically conductive structure (10a, 10b, 10c, 10d, 10e, 10f, 10g) adjacent to the at least one electrically conductive structure (10a, 10b, 10c, 10d, 10e, 10f, 10g) is electrically insulated within a cross-sectional plane of the at least one electrical line structure (1). Method according to one of the preceding claims, wherein the carrier structure (20) comprises a substrate (40, 41). Method according to one of the preceding claims, wherein the production of the at least one electrical line structure (1) is selected from the production of - a microstrip line, comprising the production of a single structure (10a) that is electrically conductive in all cross-sectional planes along the at least one electrical line structure (1); - a slot line, comprising the production of two electrically conductive structures (10a, 10b) that are electrically insulated from one another in all cross-sectional planes along the at least one electrical line structure (1); - a coplanar line, comprising the production of three electrically conductive structures (10a, 10b, 10c) that are electrically insulated from one another in all cross-sectional planes along the at least one electrical line structure (1); - an antenna, comprising the production of at least one electrically conductive structure (10a) which, in cooperation with the at least one free area (30a, 30b, 30c, 30d, 20e, 20f, 20g, 20h) generated by the at least one undercut (20a, 20b, 20c, 20d, 20e, 20f, 30g, 30h), is designed to provide a transition of an electrical signal bound to the at least one electrically conductive structure (10a) to a free wave space; - an electrical line coupler, comprising the production of three electrically conductive structures (10a, 10b, 10c) which are electrically insulated from one another in all cross-sectional planes along the at least one electrical line structure (1), wherein two of the electrically conductive structures (10a, 10c) are placed at different electrical potentials, wherein a distance between the two electrically conductive structures (10a, 10c) is selected such that a coupling of an electrical field (80) from the one electrically conductive structure (10a) to the other electrically conductive structure (10c) is set via the third electrically conductive structure (10b); - an electrical probe tip which has at least one contact element (500) suitable for contacting corresponding contact surfaces; - an electrical connection element between at least two at least one electrical conductor structure (50a-50c, 51a-51c) arranged on separate substrates (40, 41), wherein the carrier structure (20) comprises the at least two substrates (40, 41) and the first partial region (120); - an interdigital capacitor comprising a plurality of electrically conductive structures (10a, 10b, 10c, 10d, 10e, 10f, 10g), wherein these are arranged alternately in two different planes (35, 36) running parallel to one another. Method according to the preceding claim, wherein in method step a) additional mechanical protective structures (600) or monitor structures (2000) are created which are designed to prevent unwanted mechanical damage to the electrical probe tip. Method according to one of the preceding claims, wherein the introduction of the at least one undercut (20a, 20b, 20c, 20d, 20e, 20f, 20g, 20h) into the carrier structure (20) is carried out in such a way that an effective permittivity of a mode (80) guided in the at least one electrical line structure (1) is thereby set along a propagation direction of the mode (80). Method according to one of the preceding claims, wherein the production of the carrier structure (20) takes place by means of a microstructuring method, in particular selected from a multiphoton polymerization method or a stereolithography method. Method according to one of the preceding claims, wherein the at least one electrical line structure (1) varies in cross section along the propagation direction of the electromagnetic signal or follows a non-planar trajectory which is predetermined by a non-planar shape of the carrier structure (20). Method according to one of the preceding claims, wherein the first partial region (120) of the support structure (20) and the second partial region (220) of the support structure (20) - completely or partially enclose one another; - are disjoint or non-overlapping; - overlap at least in regions; - are identical. Method according to one of the preceding claims, wherein the production of at least one additional shading structure (70, 71) on the at least one electrical line transition (60a-60c, 61a-61c) takes place in such a way that when the carrier structure (20) is coated using the electrically conductive material along the projection direction (100) - at least one further electrically conductive connection is formed between the at least two already existing electrical line structures (50a-50c, 51a-51c, 51) and the at least one electrical line structure (1); or - the at least two already existing electrical line structures (50a-50c, 51a-51c) remain electrically insulated from one another. Method according to the preceding claim, wherein the at least one additional shading structure (70, 71) or a protective layer (75) is applied to further parts of the substrate (40, 41) in such a way that the further parts of the substrate (40, 41) are protected from being covered with the conductive material. Method according to one of the two preceding claims, wherein the production of the at least one additional shading structure (70, 71) or the protective layer (75) takes place by means of a microstructuring method, in particular selected from a multiphoton polymerization method or a projection lithography method. Method according to one of the three preceding claims, wherein the at least one additional shading structure (70, 71) or the protective layer (75) is removed after coating the carrier structure (20), in particular by means of a lift-off process or by means of peeling off the at least one additional shading structure (70, 71). Electrical line arrangement, comprising: - a carrier structure (20) comprising ◯ at least one first partial region (120) designed as a three-dimensional free-form structure and produced by means of a three-dimensional structuring process, and ◯ a second partial region (220) comprising an electrically insulating material, wherein the carrier structure (20) has at least one undercut (20a, 20b, 20c, 20d, 20e, 20f, 20g, 20h) with respect to a projection direction (100); and - at least one electrical line structure (1) applied to the carrier structure (20) as a coating by means of at least one spatially directed coating process with at least one electrically conductive material along the projection direction (100) aligned with the at least one undercut (20a, 20b, 20c, 20d, 20e, 20f, 20g, 20h). Electrical line arrangement according to the preceding claim, wherein the coating of the carrier structure (20) comprises at least two mutually different electrically conductive materials. Electrical line arrangement according to one of the preceding claims relating to the electrical line arrangement, wherein the thickness of the at least one electrical line structure (1), comprising the electrically conductive structures (10a, 10b, 10c, 10d, 10e, 10f, 10g), is increased by galvanic growth. Electrical line arrangement according to one of the preceding claims relating to the electrical line arrangement, wherein the at least one electrical line structure (1) comprises at least one electrically conductive structure (10a, 10b, 10c, 10d, 10e, 10f, 10g) which is electrically insulated from a further electrically conductive structure (10a, 10b, 10c, 10d, 10e, 10f, 10g) adjacent to the at least one electrically conductive structure (10a, 10b, 10c, 10d, 10e, 10f, 10g) within a cross-sectional area of the at least one electrical conductor structure (1) by means of at least one free area (30a, 30b, 30c, 30d, 30e, 30f, 30g, 30h) generated by the at least one undercut (20a, 20b, 20c, 20d, 20e, 20f, 20g, 20h). Electrical line arrangement according to one of the preceding claims relating to the electrical line arrangement, wherein the carrier structure (20) comprises a substrate (40, 41). Electrical line arrangement according to one of the preceding claims relating to the electrical line arrangement, wherein the at least one electrical line structure (1) is selected from: - a microstrip line comprising a single structure (10a) that is electrically conductive in all cross-sectional planes along the at least one electrical line structure (1); - a slot line comprising two electrically conductive structures (10a, 10b) that are electrically insulated from one another in all cross-sectional planes along the at least one electrical line structure (1); - a coplanar line comprising three electrically conductive structures (10a, 10b, 10c) that are electrically insulated from one another in all cross-sectional planes along the at least one electrical line structure (1); - an antenna, comprising the production of at least one electrically conductive structure (10a) which, in cooperation with the at least one free area (30a, 30b, 30c, 30d, 20e, 20f, 20g, 20h) generated by the at least one undercut (20a, 20b, 20c, 20d, 20e, 20f, 30g, 30h), is designed to provide a transition of an electrical signal bound to the at least one electrically conductive structure (10a) to a free wave space; - an electrical line coupler comprising three electrically conductive structures (10a, 10b, 10c) which are insulated from one another in all cross-sectional planes along the at least one electrical line structure (1), wherein two of the electrically conductive structures (10a, 10c) are at different electrical potentials from one another, wherein a distance between the two electrically conductive structures (10a, 10c) is selected such that a coupling of an electrical field (80) from one electrically conductive structure (10a) to the other electrically conductive structure (10c) is set via the third electrically conductive structure (10b); - an electrical probe tip which has at least one contact element (500) suitable for contacting corresponding contact surfaces; - an electrical connection element between at least two electrical conduction structures (50a-50c, 51a-51c) arranged on separate substrates (40, 41), wherein the carrier structure (20) comprises the at least two substrates (40, 41) and the first partial region (120); or - an interdigital capacitor comprising a plurality of electrically conductive structures (10a, 10b, 10c, 10d, 10e, 10f, 10g), wherein these are arranged essentially alternately in two different planes (35, 36) running parallel to one another, and wherein these can be at different potentials. Electrical line arrangement according to the preceding claim, comprising additional mechanical protection structures (600) or monitor structures (2000) which are designed to prevent unwanted mechanical damage to the probe tip. Electrical line arrangement according to one of the preceding claims relating to the electrical line arrangement, wherein the undercuts (20a, 20b, 20c, 20d, 20e, 20f, 20g, 20h) in the carrier structure (20) are designed such that an effective permittivity of a mode (80) guided in the at least one electrical line structure (1) is thereby set along a propagation direction of the mode (80). Electrical line arrangement according to one of the preceding claims relating to the electrical line arrangement, wherein the at least one electrical line structure (1) varies in cross section along the propagation direction of the electromagnetic signal or follows a non-planar trajectory which is predetermined by a non-planar shape of the carrier structure (20). Electrical line arrangement according to one of the preceding claims relating to the electrical line arrangement, wherein the first partial region (120) of the support structure (20) and the second partial region (220) of the support structure (20) - completely or partially enclose one another; - are disjoint or non-overlapping; - overlap at least in regions; - are identical. Electrical line arrangement according to one of the preceding claims relating to the electrical line arrangement, comprising at least one additional shading structure (70, 71) or a protective layer (75) which are applied to further parts of the substrate (40, 41) in such a way that the further parts of the substrate (40, 41) are protected from Covering with the conductive material.

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