DE102020211852A1 - Gate driver device and circuit configuration - Google Patents

Abstract

The invention relates to a gate driver module (1) for switching a power transistor (LT) on and off, comprising at least two switchable voltage sources (Vp, Vs) and at least two outputs (A1, A2) to which on and off resistors (RG1, RG2) can be connected, a configuration unit (3) being provided in which a higher-level circuit configuration of the gate driver module (1) is stored or can be recorded in relation to other gate driver modules, the gate driver module (1) also having a logic Has a unit (4) which is designed to receive a PWM signal from a higher-level control unit (20) and to switch the switchable voltage sources (Vp, Vs) as a function of the PWM signal, the logic unit (4) is further designed in such a way to store the PWM signal for at least one clock cycle, the gate driver module (1) having at least one error unit (5) which is designed in such a way that at least one internal error ler of the gate driver module (1) to at least one adjacent gate driver module and/or the higher-level control unit (20) and to receive an error message from at least one adjacent gate driver module and/or the higher-level control unit (20), the logic Unit (4) is further designed to generate a PWM signal as a function of an error message from the error unit (5), the stored or detected circuit configuration and the stored PWM signal in order to switch off a connected power transistor (LT), and a circuit configuration.

Description

The invention relates to a gate driver module and a circuit configuration with a large number of gate driver modules.

Gate driver components of this type are used to switch power transistors on and off, which can be connected up in various circuit configurations. Examples are AC voltage rectifiers with, for example, three half-bridges or 3-level half-bridge circuits, each with four power transistors per half-bridge. In the event of an error, the gate driver components must switch off the defective power transistors.

From the DE 103 51 033 A1 an integrated gate driver circuit for switching power transistors using external control is known. The integrated gate driver circuit detects desaturation of the power transistor, protecting a desaturated transistor from transient overvoltages by softly turning off the desaturated transistor via a soft turn-off sequence. A fault control circuit of the gate driver integrated circuit handles protection against supply undervoltage and the transistor desaturation is able to communicate with a plurality of gate driver integrated circuits in a multi-phase system using a dedicated local area network.

The invention is based on the technical problem of creating an improved gate driver module and a circuit configuration with gate driver modules of this type.

The technical problem is solved by a gate driver module with the features of claim 1 and a circuit configuration with the features of claim 5. Further advantageous refinements of the invention result from the dependent claims.

For this purpose, the gate driver component for switching a power transistor on and off comprises at least two switchable voltage sources and at least two outputs to which switch-on and switch-off resistors can be connected. The gate driver module also includes a configuration unit in which a superordinate circuit configuration of the gate driver module in relation to other gate driver modules is stored or can be recorded. For example, the higher-level circuit configuration is transmitted and stored by a higher-level control unit. In addition or as an alternative, this is encoded by a discrete wiring, which can then be read out or recorded by the configuration unit. For example, the gate driver component knows that this is part of a 3-level half-bridge circuit and controls the top power transistor. The gate driver component therefore knows the higher-level circuit configuration and its place in this circuit configuration. The gate driver module also has a logic unit that is designed to receive a PWM signal from a higher-level control unit and to switch the switchable voltage sources as a function of the PWM signal, with the logic unit being designed such that Store PWM signal for at least one clock cycle. The gate driver module also has at least one error unit, which is designed to forward at least one internal error in the gate driver module to at least one neighboring gate driver module and/or the higher-level control unit and an error message from at least one neighboring gate driver module and /or to receive the higher-level control unit, the logic unit being further designed to generate a PWM signal depending on an error message from the error unit, the stored or detected circuit configuration and the stored PWM signal in order to switch off a connected power transistor . Thus, when a fault occurs in a power transistor in a circuit configuration, the power transistors that need to be switched off can be switched off in a predetermined switch-off sequence in order to avoid repercussions such as overvoltages on adjacent power transistors. For example, if the uppermost gate driver component in a 3-level half-bridge circuit detects a fault in its assigned power transistor, the other three gate driver components are informed first. The two internal gate driver components then then switch off their power transistors before the two external gate driver components switch off their power transistors. A defective power transistor is therefore not switched off immediately without regard to the other power transistors. Rather, the power transistors are guided, optionally driven over a number of cycles.

If control signals (PWM) are lost or absent, the switch-off procedure required for safe switch-off is adhered to and an impermissibly high voltage cannot arise at the power transistors at any time.

In one embodiment, the gate driver module is designed in such a way that it receives at least one temperature of the power transistor and/or one output current of the power transistor, since the fault cases that occur most frequently can be determined from these parameters. In addition, other parameters can also be received, such as voltage loads on the power transistors. From these, for example, a future error can then be predicted or estimated.

In a further embodiment, the gate driver module has at least one third switchable output to which at least one current source can be connected in parallel with the input and output resistors. In this case, the at least one current source, like the input and output resistors, can be arranged outside of the gate driver module or, like the voltage source, can be integrated into the gate driver module. By means of the switchable power source, the switch-on process can be accelerated, for example, with the power source then being switched off again. It is also possible to use such a current source for rapid turn-off, the gate state then being maintained by the voltage sources in static operation. The design with a third switchable output represents an independent invention even without the logic, error and configuration unit.

The circuit configuration has a large number of gate driver components, with the error units of the gate driver components being connected to one another in the form of a daisy chain, so that local control of the circuit configuration is possible.

In a further embodiment, the higher-level control unit is integrated into the daisy chain, so that further errors can also be transmitted.

In a further embodiment, the circuit configuration is in the form of a 3-level half-bridge circuit.

• 1 ein schematisches Blockschaltbild eines Gate-Treiberbausteins mit externer Beschaltung,
• 2 eine 3-Level-Halbbrückeschaltung als Schaltungskonfiguration mit einer Daisy-Chain-Verkettung ohne übergeordnete Steuereinheit und
• 3 eine 3-Level-Halbbrückenschaltung als Schaltungskonfiguration mit einer Daisy-Chain-Verkettung mit eingebundener übergeordneter Steuereinheit.

The invention is explained in more detail below using preferred exemplary embodiments. The figures show:

• 1 a schematic block diagram of a gate driver module with external circuitry,
• 2 a 3-level half-bridge circuit as a circuit configuration with a daisy chain concatenation without a higher-level control unit and
• 3 a 3-level half-bridge circuit as a circuit configuration with a daisy chain with an integrated higher-level control unit.

In the 1 a schematic block diagram of a gate driver module 1 for switching a power transistor LT on and off is shown. In this case, the gate driver module 1 has a first output A1, at which a series circuit composed of a capacitor C _dy and an on-resistance R _G1 is arranged, which is connected to a gate G of the power transistor LT. In parallel with this series connection, there is a turn-off resistor R _G2 at a second output A2. A current source I ₀ is connected to a third output A3. The gate driver module 1 also has a configuration unit 2, a logic unit 3, an error unit 4 and an isolated voltage supply 5, which supplies two switchable voltage sources V _p , V _s and the supply voltage for the units 2-4 delivers. The gate driver module 1 also has a switching module 6 with four switches S1-S4 and an amplifier 7. The configuration unit 2 receives a configuration signal SPI from a higher-level control unit (not shown), from which a higher-level circuit configuration and the position of the gate driver module can be derived 1 in this higher circuit configuration.

Alternatively or additionally, this information is encoded via a discrete interconnection that can be detected at an input D. The logic unit 3 receives a PWM signal from the higher-level control unit (not shown), which is converted by the logic unit 3 by actuating the switching elements S1-S4. Furthermore, the logic unit 3 can access the data of the configuration unit 2 and store the PWM signal. Depending on a temperature T _jct of the power transistor LT and an output current I _out of the power transistor LT, the error unit 4 generates an error signal which is present at an output Fault_out. The temperature T _jct of the power transistor is determined, for example, by means of a temperature sensor 8 and fed to the error unit 4 via the amplifier 7 . Furthermore, the error unit 4 receives an error message Fault_in from an adjacent gate driver module and/or the higher-level control unit. In this case, the error unit 4 is connected to the logic unit 3 via a connection that is not shown. If the power transistor LT is now to be switched on very quickly, the switch S3 is closed (S1, S2 and S4 remain open). After switching on, S3 is opened and S1 is closed. To switch off, S4 is closed and the other switches S1 to S3 are opened.

S4 can then be opened and S2 closed. Only one switch S1-S4 is closed at a time, with switches S1 and S3 being used for switching on and switches S2 and S4 for switching off. be there It should be noted that the sequence can also be reversed, ie S3 is closed first and then S1 or S2 is closed first and then S4.

In the event of an error, the logic unit 3 now receives an error message. The logic unit 3 knows the higher-level circuit configuration and can then use the stored PWM signal in the next step to switch off its assigned power transistor LT in coordination with the other gate driver components of the circuit configuration, without this having harmful repercussions on the other power transistors.

In the 2 a 3-level half-bridge circuit 10 is shown, which has four power transistors LT, with a center tap M and a neutral point N being provided. The power transistors LT are each driven by a gate driver module 1 . The gate driver modules 1 each receive their PWM signal PWM1-PWM4 and their configuration signal SPI from the higher-level control unit (not shown). The error inputs Fault_in and error outputs Fault_out are linked to one another in the form of a daisy chain, so that each gate driver component is informed of an error that has occurred within the circuit configuration and the subsequent shutdown of the power transistor LT can be coordinated with one another. It should be noted that a daisy chain configuration with more than 4 elements is also possible.

In the 3 an alternative embodiment is shown, in which the higher-level control unit 20 is integrated into the daisy-chain connection.

Reference List

1

gate driver device

2

configuration unit

3

logic unit

4

error unit

5

power supply

6

switching module

7

amplifier

8th

temperature sensor

10

3-level half-bridge circuit

20

control unit

LT

power transistor

G

Gate

S1-S4

counter

QUOTES INCLUDED IN DESCRIPTION

This list of documents cited by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent Literature Cited

• DE 10351033 A1 [0003]

Claims (7)

Gate driver module (1) for switching a power transistor (LT) on and off, comprising at least two switchable voltage sources (V _p , V _s ) and at least two outputs (A1, A2) to which on and off switch resistors (R _G1 , R _G2 ) can be connected, a configuration unit (3) being provided in which a higher-level circuit configuration of the gate driver module (1) is stored or can be recorded in relation to other gate driver modules, the gate driver module (1) further having a logic Has a unit (4) which is designed to receive a PWM signal from a higher-level control unit (20) and to switch the switchable voltage sources (V _p , V _s ) as a function of the PWM signal, the logic unit ( 4) is further configured to store the PWM signal for at least one clock cycle, the gate driver module (1) having at least one error unit (5) configured in such a way that at least one internal error of the gate driver is detected relay module (1) to at least one neighboring gate driver module and/or the higher-level control unit (20) and to receive an error message from at least one neighboring gate driver module and/or the higher-level control unit (20), the logic unit (4) is further designed to generate a PWM signal as a function of an error message from the error unit (5), the stored or detected circuit configuration and the stored PWM signal in order to switch off a connected power transistor (LT). gate driver chip claim 1 , characterized in that the gate driver module (1) is designed to receive at least one temperature (T _jct ) of the power transistor (LT) and/or an output current (I _out ) of the power transistor (LT). gate driver chip claim 2 , characterized in that the gate driver module (1) is designed in such a way to receive at least one further parameter of the power transistor (LT). Gate driver module according to one of the preceding claims, characterized in that the gate driver module (1) has at least one third switchable output (A3) to which at least one current source (I ₀ ) is connected in parallel with the input and output resistors (R _G1 , R _G2 ) can be connected. Circuit configuration with a large number of gate driver modules according to one of the preceding claims, characterized in that the error units (5) of the gate driver modules (1) are connected to one another in the form of a daisy chain. circuit configuration claim 5 , characterized in that the higher-level control unit (20) is integrated into the daisy chain. circuit configuration claim 5 or 6 , characterized in that the circuit configuration is designed as a 3-level half-bridge circuit (10).

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