DE102012109240B4 - Method for producing contact openings in a semiconductor body and of self-aligned contact structures on a semiconductor body - Google Patents

Abstract

A method of making contact openings (30, 122) in a semiconductor body (10, 100), the method comprising forming a plurality of self-aligned structures on a main surface (11, 106) of a semiconductor body, wherein adjacent ones of the self-aligned structures have spaced side walls facing each other by forming a plurality of trenches (12, 104) extending from the main surface (11, 106) of the semiconductor body (10, 100) into the semiconductor body; Forming a first layer (15, 108) on the major surface (11, 106) and in the trenches (12, 104), the first layer (15, 108) having recessed areas (16) above the trenches; Forming a second layer (20, 110) on the first layer, the second layer (20, 110) filling the recessed areas (16) of the first layer (15, 108); and forming apertures (30, 112) in the first and second layers (15, 20, 108, 110) extending to the major surface (11, 106) over island regions of the semiconductor body between adjacent ones of the trenches (12, 104); Forming a spacer layer (120) on the sidewalls of the self-aligned structures and forming openings (30, 122) in the semiconductor body (10, 100) between adjacent ones of the self-aligned structures while the spacer layer (120) is on the sidewalls of the self-aligned structures, such that each opening has a width and a distance to the side wall of an adjacent trench, which corresponds to a thickness of the spacer layer.

Description

GENERAL PRIOR ART

The semiconductor industry has always sought to achieve smaller feature sizes. For this it is necessary to reduce the size of the required structural elements. In this case, however, the tolerance limits must not be ignored. Self-aligned production methods are increasingly being used for this purpose and make it possible to meet the requirements for smaller structures, while at the same time meeting the required tolerance ranges.

Examples from power semiconductor technology for self-aligned structural elements are out DE 10 2004 057 237 A1 which describes contact holes for channel / source regions in the case of gate trench transistors. The contact holes are created in mesa areas between two trenches with a defined small distance from the trenches. This can be done here either with the help of so-called "spacers" or with the help of a - prepared by thermal oxidation "oxide layer" as a mask for the Kontaktlochätzen. However, the tolerances are relatively large in the case of "spacers", and in the case of the oxide masks, particularly in the case of gate trench transistors, the gate trench must be made with a greater depth in order for the thermal oxidation to be carried out.

From the US Pat. No. 7,851,349 B2 For example, a method for producing a connecting element between two semiconductor regions arranged one above the other is known. In the WO 2008/121991 A1 A method of making a self-aligned trench MOSFET is described. Further methods for the production of semiconductor devices are known from DE 40 42 163 A1 as well as the DE 10 2010 046 213 B3 known.

It is an object of the invention to provide a method of manufacturing a structural element having small tolerance limits and a self-aligned structural element in a semiconductor component. A solution to the problem is given in the independent claims. Further embodiments are defined in the dependent claims.

BRIEF SUMMARY OF THE INVENTION

Embodiments described herein provide a method of fabricating a feature with small tolerance limits and a self-aligned feature in a semiconductor component.

Embodiments of the method generally include the following features:
Providing a semiconductor body having a surface; Forming a cutout on the surface, the cutout extending from the surface of the semiconductor body into the semiconductor body in a direction perpendicular to the surface, the cutout having a base and at least one sidewall; Producing a first auxiliary layer on the surface and in the cut-out such that the first auxiliary layer forms a trough over the cut-out, the trough having a trough base and at least one trough sidewall forming an angle α in the range of 20 ° to 80 ° with respect to the surface of the semiconductor body forms; Forming a second auxiliary layer in the well at the well base and at the at least one well side wall, wherein the auxiliary layer and the second auxiliary layer form a common surface at an identical surface height, the second auxiliary layer being made of a different material than the first auxiliary layer; and selectively removing the regions of the first auxiliary layer that are not covered by the second auxiliary layer.

The adjustment of the angle α of the trough side walls can be set very precisely. With the aid of the angle α, a distance extending from the cutout over the surface of the semiconductor body can also be defined very precisely. Because of the different materials of the first and second auxiliary layers, by means of the selective removal of the first auxiliary layer due to the protective effect of the second auxiliary layer on the first auxiliary layer, the width and therefore the lateral overlap of the first auxiliary layer over the surface of the semiconductor body with the help the set angle α are produced very precisely. In this case, the choice of the angle α in conjunction with the thickness of the first auxiliary layer on the surface of the semiconductor body allows the setting of a very small lateral overlap of the first auxiliary layer over the surface of the semiconductor body. This therefore represents a self-aligned method with small tolerance limits, whereby spacings with respect to the cutout in the semiconductor body can be set very precisely and can be kept very small. In particular, a feature fabricated according to the method is suitable for use as a masking layer for subsequent further processing of the semiconductor body for a semiconductor component such as, for example, as a masking layer in an etching or implantation process.

Development of the method provides the first auxiliary layer to be produced by an HDP process. An HDP process is a process for chemically depositing a material from the gas phase, which simultaneously has a sputtering effect the deposited material, that is, the deposited material is also removed by impinging particles, particularly at occurring edges of the deposited material, but the deposition rate is higher than the sputtering rate. As a result, layer growth occurs throughout an HDP process. However, edges in the deposited material experience flattening, thus resulting in an inclined surface of the deposited material at the edge, particularly at an angle in the range of 35 ° to 50 ° with respect to a major surface.

In particular, in an HDP process, it may therefore be necessary to protect an already existing edge, such as, for example, the edge of the cutout with respect to the surface of the semiconductor body, prior to removal by the sputtering effect of the HDP process. For this purpose, in one embodiment, for example, before producing the first auxiliary layer on the surface of the semiconductor body and in the cutout, a continuous protective layer is produced.

Development of the process provides for the second auxiliary layer to be made by depositing the other material in the well. Consequently, the trough sidewalls are retained in their original shape and consequently, even in subsequent process steps, they still have the same dimensions, in particular the same angle α, as before the deposition of the second auxiliary layer.

It is a particularly simple production variant if the second auxiliary layer completely fills the trough. In particular, if the common surface of the first and second auxiliary layers is formed by a CMP method, first the second auxiliary layer may be formed over the entire area in the well and also over the first auxiliary layer, and thereafter, by means of uniform removal, the common surface of the First and second auxiliary layer can be set very precisely on an identical surface level. In the case of a CMP processor used, the removal is followed first mechanically and then chemically in the final phase, whereby the chemical removal can be terminated very precisely on the first auxiliary layer.

One embodiment of the method provides for removing the second auxiliary layer from the well after the process of selectively removing the regions of the first auxiliary layer that are not covered by the second auxiliary layer.

This can be realized, in particular, when the second auxiliary layer is removed during the production of a trench in the semiconductor body. For example, when a material is used for the second auxiliary layer that can be etched using an etch medium identical to that used for the semiconductor body, removal of the second auxiliary layer during trench etching into the semiconductor body is possible without additional effort. In particular, in this case, the first auxiliary layer made of a different material may serve as a mask for the trench etching process.

An exemplary embodiment of a semiconductor component comprises the following structural features: a semiconductor body having a surface; a cutout in the semiconductor body, the cutout extending from the surface of the semiconductor body into the semiconductor body in a direction perpendicular to the surface, and the cutout having a base and at least one sidewall; a layer on the surface of the semiconductor body and in the cutout, the layer forming a trough over the cutout, the trough having a trough base and at least one trough sidewall, the at least one trough sidewall forming an angle α in the range of 20 ° to 80 ° forms the surface of the semiconductor body, and wherein the layer has at least one edge 22 which, starting from the trough edge, extends in the direction of the surface of the semiconductor body.

The layer on the surface of the semiconductor body is dimensioned in a self-aligned manner by the angle α of the trough side wall and has only a very small tolerance range.

In particular, it is thus possible to provide a semiconductor element in which the layer covers the surface of the semiconductor body, starting from the side wall of the section, over a distance x in the range of 50 nm to 150 nm.

An embodiment of the semiconductor component may provide for a trench to be formed in the semiconductor body, the trench having at least one trench sidewall extending into the semiconductor body from the edge of the layer.

In this variant, the layer may be used as a mask layer for trench etching or subsequent process steps such as, for example, implants, which enables very precise features feature sizes, in particular a very precise and small distance between the cutout and the trench produced.

According to a further embodiment, a method for producing contact openings in a semiconductor body comprises: forming a plurality of self-aligned structures on one Main surface of a semiconductor body, wherein each self-aligned structure fills a trench formed in the semiconductor body and extending over and onto the main surface, adjacent ones of the self-aligned structures having spaced sidewalls facing each other; Forming a spacer layer on the sidewalls of the self-aligned structures and forming openings in the semiconductor body between adjacent ones of the self-aligned structures while the spacer layer is on the sidewalls of the self-aligned structures such that each opening has a width and a distance to the side wall of an adjacent trench that corresponds to a thickness of the spacer layer.

According to one embodiment of a method for producing self-aligned contact structures on a semiconductor body, the method comprises: forming a plurality of trenches extending from a main surface of a semiconductor body into the semiconductor body;
Forming a conductive plate in a lower part of the trenches and isolated from the semiconductor body;
Forming a first material on the major surface and on the conductive plates in the trenches, the first material having recessed regions over the trenches; Filling the recessed areas of the first material with a second material; Forming openings in the first material extending to the major surface over island regions of the semiconductor body between adjacent ones of the trenches to form a plurality of spaced self-aligned structures with the second material in the recessed regions of the first material; Forming grooves in the semiconductor body between adjacent ones of the self-aligned structures and filling the grooves and open gaps between adjacent ones of the self-aligned structures with a material having a different etch selectivity than the first and second materials.

Those skilled in the art will recognize further features and advantages upon reading the following detailed description and upon consideration of the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The elements of the drawings are not necessarily to scale relative to one another. Like reference numerals designate corresponding similar parts. The features of the various illustrated embodiments may be combined unless they are mutually exclusive. Embodiments are illustrated in the drawings and detailed in the description which follows.

1 shows in schematic cross-sectional views 1a to 1e individual exemplary method steps of a method for producing a structural element.

2 shows in a schematic cross section a further method step in the method for producing a structural element.

3 shows in a schematic cross section an excerpt of an exemplary semiconductor component with self-aligned structural elements.

4 shows in a schematic cross-sectional view of an excerpt from a gate trench power transistor.

5 shows in schematic cross-sectional views 5a to 5c individual exemplary method steps of a method for producing contact openings in a semiconductor body.

6 shows in schematic cross-sectional views 5a to 5h individual exemplary method steps of a method for producing self-aligned contact structures on a semiconductor body.

DETAILED DESCRIPTION

1a shows a semiconductor body 10 with a first surface 11 , The semiconductor body 10 can be made of any known semiconductor material, in particular of silicon. Depending on the application, the semiconductor body 10 be n-doped or p-doped. In particular, the semiconductor body 10 also comprise a semiconductor substrate having an epitaxial layer deposited thereon, wherein the semiconductor substrate and the epitaxial layer may be differently doped. The epitaxial layer could then be the surface 11 exhibit. For the exemplary use of the semiconductor body 10 in a power semiconductor component, that is to say in a semiconductor component in which voltages of up to hundreds or even thousands of volts can be present between two electrodes, such a semiconductor body exists 10 generally of a heavily doped semiconductor substrate and a lightly doped epitaxial layer deposited thereon.

1b shows one on the surface 11 of the semiconductor body 10 made cutting 12 , In this case, the section extends 12 from the surface 12 of the semiconductor body 10 in the semiconductor body 10 in a direction perpendicular to the surface 11 , The cutout has a base 13 and sidewalls 14 on.

The cutout 12 which may have a depth of a few nanometers to a number of microns may elongate into the semiconductor body 10 extending trench or otherwise a point-shaped depression in the semiconductor body 10 be, wherein the shape of such a punctiform depression may be round, square or hexagonal, for example, in plan view. There may also be other functional elements of a semiconductor component in the detail 12 be educated. By way of example, in the section 12 also electrodes are produced, as they occur for example in power semiconductor components. In these cases is exemplified in the section 12 a channel control electrode (gate electrode) is formed. In addition, in the clipping 12 even more electrodes such as field plates are produced.

1c shows the structure after making a first auxiliary layer 15 on the surface 11 and in the clipping 12 , In this case, the first auxiliary layer forms 15 even a hollow 16 over the clipping 12 , where the trough 16 a trough base 17 and trough sidewalls 18 having. In this case, the trough sidewalls form 18 an angle α with respect to the surface 11 of the semiconductor body 10 , The angle α may have a value in the range of 20 ° to 80 °.

In this case, the first auxiliary layer 15 from a different material with respect to the material of the semiconductor body 10 produced. By way of example, the material of the first auxiliary layer 15 be a dielectric. In particular, in this case, an oxide such as, for example, SiO ₂ is suitable.

In this case, the production is effected such that the trough 16 over the clipping 12 is formed and the desired angle α is set. In this case, the trough sidewalls extend 18 over the edge of the side walls 14 of the clipping 12 and over a defined distance x of the surface 11 of the semiconductor body 10 , The distance x is defined by the angle α and may, for example, be between 50 nm and 150 nm. In this case, the distance x also depends on the layer thickness of the auxiliary layer 15 from. In this case, typical layer thicknesses are for example in the range of 100 nm to 500 nm.

The first auxiliary layer 15 can in the clipping 12 either directly at the base 13 or otherwise on functional elements already in the clipping 12 are present, such as, for example, the already mentioned gate electrode produced.

The first auxiliary layer 15 can be produced using, for example, an HDP (High Density Plasma) process. Such a process is a combination of a vapor phase deposition process and a sputtering process wherein material is removed, especially at present edges. With the help of such a HDP process, the formation of the inclined Muldenseitenwände 18 be realized with the angle α in a particularly simple manner by adjusting the sputtering power and the deposition rates. Typical values of the sputtering power are, for example, about 1000 watts. In this case, for example, the present surface is treated with arsenic for about 82 seconds, oxygen for about 234 seconds, or SiH ₄ for about 100 seconds.

1d shows one in the hollow 16 prepared second auxiliary layer 20 , In this case, the second auxiliary layer 20 first over the whole area on the trough base 17 , the trough sidewalls 18 and on a surface of the first auxiliary layer 15 getting produced. This can be done, for example, by means of a process of depositing another material relative to the material of the first auxiliary layer 15 from the gas phase. Exemplified is doped or undoped polysilicon or a nitride such as, for example, silicon nitride as the material for the second auxiliary layer 20 appropriate.

After deposition over the entire area becomes the second auxiliary layer 20 from the surface of the first auxiliary layer 15 removed, leaving the second auxiliary layer 20 only in the hollow 16 remains. The removal of the second auxiliary layer 20 from the surface of the first auxiliary layer 15 can be effected, for example, by a chemical-mechanical polishing (CMP) process. In this case, the second auxiliary layer becomes 20 in a first method step mechanically such as with the aid of, for example, loops and lobes to just over the surface of the first auxiliary layer 15 away. In a further method step during the CMP, the second auxiliary layer 20 then finally and completely from the surface of the first auxiliary layer 20 removed by means of a chemical etching step, as a result of a common surface 21 the first auxiliary layer 15 and the second auxiliary layer 20 in the hollow 16 remains formed at an identical surface height and a transition between the first auxiliary layer 15 and the second auxiliary layer 20 at the trough edge 23 on the surface 21 arises. In this case, the surface of the first auxiliary layer 15 serve as an etch stop. Alternatively, the second auxiliary layer 20 also be removed by means of an isotropic etching process.

The remaining second auxiliary layer 20 can the trough 16 (as shown) only partially fill or otherwise the trough 16 completely through the second auxiliary layer 20 be filled. In this case would the in 1d illustrated common surface 21 continuously over the whole trough 16 be formed.

1e shows the situation after the selective removal of the first auxiliary layer 15 the areas not covered by the second auxiliary layer 20 are covered. The selective removal is preferably by means of selective etching of the material of the first auxiliary layer 15 with respect to the material of the second auxiliary layer 20 causes. In this case, selectivity should be understood as meaning a relationship of the etch rates of the two different materials in a ratio of at least 10: 1. In this case, the first auxiliary layer 15 by means of an isotropic etching process at the junction of the first auxiliary layer 15 to the second auxiliary layer 20 at the trough edge 23 on the surface 21 as good as perpendicular in one direction to the semiconductor body surface 11 be etched. This leads to a structural element that consists of the first auxiliary layer 15 and the second auxiliary layer 20 exists and that one edge 22 extending in a manner different from the trough edge 23 on the surface 21 in one direction on the surface 11 of the semiconductor body 10 emanates. Due to erosion of the second auxiliary layer 20 can the edge 22 also a slightly rounded shape at the trough edge 23 have, so that the edge at the trough edge 23 between the second auxiliary layer 20 and the edge 22 forms no angle of 90 °, but rather a smaller angle, generally an angle in the range of 45 ° to 90 °, in particular between 75 ° and 80 °. Such a rounded edge on the trough edge 23 is in an excerpt in 1E ' shown.

2 shows an embodiment of the method, wherein prior to the preparation of the first auxiliary layer 15 a continuous protective layer 25 on the surface 11 of the semiconductor body 10 and in the clipping 12 is made, leaving the edge on the surface 11 concerning the side walls 14 of the clipping 12 from the protective layer 25 is covered. As a result, this edge of the semiconductor body is 10 during an exemplary HDP process for depositing the first auxiliary layer 15 protected from being removed by the sputtering effect of the HDP process.

3 shows an embodiment of the method, wherein a trench 30 in the semiconductor body 10 with the layer 15 is produced as a mask layer. In this case, the trench 30 be prepared by means of an anisotropic etching process, wherein in the case of an exemplary silicon semiconductor body 10 and a polysilicon as a material for the second auxiliary layer 20 the second auxiliary layer 20 equally etched simultaneously and thus with the anisotropic etching of the trench 30 is removed, leaving the trough base 17 and the trough sidewalls 18 are uncovered.

4 illustrates an example of a semiconductor component with a gate trench as a detail 12 , A field electrode 36 is in a lower area in the gutter trench 12 formed, wherein the field electrode by a field dielectric 37 from the semiconductor body 10 is isolated. A channel control electrode 35 is in an upper area of the gate trench 12 on one of the field electrodes 36 isolated manner arranged. The channel control electrode 35 is also from a canal zone 38 that in the semiconductor body 10 is formed by a gate dielectric 41 , For example, a SiO ₂ gate dielectric isolated. The gate dielectric 41 is so embodied that it is thinner than the field dielectric 37 , The canal zone 38 is located along the gate trench 12 between one in the semiconductor body 10 trained source zone 39 and a drain zone 40 at the field electrode 36 , A layer 15 is in the gutter 12 over the channel control electrode 35 arranged, the layer 15 a hollow 16 above the gate trench 12 forms. In this case, the trough points 16 a trough base 17 and trough sidewalls 18 at an angle in the range of 20 ° to 80 °, in particular in the range of about 40 ° to 45 °, with respect to the surface 11 of the semiconductor body 10 form. The layer 15 is from an edge 22 limited. The edge 22 extends to one of the trough edge 23 outgoing way in one direction to the surface 11 of the semiconductor body 10 , The layer 15 covers the surface 11 of the semiconductor body 10 being from a side wall of the gutter trench 12 assumes a distance x, for example in the range of 50 nm to 150 nm.

In the semiconductor component, as in the example 4 shown can be a ditch 30 in the semiconductor body 10 be formed. In this case, the ditch points 30 a trench sidewall 42 on, focusing on one of the edge 22 the layer 15 outgoing way into the semiconductor body 10 extends. A common connection electrode for the source zone 39 and the channel zone 38 can ditch in the 30 be arranged.

The embodiment of an in 4 Semiconductor component shown as an excerpt is a MOS field effect transistor for applications that provide voltages of between about 20 volts to hundreds of volts between source and drain.

The layer 15 can be made by the method described above and serves as a mask layer for the formation of the contact hole trench 30 , Through this self-aligned layer 15 can the contact hole trench 30 a very small distance from the gate trench 12 exhibit. Consequently, it is possible to divide, that is the distance between two parallel gate trenches 12 to significantly reduce compared to previous distances. For example, prior solutions have a pitch of about 950 nm, which results from the fact that the contact hole for the source / channel region junction must be taken between the two gate trenches. Due to the self-aligned mask layer 15 For example, the pitch can be reduced to 750 nm. Consequently, the channel for the MOSFET can also be made shorter because the field does not penetrate into the channel zone to such a large extent. In addition, the presented method steps for fabricating the structure element can be implemented in existing methods for producing gate transistors without much additional effort.

The spacing between adjacent cells may be further reduced or optimized using the self-aligned process described next. This self-aligned process is related to the 5A to 5C described.

In 5A shows a semiconductor body 100 such as the type previously described herein, after multiple processing steps are performed, to self-aligned mesa structures 102 train. trenches 104 extend from a first main surface 106 of the body 100 in the semiconductor body 100 , An HDP deposition step, for example, as described hereinbefore, is then performed to apply to the semiconductor body 100 an HDP layer 108 train and the trenches 104 to fill. Next is carbon or any other suitable material 110 deposited to fill the HDP profile, the wells or recessed areas according to the shape of the trenches 104 having. The excess filler 110 is removed, for example, using an etchback and / or a CMP process performed on the HDP material 108 stops. openings 112 are then in the HDP material 108 between adjacent trenches 104 formed, resulting in self-aligned HDP mesa structures 102 result.

The side walls 114 HDP mesa structures 102 may be tapered or not tapered depending on the etching process used. The distance d1 between adjacent HDP mesa structures 102 determines the spacing between adjacent device cells. The device cells are partially in the trenches 104 formed, for example, a gate and a gate dielectric in the trenches 104 (e.g., as previously described herein with reference to FIGS 4 described), and body and source regions of the device can in the islands 116 of the semiconductor body 100 between adjacent trenches 104 be formed. The semiconductor body islands 116 are then processed to form the components.

This processing involves the formation of contact openings 122 in the semiconductor islands 116 and implanting dopant species in the islands 116 through the contact openings 122 , The minimum distance d2 between the contact openings 122 and the side walls 118 the neighboring trenches 104 should be large enough (for example, about 50-100 nm) to allow ion implantation interactions in the contact holes 122 with already implanted areas (eg the body) or the trench sidewalls 118 to suppress lining oxides. Otherwise, electrical parameters may shift and degrade component quality. On the other hand, the contact openings 122 not too tight, z. B. less than <70 nm to avoid problems with high electrical resistance or filling problems (cavities).

5B shows the semiconductor body 100 after a TEOS (tetraethyl orthosilicate) or carbon deposition process is performed to target the semiconductor body 100 and the HDP mesa structures 102 a TEOS / carbon spacer layer 120 train. The thickness of this TEOS / carbon spacer layer 120 determines the width w of the contact openings 122 in the islands 116 of the semiconductor body 100 between adjacent trenches 104 and the distance d2 between the contact openings 122 and the side walls 118 the neighboring trenches 104 ,

The thickness of this TEOS / carbon spacer layer 120 may be regardless of the actual distance d1 between adjacent mesas 102 be predetermined. In one embodiment, the thickness of the TEOS / carbon spacer layer becomes 120 on the basis of a certain assumption for the width w of the contact openings 122 chosen, for example by accepting a wide contact opening. In another embodiment, the thickness of the TEOS / carbon spacer layer becomes 120 based on the measured distance between adjacent ones of the HDP mesa structures 102 certainly.

The distance between adjacent HDP mesa structures 102 For example, it can be measured using SEM (Scanning Electron Microscopy) or any other suitable electron microscopy technology. The measurement may be at multiple points on the wafer (eg, center, edge, etc.) to account for variation across the wafer. The mean of the readings may be with a target value for the distance between adjacent HDP mesa structures 102 be compared. Usually, the (measured) average is greater than the Target value. This difference represents that for the TEOS / carbon spacer layer 120 required thickness to reach the target value after processing. Typical uniformity signatures of HDP deposition, etching, and TEOS / carbon deposition may be taken into account to achieve greater uniformity.

The TEOS / carbon capture process can be performed in a closed loop environment. This provides high-precision control of the layer thickness, thereby providing a high-precision contact opening width w in the semiconductor body islands 116 and a high-precision distance d2 between the contact holes 122 and the side walls 118 the neighboring trenches 104 is achieved. The intracell spacing can be optimized if precise control of these critical parameters is provided. A variable time may also be used during the TEOS / carbon film deposition process to achieve even more precise control.

5C shows the semiconductor body 100 after the contact openings 122 in the islands 116 of the semiconductor body 100 are formed. The width w of the contact openings 122 and the distance d2 between each contact hole 122 and the side walls 118 the neighboring trenches 104 is based on the thickness of the TEOS / carbon spacer layer 120 determined as described above. The bottom part of the TEOS / carbon spacer layer 120 on the first main surface 106 of the semiconductor body 100 is deposited, is removed, leaving contact openings 122 in the islands 116 can be trained. An anisotropic etching process is used to contact the openings 122 with the desired width w and the desired trench sidewall spacing d2. Optionally, the TEOS / carbon spacer layer 120 be removed. The source region (and a body region, if not previously formed) are formed by ion implantation. For this dopant species of the corresponding conductivity through the contact openings 122 into the semiconductor body islands 116 implanted. The contact openings 122 are then filled with an electrically conductive material to provide electrical contact to the source and body regions. The source electrode, the body and corresponding contacts are for ease of illustration 5A to 5C Not shown.

In the 5A to 5C shown self-aligned process embodiment can for relatively small-scale technologies, eg. Division ~ 400-1500 nm and mesa width ~ 100-1000 nm. Of course, these dimensions depend on the particular semiconductor technology used. If the contact implant uses a very high energy, the effect of lateral spread on the electrical behavior could also be avoided using this narrowing procedure, even if the technology uses larger dimensions.

The 6A to 6H illustrate cross-sectional views of a semiconductor body 200 during various steps of a method of forming self-aligned contact structures. 6A shows the semiconductor body 200 after ditches 202 in the body 200 etched, wherein a field oxide 204 along the side walls 203 and the soil 205 the trenches 202 is formed, the trenches 202 are filled with a conductive material such as polysilicon and the conductive material is etched back to field plates 206 in the lower part of the trenches 202 train. The field plates 206 are indicated in the figures with an 'S' to indicate that the field plates 206 can be connected to the source potential.

6B shows the semiconductor body 200 after HF (hydrogen fluoride) machining, which is the field oxide 204 from the upper part of the trenches 202 away. The field oxide 204 remains in the lower part of the trenches 202 to the field plates 206 to isolate against the surrounding semiconductor material. Optional source and body implants may be performed at this point to form source and body regions, for example by filling the trenches 202 with a resist, etching back the resist to the main surface 201 of the semiconductor body 200 and implanting a dopant species having the corresponding conductivity into the semiconductor body 200 , Otherwise, the source and / or body areas can be formed later or earlier.

6C shows the semiconductor body 200 after an HDP deposition is performed, e.g. As described hereinbefore, to an HDP layer 208 on the semiconductor body 200 and in the trenches 202 train. The field plate 206 is deep in the trenches 202 let in, leaving a gate ladder in the trenches afterwards 202 over the field plates 206 can be trained (in 6E shown). Such a deep recess provides an HDP profile that is more pronounced and allows for a wider process window and more tolerance to subsequent process variations such as subsequent grooving (in 6E shown).

6D shows the semiconductor body 200 after carbon, C 'has been deposited to fill the HDP profile, which has valley or recessed areas corresponding to the shape of the trenches 202 and the recess depth of the field plates 206 , For example, excess carbon is removed using an etchback and / or CMP process, stopping on the HDP material to form carbon plugs 210 in the hollow or recessed areas of the HDP layer 208 train.

6E shows the semiconductor body 200 after forming grooves 212 in the islands 214 of the semiconductor body 200 between the trenches 202 , An anisotropic etch process is used to selectively remove the HDP material to the carbon material resulting in self-aligned and spaced HDP / carbon structures 216 leads. The self-aligned HDP / carbon structures 216 are spaced apart by an open gap, g ', and may have tapered or non-tapered sidewalls, depending on the etching process used 218 exhibit. An in 6E not shown optional spacer layer may be on the semiconductor body 200 and the HDP / carbon structures 216 before etching the HDP layer 208 are deposited to the open gap, g 'between the HDP / carbon structures 216 continue to narrow, such as. Example hereinbefore with reference to 5B described. For boundary cells can be a resist layer 220 on the HDP layer 208 in the edge region to remove the HDP layer 208 in the edge area. groove 212 then go into the semiconductor body islands 214 between the trenches 202 through the open gaps, g 'between adjacent HDP / carbon structures 216 etched. Optionally, source / body and contact implants may be made after etching the grooves 212 and before filling the grooves 212 respectively.

6F shows the semiconductor body 200 after the grooves 212 with nitride or other material 222 with a different etching selectivity than the HDP material 208 and the carbon material 210 are filled. An etch back and / or CMP process is used to remove the excess grout 222 to remove, taking on the carbon material 210 is stopped.

6G shows the semiconductor body 200 after removing the self-aligned HDP / carbon structures 216 out of the trenches 202 selective to the Nutenfüllmaterial 222 z. B. by O ₂ plasma etching. Any remaining HDP remainder 223 on the side walls of the Nutenfüllmaterials 222 can also be removed, eg. By a wet chemical etch (HF), and a gate oxide 224 becomes along the trench sidewalls 203 in the upper part of the trenches 202 educated. The field oxide 204 and the field plate 206 remain in the lower part of the trenches 202 , The groove filling material 222 also remains after removal of the HDP / carbon structures 216 ,

6H shows the semiconductor body 200 after depositing a gate conductor material 226 such as polysilicon in the trenches 202 and on the semiconductor body 200 (as indicated by the dashed line). An etch back and / or CMP process is used to remove excess gate conductor material, which is a gate conductor 228 in the trenches 202 results. The gate ladder 228 are above the field plates 206 in the trenches 202 arranged and through the field oxide 204 vertically from the field plates 206 spaced and through the gate oxide 224 laterally from the semiconductor body 200 spaced. Subsequent conventional processing steps may be performed, such as deposition of an insulating oxide such as BPSG, CMP or plug-mesa backplate, plug removal, metal filling, source / body implantation, contact implantation, etc. The grooved material 222 can then be removed to source and / or body regions and corresponding contact structures in the semiconductor body 200 to train, z. As described hereinbefore.

Spatially relative terms, such as "below," "below," "lower," "above," "upper," and the like, are used to facilitate the description of positioning one element relative to a second To explain element. These terms are intended to encompass different orientations of the device in addition to those other orientations shown in the figures. Furthermore, terms such as "first / e / e", "second / e / e" and the like are also used to describe various elements, regions, sections, etc., and are also not meant to be limiting. Like terms refer to like elements throughout the description.

The terms "have," "include," "with," "include," and the like, as used herein, are open phrases that indicate the presence of indicated elements or features, but do not preclude additional elements or features. The articles "a / a" and "the / the" should include the plural as well as the singular unless the context clearly indicates otherwise.

Claims (19)

Method for producing contact openings ( 30 . 122 ) in a semiconductor body ( 10 . 100 ), the method comprising: forming a plurality of self-aligned structures on a main surface ( 11 . 106 ) of a semiconductor body, wherein adjacent ones of the self-aligned structures have spaced sidewalls facing each other by forming a plurality of ones from the main surface ( 11 . 106 ) of the semiconductor body ( 10 . 100 ) in the semiconductor body extending trenches ( 12 . 104 ); Forming a first layer ( 15 . 108 ) on the main surface ( 11 . 106 ) and in the trenches ( 12 . 104 ), the first layer ( 15 . 108 ) excluded areas ( 16 ) above the trenches; Forming a second layer ( 20 . 110 ) on the first layer, the second layer ( 20 . 110 ) the excluded areas ( 16 ) of the first layer ( 15 . 108 ) fills; and forming openings ( 30 . 112 ) in the first and second layers ( 15 . 20 . 108 . 110 ) leading to the main surface ( 11 . 106 ) over island regions of the semiconductor body between adjacent trenches ( 12 . 104 ) extend; Forming a spacer layer ( 120 ) on the sidewalls of the self-aligned structures and forming openings ( 30 . 122 ) in the semiconductor body ( 10 . 100 ) between adjacent ones of the self-aligned structures, while the spacer layer (FIG. 120 ) is located on the sidewalls of the self-aligned structures such that each opening has a width and a distance to the side wall of an adjacent trench that corresponds to a thickness of the spacer layer. The method of claim 1, wherein the first layer ( 15 . 108 ) is formed by HDP deposition. Method according to claim 1 or 2, wherein the second layer ( 20 . 110 ) Comprises carbon. Method according to claim 1, wherein the spacer layer ( 120 ) is formed by TEOS deposition. Method according to one of the preceding claims, wherein the spacer layer ( 120 ) Comprises carbon. Method according to one of the preceding claims, wherein the side walls of the self-aligned structures are tapered. Method according to one of the preceding claims, further comprising the thickness of the spacer layer ( 120 ) based on a predetermined width for in the semiconductor body ( 10 . 100 ) between adjacent self-aligned structures. The method of any one of the preceding claims, further comprising: measuring a distance between adjacent ones of the self-aligned structures prior to forming the spacer layer (10) 120 ) and determining the thickness of the spacer layer ( 120 ) based on the measured distance. The method of claim 8, wherein the distance between adjacent ones of the self-aligned structures is measured by scanning electron microscopy. Method according to claim 8 or 9, wherein the semiconductor body ( 10 . 100 ) Is part of a semiconductor wafer and a plurality of distances between adjacent self-aligned structures are measured at various points on the wafer prior to formation of the spacer layer. The method of claim 10, further comprising: calculating an average for the plurality of distance measurements and determining the thickness of the spacer layer ( 120 ) based on the calculated mean. Method according to claim 11, wherein the thickness of the spacer layer ( 120 ) corresponds to the difference between the calculated average and a target value for the distance between adjacent ones of the self-aligned structures. A method for producing self-aligned contact structures on a semiconductor body, the method comprising: forming a plurality of trenches ( 205 ) extending from one main surface ( 201 ) of a semiconductor body ( 200 ) extend into the semiconductor body; Forming a conductive plate ( 206 ) in a lower part of the trenches ( 205 ) and of the semiconductor body ( 200 isolated; Forming a first material ( 208 ) on the main surface ( 201 ) and on the conductive plates ( 206 ) in the trenches ( 205 ), the first material ( 208 ) has recessed areas above the trenches; Filling the recessed areas of the first material ( 208 ) with a second material ( 210 ); Forming openings ( 212 ) in the first material by an etching process selective to the second material, wherein the openings to the major surface extend across island regions of the semiconductor body between adjacent ones of the trenches to form a plurality of spaced self-aligned structures (US Pat. 216 ) with the second material ( 210 ) in the exempted areas of the first material ( 208 ) to train; Forming grooves ( 212 ) in the semiconductor body ( 200 ) between adjacent ones of the self-aligned structures and filling the grooves ( 212 ) and open gaps between adjacent ones of the self-aligned structures ( 216 ) with a material ( 222 ) with a different etching selectivity than the first and second materials. The method of claim 13, wherein the first material ( 208 ) is formed by HDP deposition. A method according to claim 13 or 14, wherein the second material ( 210 ) Comprises carbon. The method of claim 13 to 15, further comprising removing the self-aligned structures ( 216 ) selectively to which the grooves ( 212 ) and the open column filling material ( 222 ). The method of claim 16, further comprising forming gate conductors ( 228 ) in an upper part of the trenches ( 205 ), whereby the gate ladder ( 228 ) of the semiconductor body ( 200 ) and the field plates ( 206 ) are isolated. The method of claim 16, further comprising forming a spacer layer on the sidewalls of the self-aligned structures prior to forming the grooves in the semiconductor body and forming the grooves in the semiconductor body by forming openings in the semiconductor body between adjacent ones of the self-aligned structures Spacer layer is located on the side walls of the self-aligned structures, so that each opening has a width and a distance to the side wall of an adjacent trench, which corresponds to a thickness of the spacer layer. Method according to one of claims 13 to 18, wherein the grooves ( 212 ) and the open-gap material comprises nitride.

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