DE102011079919B4 - A method of fabricating complementary transistors with increased integrity of gate stack by increasing the gap of gate lines - Google Patents

Abstract

A method of fabricating complementary transistors, the method comprising: forming a first active region, a second active region and an isolation region separating the first active region from the second active region, forming a strain-inducing semiconductor alloy selectively in the first active region under cover of the second active region, forming a gate layer stack over the first active region, the second active region and the isolation region, forming a first p-channel gate electrode structure over the first active region and a second n-channel gate electrode structure aligned therewith over the second active region above the isolation region are separated from each other by a lateral distance, wherein the first and second gate electrode structures are fabricated with a gate length of 40 nm or less, forming a resist mask for covering the second active region and the second gate electrode structure and carrying out an additional etching step for removing excess coating material residues of the resist mask in the region of the isolation region, wherein an end region of the gate electrode structure of the n-channel transistor is exposed, determining the degree of exposure of the end region (260e) of the gate electrode structure (260c) of the n-channel transistor. Channel transistor (250c) after creation and etch back of the resist mask (205r) covering the n-channel transistor (250c) and leaving the adjacent p-channel transistor (250a) on a first substrate (201), setting a critical dimension that determines the distance ( 260d) in a transistor width direction (B) of the gate electrode structure (260c) of the n-channel transistor (250c) to a gate electrode structure (260a) of the adjacent p-channel transistor (250a) in consideration of the determined degree of exposure of the end region (260e) End portion (260 e) of the n-channel gate electrode structure (260 c) is retracted such that at otherwise predetermined dimensions of the components involved and the resist mask is covered with the etched-back resist mask (205r), and forming the gate electrode structures (260a, 260c) of the n-channel transistor (250c) and the adjacent p-channel transistor (250a) having the determined critical dimension on a second substrate (201).

Description

In general, the present invention relates to the fabrication of state-of-the-art integrated circuits with advanced transistors that include gate structures with a high-k gate dielectric material.

The manufacture of advanced integrated circuits such as CPUs, memory devices, ASICS (Application Specific Integrated Circuits), and the like requires that a large number of circuit elements be fabricated on a given chip area according to a specified circuit configuration. In very many types of integrated circuits, field effect transistors are an important type of circuit element that essentially determines the performance of integrated circuits. Generally, a variety of process technologies are currently being used to fabricate field effect transistors, with CMOS technology being one of the most promising approaches for many types of complex circuits due to their good performance in terms of operating speed and / or power consumption and / or cost effectiveness. During the fabrication of complex integrated circuits using CMOS technology, millions of transistors, i. H. n-channel transistors and p-channel transistors, fabricated on a substrate having a crystalline semiconductor layer. Regardless of whether an n-channel transistor or a p-channel transistor is considered, a field effect transistor includes pn junctions defined by an interface of heavily doped regions, referred to as drain and source regions, and a lightly doped or undoped one Area, are formed, such as a channel region, which is adjacent to the heavily doped areas. In a field effect transistor, the conductivity of the channel region, i. H. the forward current of the conductive channel is controlled by a gate electrode disposed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region in the construction of a conductive channel due to the application of a suitable control voltage to the gate electrode depends u. a. from the mobility of the charge carriers in the channel region.

The steady reduction in critical dimensions of transistors has resulted in a gate length of field effect transistors of 50 nm and significantly less, providing complex semiconductor devices with improved performance and increased packing density. The increase in the electrical performance of the transistors is associated with the reduction in channel length, resulting in increased forward current and increased switching speed of the field effect transistors. On the other hand, the reduction of the channel length has a number of problems with regard to the channel controllability and the static leakage currents of these transistors. It is well known that very short channel field effect transistors require increased capacitive coupling between the gate electrode structure and the channel region to achieve the desired controllability of static and dynamic current flow. Typically, the capacitive coupling is increased by decreasing the thickness of the gate dielectric material typically fabricated based on a silica base material, possibly in combination with nitrogen, due to the favorable properties of a silicon / silicon dioxide interface. When establishing a channel length of the order of magnitude mentioned above, the thickness of the silicon dioxide-based gate dielectric material reaches values of 1.5 nm and less, which in turn leads to pronounced leakage currents due to a direct tunneling of the carriers through the very thin gate dielectric material. Since the exponential increase in leakage currents, while further reducing the thickness of silicon dioxide-based gate dielectric materials, is not compatible with thermal design performance requirements, other mechanisms have been developed to improve transistor performance and / or reduce overall transistor dimensions.

For example, by creating some strain in the channel region of silicon-based transistor elements, the charge carrier mobility and thus the overall conductivity of the channel can be increased. For a silicon material with a standard crystal configuration, ie one ( 100 ) Surface orientation and an orientation of the channel longitudinal direction along a < 110 > equivalent direction, a tensile strain in the current flow direction can improve the conductivity of the electrons, thereby improving the transistor performance of n-channel transistors. On the other hand, creating a compressive strain in the current flow direction increases the mobility of holes and thus provides better conductivity of p-channel transistors. Thus, a variety of deformation-inducing mechanisms have been developed in the past, which in themselves require a very complex manufacturing sequence to set up these techniques. With further size reduction of the devices, "internal" strain-inducing sources, such as an embedded strain-inducing semiconductor material, are very efficient strain-inducing mechanisms. For example, the incorporation of a compressive strain-inducing silicon / germanium alloy into the drain and source regions of p-channel transistors is often used to improve the performance of these To improve transistors. For this purpose, in an early manufacturing stage, recesses are made in the active area laterally adjacent to the gate electrode structure of the p-channel transistor, while the n-channel transistors are covered by a spacer layer. These recesses are subsequently filled with the silicon / germanium alloy based on selective epitaxial growth techniques. During the etch process for making the recesses and during the subsequent epitaxial growth process, the gate electrode of the p-channel transistor must be included to avoid undesirably sensitive gate electrode structure materials such as silicon-based electrode material, the process environment for making the recesses, and selectively growing the silicon / Germanium alloy. Thereafter, the gate electrode structures are exposed and further processing is continued by making drain and source regions according to a suitable process strategy.

Basically, the deformation-inducing mechanism described above is a very efficient concept for improving the transistor performance of p-channel transistors, but the efficiency of the ultimate deformation in the channel region of the transistor is significantly different from the internal strain level of the semiconductor alloy and the lateral distance of that material from the channel region depends. Typically, the material composition of the strain-inducing semiconductor alloy is limited by the currently available complex selective epitaxial deposition recipes, which in the case of a silicon / germanium alloy currently does not permit germanium concentrations greater than about 30 atomic percent. Thus, further increasing the overall strain in the channel region requires a reduction in the lateral spacing of the silicon-germanium alloy from the channel region so that protective spacer structures having a smaller width are to be provided.

In addition to providing strain-inducing mechanisms in complex field effect transistors, complex gate electrode materials have also been proposed to overcome the limitations of conventional silicon dioxide / polysilicon based gate electrode structures. For this, the conventional silicon dioxide-based dielectric material is at least partially replaced by a so-called high-k dielectric material, i. H. by a dielectric material having a dielectric constant of 10.0 or higher, resulting in a desired high capacitance between the gate electrode and the channel region, while still maintaining a certain minimum physical thickness to maintain the resulting leakage currents at an acceptable level. For this purpose, many dielectric materials, such as hafnium oxide based materials, zirconia, alumina and the like, are available and can be used in complex gate electrode structures. Further, the polysilicon material is also replaced at least in the vicinity of the gate dielectric material, since polysilicon typically exhibits charge carrier depletion in the vicinity of the gate dielectric material, resulting in a reduction in effective capacitance. Further, in complex high-k gate dielectric materials, the work function of standard polysilicon materials produced by appropriate doping is no longer sufficient to provide the required electronic properties of the gate electrode material, i. h., To achieve a desired threshold voltage of the considered transistors. For this reason, special work function adjusting metals, such as aluminum, lanthanum, and the like are typically incorporated into the dielectric material and / or a suitable electrode material to achieve a desired work function and to increase the conductivity of the gate electrode material at least in the vicinity of the gate dielectric material.

Therefore, many complex process strategies have been developed, and in some promising approaches, the complex gate materials, such as a large ε dielectric material and a metal-containing electrode material, possibly containing a work function metal-containing metal species, are provided in conjunction with a polysilicon material in an early manufacturing stage maintain high level of compatibility with conventional process strategies for the fabrication of complex field effect transistors. However, it has been found that reliable confinement of the sensitive material system including the high-k dielectric material and the metal-containing electrode material must be ensured to allow for shift of the threshold voltage or other instabilities of the large-metal complex metal gate electrodes during further processing avoid.

In an attempt to further improve the device performance of complex field-effect transistors, it has been proposed to combine complex high-k gate metal electrode structures with a strain-inducing mechanism, such as incorporating a strain-inducing semiconductor alloy into the active regions of the transistors. In this case, the encapsulation of the gate electrode structure of the transistor must be embedded Deformation-inducing semiconductor alloy requires to be set up on the basis of mutually conflicting requirements. On the one hand, the inclusion of the gate electrode structure must ensure the integrity of the sensitive material system, for example, before, during, and after incorporation of the strain-inducing semiconductor material, and on the other hand, a smaller thickness of any protective spacer elements, such as silicon nitride-based materials, is desirable in terms of improving the effectiveness of the strain inducing mechanism , As a result, a compromise is typically made between the thickness of the spacer elements and the gain in complex transistor performance.

In general, the above strategies, ie, the incorporation of strain-inducing semiconductor material into the p-channel transistors and the provision of high-k dielectric gate electrode structures, are very promising approaches to improving the performance of the resulting transistors. With a further reduction of the feature sizes, ie the gate length of the transistors, however, it can be seen that an increased failure rate is observed, so that the higher performance of the individual transistors is significantly impaired by the lower yield in the mass production. Related to the 1a to 1d Now, a typical process flow will be described in which transistors with complex gate electrode structures and built-in strain-inducing silicon / germanium material are fabricated into p-channel transistors to show potential failure mechanisms.

1a schematically shows a plan view of a semiconductor device 100 in a certain manufacturing phase, in which a gate layer stack 160s over corresponding active areas 102 . 102b . 102c is trained. It should be noted that in the presentation of the 1a the active areas 102 . 102b . 102c are not actually visible, as these are from the gate layer stack 160s are covered. The active areas 102b . 102c For example, active areas over which n-channel transistors are to be made are the active area 102 represents the range of one or more p-channel transistors. In general, an active region is to be understood as a semiconductor region in and over which one or more transistors are to be produced. The active areas 102 . 102b and 102c are typically laterally separated by an isolation region, such as a shallow trench isolation region, as shown in FIG 1a not shown. Further, in the gate layer stack 160s containing the single materials for the gate electrode structures, a hardmask layer 164 provided, which is already structured to a certain extent, so as to substantially fix the length of the gate electrode structures to be generated. In the illustration in 1a for example, the corresponding hard mask layer 164 in oblong stripes with a width 160l divided substantially corresponding to the length of the gate electrode structures to be generated. In the strategy described is based on the already uniquely structured layers 164 another structuring process is performed to a distance 160d corresponding gate electrode structures in a transistor width direction, which is indicated by B set. For this purpose, for example, a suitable lithography and etching strategy is used, in which a suitable mask (not shown) is structured in such a way that then the strips 164 can be divided in the way as indicated by the dashed line and the distance 160d is specified. In this way, the layers become 164 are provided as suitable hard masks, which have substantially the length and the width of the gate electrode structures to be generated, in order to cover the underlying remaining materials of the gate layer stack 160s to structure in a further etching sequence in a suitable manner.

1b schematically shows a plan view of the device 100 in a more advanced manufacturing stage, in which the structuring process described above was performed in order to use the hard mask layer 164 provide with their final shape, so that on the one hand the length of the gate electrodes and also the distance 160d through the hard mask layers 164 is predetermined. Based on the hard mask 164 For example, having one or more suitable material layers, for example, silicon dioxide in conjunction with silicon nitride, and the like, which may also include two or more layers, then a complex patterning process is carried out in which the remaining layers of the gate layer stack 160s be etched. For example, a semiconductor material, such as amorphous silicon, polysilicon, and the like are etched, often followed by a metal-containing electrode material, whereupon the gate dielectric is etched, which in demanding applications, as previously explained, contains a high-k dielectric material. In this way, the dimensions of the hard mask 164 essentially on the underlying layers of the gate layer stack 160s so as to determine the lateral dimensions of the resulting gate electrode structures.

1c schematically shows a cross-sectional view along the section line Ic 1b , In the illustration shown is the component 100 in a more advanced manufacturing phase shown. As shown, the device comprises 100 a substrate 101 , such as a silicon material, on which a semiconductor layer 102 , typically a silicon layer, is formed. In the semiconductor layer 102 are the active areas 102 . 102b formed as in the previous plan views in 1a and 1b is shown. In the active area 102 is a p-channel transistor 150a This is still to be completed while in and above the active area 102b an n-channel transistor 150b is made. In the example shown is in the active area 102 Further, a semiconductor material 104 below a gate electrode structure 160a is provided, which has a suitable composition, for example in the form of a silicon / germanium alloy material, in order to allow suitable adaptation of the conduction band edge or the Fermi energy, in order to cooperate with the gate electrode structure 160a a desired threshold voltage for the transistor 150a whereas a corresponding shift in the work function of a gate electrode structure 160b of the transistor 150b is not required. Furthermore, in the active area 102 a strain-inducing silicon / germanium material 151 laterally adjacent to the gate electrode structure 160a provided so that in the area of a canal area 152 a desired high compressive deformation is caused, in turn, the mobility of the holes in the channel region 152 clearly increased.

Frequently in the n-channel transistor 150b corresponding embedded semiconductor materials are not provided, since other powerful deformation-inducing mechanisms are available for n-channel transistors. In the manufacturing stage shown, the gate electrode structures contain 160a . 160b a gate dielectric material 162 , which is typically provided as a high-k material, so that at a given thickness, the corresponding gate leakage current is kept at an acceptable level, yet a high capacitive coupling of the gate electrode to the channel region 152 is reached. Frequently, a very thin conventional dielectric, such as silicon oxynitride, is provided in conjunction with a high-k dielectric material, such as hafnium oxide, and the like, also typically including a metal-containing electrode material (not shown) in the layer stack 163 is provided in order to set on the one hand a suitable work function and on the other hand to obtain an improved conductivity, wherein the metal-containing electrode material serves as a conductive cover layer for the underlying dielectric. Often, materials such as titanium nitride, tantalum nitride, and the like are provided for this purpose, and other types of metal, such as aluminum, lanthanum, and the like, are incorporated to obtain a suitable work function for each conductivity type. Corresponding metals for the adjustment of a suitable work function can also be diffused into the dielectric material, depending on the process strategy used.

So it should be noted that the layer or the layer stack 162 a dielectric material having a suitable thickness and a dielectric constant which is significantly higher than the dielectric constant of conventional dielectrics, such as silicon dioxide and silicon nitride, whereby a conductive material, such as titanium nitride, and the like may be integrated to give the overall desired electronic properties for the gate electrode structures 160a . 160b to obtain. It is often a different structure of the layers 162 for the gate electrode structures 160a . 160b provided to the different conductivity type of the transistors 150a . 150b Take into account. Further, typically is another electrode material 163 , provided in the form of silicon, to which the layer 164 which serves as a dielectric overcoat or overcoat system in this manufacturing stage and which was used as an efficient hardmask layer in the previous manufacturing stage, as previously explained. In the illustrated manufacturing phase are also sidewall spacers 161 on sidewalls of the electrode material 163 and in particular the sensitive material system 162 provided, wherein in some manufacturing strategies, the spacers 161 both as a protective material, in particular for the layer 162 serve, on the other hand, as a spacer for adjusting the lateral distance of the material 151 to a canal area 152 be used. On the other hand, a spacer layer 161s over the active area 102b and the gate electrode structure 160b Provided as an efficient hard mask during installation of the material 151 selectively in the active area 102 serves.

The semiconductor device 100 as it is in 1c can be made on the basis of the following processes. The active areas, such as the areas 102 . 102b are determined in their lateral size and shape by the isolation area 103 This is done by well-established process strategies, such as using lithography, etching, deposition, and planarization techniques, to create suitable trenches in the layer 102 and then to fill these trenches with a suitable insulating material. Before making the insulation structure 103 or after that becomes the basic conductivity of the active areas 102 . 102b adjusted by about appropriate Implantation processes are applied with associated masking steps. When the semiconductor material 104 to adjust the threshold voltage, this may be selective in the active area 102 For example, a hard mask, such as an oxide layer, may be formed to form the active region 102b After which a selective epitaxial growth process can be performed to the material 104 grow up. During this process sequence, a pronounced material erosion typically occurs in the isolation area 103 near the active area 102 like this through 103r is specified. This local material erosion in the isolation area 103 is done mainly by the selective removal of the hard mask and the cleaning measures required for the subsequent epitaxial growth process.

After removing the appropriate hardmask on the area 102b the gate layer stack is applied, such as the stack 160s as he is in the 1a and 1b described above, wherein before still a suitable structuring of corresponding layers for the layer system 162 can be performed, for example, if different materials are to be provided above the respective active areas. That is, suitable metal layers may selectively over the respective areas 102 . 102b be applied, so that in cooperation with a previously prepared dielectric the desired properties for the layer system 162 can be achieved. Then the material becomes 163 in connection with the material 164 , which, as explained above, also have several layers, deposited, whereupon a structuring of the layer system 164 as previously explained, so as to allow substantially the gate length and the structuring in the transistor width direction, as previously with reference to the 1a and 1b is described. After structuring the hard mask material 164 a structuring process is carried out in order to structure the further material layers so that finally the gate electrode structures 160a . 160b with the desired lateral dimensions, with about one gate length often being 50 nm and less. Then the spacer layer becomes 161s this is accomplished by appropriate deposition techniques to apply a dense and resistive material, such as silicon nitride, in a highly conformal manner. For this purpose, suitable multi-layer deposition methods and the like are available. The layer 161s is then using a mask 109 that the p-channel tranisistor 150a and part of the isolation structure 103 leaves open, structured, leaving the spacer 161 is formed while the transistor 150b continue from the layer 161s is covered. As previously explained, the spacer becomes 161 thus in many strategies for encapsulating the sensitive materials in the layer 162 used, and further defines the lateral spacing of recesses, for example, in the presence of the mask 109 in the active area 102 be produced by performing suitable etching. For example, immediately after the patterning of the spacer layer 161s over the active area 102 a corresponding suitable etching sequence is carried out to be in the material of the area 102 to etch while the topcoat 164 and the spacers 161 for the integrity of the gate electrode structure 160a to care. Due to the pronounced surface topography in the isolation area 103 However, it is often observed that the resist mask used to structure the layer 161s and for creating the recesses in the active area 102 serves only with a different lateral dimension at the foot of the mask compared to the top of the mask can be applied, so that a further mask patterning step is required, but which may lead to end portions of gate electrode structures over the isolation region 103 are exposed, as will be described below generally for corresponding masking steps using a resist mask.

Then, proper cleaning processes are carried out to finally get the material 151 in the form of silicon / germanium, for example, by growing a selective epitaxial growth process in the previously created recesses. During this selective epitaxial growth process, the layer serves 161s as an efficient mask, which allows deposition of semiconductor material on or over the transistor 150b prevented.

It should be noted, that is due to the installation of the material 104 in particular the exposed area of the insulation structure 103 So the area of the transistor 150a surrounds, experiences a significantly different process history than the transistor 150b surrounding area of the insulation structure 103 , so that in particular a pronounced topography is caused, which in turn however has a great influence on the further method steps, in particular already during the production of the material 151 , as explained below.

Thereafter, processing is typically continued by placing the spacer layer 161s also to spacers in the gate electrode structure 160b is structured, so that then further processing can be continued by introducing dopants and other spacer structures are prepared to such as the desired lateral and vertical dopant profile for the transistors 150a . 150b to create.

1d schematically shows a cross-sectional view along the section line Id in 1b in a manufacturing phase in which the gate electrode structures are completely structured. In the illustrated sectional view, for example, the gate electrode structure 160a over the active area 102 formed and extends over a part of the isolation area 103 as well as in the plan view 1b is apparent. Further, the active area is also 102c above which a gate electrode structure is shown 160c is formed, which is part of an n-channel transistor 150c is in and over the active area 102c is trained. The gate electrode structures 160a . 160c own the material system 162 with the high-k dielectric, possibly in conjunction with a metal-containing electrode material, as previously explained, and then the further electrode material 163 connects and where also the cover layer 164 is available. Further, the spacers 161 on the sidewalls of the materials 162 . 163 and 164 educated. As explained above, it is for many other process steps as well as in the selective production of the material 151 in the active area 102 it is necessary to alternately cover the p-channel transistors and n-channel transistors, for example, to introduce suitable dopants, and the like. This will typically be a suitable mask 105 provided based on well-established lithography techniques. Typically, the mask becomes 105 provided in the form of a resist material, which in turn is patterned on the basis of a lithography mask, suitably the gate electrode structure 160c and the active area 102c covering while the transistor 150a is free. The structuring of the mask 105 however, is due to the pronounced surface topography in the isolation area 103 significantly affected, so that in particular at the bottom or at the foot of the gate electrode structure 160c a thicker paint layer accumulates, as by 105f with this paint thickness at the foot of the gate electrode structure 160c can contribute to large process non-uniformities during further processing, so that typically a further patterning process or etching step is required to remove in particular these excess paint residues before further processing. For this purpose, suitable plasma-assisted etching processes based on oxygen are used in the material of the resist mask 105 is removed, resulting in a reduced resist mask 105r but it is observed that at the end region 160e the gate electrode structure 160c too much paint material is removed and thus there is a high probability that in particular the spacer 161 or even the layer 161s (S. 1c ) in the structuring of the spacers 161 at the gate electrode structure 160a and in the production of the recesses for the material 151 in this end area 160e is exposed.

Without wishing to limit the present application to the following explanation, it is nevertheless believed that this increased likelihood of exposure, particularly of the spacers 161 or the layer 161s (S. 1c ) in the end area 160e the gate electrode structure 160c to a greater material erosion of the spacer 161 or the layer 161s contributes. Due to the greater material erosion, however, a significantly higher probability is given that in particular the sensitive material system 162 in the end area 160e is attacked and thus, for example, a high loss of material in the layer system 162 may in turn adversely affect the properties of the gate electrode structure 160c effect.

From the DE 10 2009 015 715 A1 For example, there is known a method of fabricating complementary transistors having a large-gate gate metal stack employing an offset spacer to determine the spacing of the strain-inducing material to preserve the integrity of the gate layer stack.

From the US 2010/0124815 A1 For example, a method of manufacturing a semiconductor device is known in which the opposite ends of the gate electrodes are separated from each other by means of a two-stage etching process using antireflection layers.

In view of the situation described above, it is therefore an object of the present invention to provide means for providing complex transistors with high-k dielectric with gate electrode structures, wherein one or more of the aforementioned problems are to be prevented or alleviated in effect.

According to the present invention, the aforementioned object is achieved by a method having the features according to claim 1.

According to the invention, therefore, the distance between two gate electrode structures over an isolation region is determined on the basis of data which essentially describe the degree of influence on a resist mask used, for example, for covering the n-channel transistor and the associated gate electrode structures. Thus, the lateral dimension of the gate electrode structures in the transistor width direction can be suitably adjusted so that For example, the material erosion of the paint material caused in the patterning of the resist mask is taken into account such that no exposure of the end region of the gate electrode structure of the n-channel transistor takes place. In this way, the risk of material erosion of a protective spacer structure or a material layer is significantly reduced, so that overall the integrity of the sensitive material system in the gate electrode structure is preserved.

In an advantageous embodiment, the gate electrode structures of the n-channel transistors and the p-channel transistors on the first and the second substrate are produced with a high-k gate dielectric. The use of a high-k gate dielectric is particularly advantageous in the context of complex transistors, in particular because it increases performance, while preserving the integrity of the sensitive material system.

In an advantageous embodiment, forming the gate electrode structures includes generating a hard mask by performing a first lithography and etch sequence to adjust the gate length and performing a second lithography and etch sequence to adjust the gate width in the hard mask. That is, according to the invention, a two-stage structuring of a hard mask material can be used, so that, in particular, very efficient, well-established structuring schemes can be used without having to introduce further lithography steps or masking steps.

Overall, the present invention enables manufacturing processes for the production of complex transistors, wherein in particular the pronounced material erosion in the end regions of gate electrode structures in n-channel transistors is taken into account during the production of a resist mask over an isolation region with pronounced topography, by a suitable lateral distance between the gate electrode structures of adjacent n Channel transistors and p-channel transistors is provided, so that the possibly generated pronounced surface topography over the isolation region thus exerts no negative effects in the preparation of corresponding resist masks. Thus, the likelihood of a reduction in production yield due to material erosion in end regions of gate electrode structures can be reduced without requiring additional process steps. In particular, the throughput and the course of other process steps are not adversely affected by the procedure according to the invention.

Further advantageous embodiments will become apparent from the claims, and are pointed out in the following detailed description, given with reference to the accompanying drawings, in which:

1a and 1b schematically show plan views of a semiconductor device,

1c and 1d show corresponding sectional views of the semiconductor device in more advanced manufacturing stages according to conventional strategies,

2a and 2 B schematically show plan views of a semiconductor device according to illustrative embodiments of the present invention and

2c to 2f corresponding sectional views of the semiconductor device in more advanced stages of manufacture according to the present invention show.

Related to the 2a to 2f The present invention will now be described in more detail, wherein also on demand on the 1a to 1d is referenced.

2a schematically shows a plan view of a semiconductor device 200 in which an active area 202a and an active area 202c are shown, over which gate electrode structures from a gate layer stack 260s are to produce. It should be noted that in the illustration in 2a the active areas 202a . 202c are shown as if the gate layer stack 260s would be transparent. Furthermore, in the illustrated manufacturing phase, the gate layer stack 260s already partially structured, so that about a hard mask layer or a layer system 264 already has a suitable dimension in a lateral direction. For example, as shown, one gate length 260l essentially in the hard mask 264 already set while a distance 260d in the perpendicular lateral direction is still set up. That is, the mask layer 264 the gate layer stack 260s is already a strip-shaped structure with a corresponding gate length 260l provided, as previously with respect to the device 100 is explained. Unlike conventional strategies in which, for example, a typical lateral distance 160d for the resulting gate electrode structures between the active areas 202a . 202c to set up, as previously related to the 1a to 1b is explained, according to the invention, this distance as a greater distance 260d set, which is dimensioned so that in a subsequent production of a resist mask unwanted exposure of end portions the resulting gate electrode structures is substantially avoided.

For this purpose, for example, on the basis of given design dimensions, such as, for example, generally the device 100 match that previously with reference to the 1a to 1d is described, in structuring the degree of exposure of the resist mask 105 certainly. Ie. For example, it becomes the difference in the lateral dimension of the resist masks 105 and 105r (please refer 1d ), so that it can be determined which degree of "retraction" of the gate electrode structure 160c (please refer 1d ) with otherwise predetermined dimensions of the components involved and the resist mask 105 is required, in particular their end 160e through the mask 105r to keep covered. Corresponding measurements can be carried out, for example, efficiently on the basis of electron microscopic measurements, so that in particular the distance 260d compared to the original distance 160d can be determined in a suitable manner, so that in the further processing, an exposure of the end region of the resulting gate electrode structures is avoided. On the other hand, the further dimensions of all components, such as the active areas, and the like can be maintained, in particular, the gate length 260l the gate length of the device described above 100 can match if otherwise the dimensions and characteristics of the device 100 the structure of the device to be produced 200 correspond. That is, based on measurement data obtained from a first substrate, ie the device 100 can thus be suitably adapted to the distance 260d done so that in the manufacture of the device 200 on other other substrates for otherwise similar components and process methods and a reduced degree of material erosion in sensitive materials of the gate electrode structures.

2 B schematically shows a plan view of the device 200 for the sake of simplicity, only a single mask layer 264 shown with the remaining gate layer stack 260s over the active area 202a and the active area 202c and to be patterned over the intervening isolation area (not shown).

2c schematically shows a cross-sectional view of the device 200 according to the section line IIc 2 B , As shown, the device comprises 200 a substrate 201 over which a semiconductor layer 202 is formed, in turn, through an isolation area 203 is divided into active areas, wherein in the sectional view of 2c only the active area 202a is visible. In the embodiment shown is in the active area 202a a threshold voltage adjusting semiconductor alloy 204 , such as in the form of a silicon / germanium material, so as to provide suitable electronic properties of a transistor located in and over the active region 202a is to produce. As previously related to the device 100 explains it, the isolation area 203 in the vicinity of the active area 202a have a pronounced material erosion (not shown), which can significantly influence the further processing, as also explained above. Further, the gate layer stack 260s via semiconductor layer 202 applied and includes the layer system 262 which, in one illustrative embodiment, includes at least one high-k dielectric material, as previously described, with particular provision for a metal-containing electrode material, such as titanium nitride, tantalum nitride, and the like. Further, another electrode material 263 , in the form of polysilicon, and the like, in the layer stack 260s contain. In this manufacturing phase, as already in the 2a and 2 B is shown, the hard mask 264 structured in a lateral direction, the hard mask 264 may have two or more layers of material, which are not shown for simplicity.

The manufacture of the semiconductor device 200 as it is in the 2a to 2c can be done on the basis of process strategies, as previously with respect to the semiconductor device 100 are described. That is, the active regions are formed by appropriately generating the isolation region 203 determined laterally in size and shape, whereupon the conductivity can be adjusted by means of implantation processes in connection with suitable masking steps. For example, the active area becomes 202a produced as an active region of a p-channel transistor. Then, if necessary, the material layer 204 applied, as previously related to the device 100 is explained, resulting in a different process history for the part of the isolation area 203 can lead the active area 202a surrounds. The shift system 262 is fabricated by suitable deposition processes and, if necessary, by patterning processes and annealing processes to have the appropriate dielectric and conductive properties over the respective active regions to provide, in particular, a desired threshold voltage, capacitive coupling and leakage current behavior. The layer 263 is applied by well-established deposition techniques, which is the deposition of the layer system 264 followed, the following by means of a lithography and etching sequence 206 is structured so as to set a suitable gate length, as previously explained. Ie., the lithography and etching sequence 206 involves a complex lithography process for applying a resist mask and its structuring, both with subsequent etching, for example using suitable trim etch processes, so that ultimately the desired lateral dimension of the mask 264 is set. Then the device can 200 for a further structuring of the hard mask 264 Be prepared by adding another mask material 207 , such as a paint material, a polymer material, or other dielectric material is applied.

2d schematically shows a sectional view along the section line IId in 2 B of the component 200 in the production phase described above. As shown, the gate layer stack is with the materials 262 . 263 . 264 as well as the additional mask 207 over the active areas 202a . 202c , and the isolation area 203 applied.

2e schematically shows the device 200 in a more advanced manufacturing stage, in which a further lithography and etching sequence 208 running, so first the mask 207 is structured to make it an opening 207a which, in turn, serves to form the underlying hardmask 264 to structure in the other lateral direction, thus allowing the distance 260d is established, as previously with respect to 2a is described. During the lithography and etching sequence 208 becomes the structuring of the hardmask 264 so executed that the distance 260d which ensures that exposing a gate electrode structure over the isolation region 203 is essentially avoided in a later manufacturing phase. For this purpose, the lithography mask (not shown) may be used during the sequence 208 is applied, suitably prepared so that already here a greater distance in the opening 207a while maintaining other lateral dimensions. In other embodiments, the properties of the corresponding lithography process and / or etching process become in the sequence 208 be adjusted so that, for example, the opening 207a greater than conventional strategies, so after transferring the opening 207a in the hard mask 264 the desired larger distance 260d is obtained. For example, the exposure parameters may be in the sequence 208 and / or other process parameters in the lithographic process, such as curing of the paint, etc., are adjusted accordingly, or it can also generally larger dimensions for the opening 207a are used, which is then reduced again in a suitable manner by corresponding spacers (not shown) in the opening 207a be generated, but in turn be set so that finally the desired greater distance 260d is produced. After structuring the hard mask 264 can the mask 207 this can be done by well-established measures. Based on the textured hard mask 264 , in particular in the transistor width direction B, the larger lateral dimension 260d owns, then the rest of the gate layer stack 260s ie the layers 263 . 262 be structured so that in particular over the isolation area 203 which may locally have a pronounced surface topography, as previously explained, between both active areas 202a . 202c gives a greater distance for the resulting gate electrode structures.

2f schematically shows the device 200 in a further advanced manufacturing phase, which here too the cross-sectional view is shown, the cut line IId from 2 B equivalent. As shown, is a p-channel transistor 250a over the active area 202a formed and includes a gate electrode structure 260a which in turn is the shift system 262 with the material of high ε, the electrode material 263 and, in the production phase shown, the hard mask 264 has in the form of a dielectric cover layer. Similarly, an n-channel transistor 250c in and over the active area 202c formed and includes a gate electrode structure 260c which in turn is the shift system 262 with the appropriate electronic properties, the electrode material 263 and the hard mask 264 having. Furthermore, sidewall spacers 261 on the sidewalls of the gate electrode structures 260a . 260c educated. It should be noted that at the gate electrode structure 260C It is also possible for an unstructured spacer layer to be formed which, in the production of a deformation-inducing semiconductor material, is selectively formed in the active region 202a especially in the active area 202a is used as a mask, as previously in connection with the device 100 is described. In other embodiments, embedded strain-inducing semiconductor material is already in the active region 202a formed, as for example, previously with respect to the transistor 150a in the form of the material 151 is described. In this way, a desired compressive deformation in a channel region 252 of the transistor 250a be generated, as also described above.

The transistors 250a . 250c can be made on the basis of process techniques, as previously described. That is, after the patterning of the gate electrode structures 260a . 260c becomes the deformation-inducing semiconductor material (not shown) in the active region 202a incorporated, as before with respect to the material 151 is explained, so that in this regard, the transistors 250a and 150a have essentially the same structure. As also explained above, in particular due to the unequal process history for the transistors 250a . 250c a correspondingly pronounced topography over the isolation area 203 which has pronounced effects in the conventional strategy, as previously explained. However, according to the present invention, the lateral distance is 260d adjusted so that when creating a resist mask 205 that the transistor 250c and the associated gate electrode structure 260c should cover a corresponding accumulation of material at the bottom of the gate electrode structure does not adversely affect the further processing. That is, the resist mask 205 can be applied and patterned, as is conventionally the case, and as previously described with respect to the device 100 is explained. To remove the excess paint material at the bottom of the gate electrode structure 260c Therefore, a further etching process is carried out so that, overall, the reduced resist mask 205r is generated, but this still reliable the end 260e the gate electrode structure 260c covers, and thus the spacer 261 or the corresponding spacer layer, if the spacers 261 at the gate electrode structure 260c not yet textured, covered, so that no unwanted material erosion on the spacer 261 or the associated material layer takes place. D. h., When using appropriate resist masks for mutual coverage of the transistors 250a . 250c finds a substantially "symmetrical" or balanced influence on the spacers 261 through reactive etching atmospheres, so that the spacer structure 261 the gate electrode structure 260c the integrity of the sensitive gate materials can be preserved in the same reliable manner as the spacer structure 261 the gate electrode structure 260a as well as the reduced mask 205r reliable the end area 260e covered.

Thus, the present invention provides fabrication techniques in which excessive material erosion in spacer structures, particularly gate electrode structures, of n-channel transistors is avoided by increasing the lateral spacing in the transistor width direction of mutually aligned gate electrode structures of a p-channel transistor and an n-channel transistor for otherwise equal lateral dimensions. In this way it is ensured that, in particular after the incorporation of a semiconductor alloy for selective adjustment of the threshold voltage of a p-channel transistor in the further generation of a resist mask for covering the n-channel transistor and the end region is not exposed over an isolation area with locally pronounced surface topography, so that the integrity of sensitive gate materials of the gate electrode structure can be improved in n-channel transistors such as the incorporation of a deformation-inducing semiconductor material in the active region of the p-channel transistors.

Claims (4)

A method of fabricating complementary transistors, the method comprising: forming a first active region, a second active region and an isolation region separating the first active region from the second active region, forming a strain-inducing semiconductor alloy selectively in the first active region under cover of the second active region, forming a gate layer stack over the first active region, the second active region and the isolation region, forming a first p-channel gate electrode structure over the first active region and a second n-channel gate electrode structure aligned therewith over the second active region above the isolation region are separated from each other by a lateral distance, wherein the first and second gate electrode structures are fabricated with a gate length of 40 nm or less, forming a resist mask for covering the second active region and the second gate electrode structure and performing an additional etching step for removing excess paint material residues of the resist mask in the region of the isolation region, wherein an end region of the gate electrode structure of the n-channel transistor is exposed, determining the degree of exposure of the end region (FIG. 260e ) of the gate electrode structure ( 260c ) of the n-channel transistor ( 250c ) after generation and etching back of the resist mask ( 205r ), the n-channel transistor ( 250c ) and the adjacent p-channel transistor ( 250a ) on a first substrate ( 201 ), setting a critical dimension that determines the distance ( 260d ) in a transistor width direction (B) of the gate electrode structure (FIG. 260c ) of the n-channel transistor ( 250c ) to a gate electrode structure ( 260a ) of the adjacent p-channel transistor ( 250a ), taking into account the specific degree of exposure of the end region ( 260e ), so that an end region ( 260e ) of the n-channel gate electrode structure ( 260c ) is withdrawn in such a way that with otherwise predetermined dimensions of the components involved as well as the resist mask with the back-etched resist mask ( 205r ), and forming the gate electrode structures ( 260a . 260c ) of the n-channel transistor ( 250c ) and the adjacent p-channel transistor ( 250a ) with the determined critical dimension on a second substrate ( 201 ). The method of claim 1, wherein the gate electrode structures of the n-channel transistors and the p-channel transistors on the first and second substrates are fabricated with a high-k gate dielectric. Method according to one of claims 1 or 2, wherein the etching back of the resist mask is carried out with a plasma-assisted etching process based on oxygen. The method of claim 1, wherein forming the gate electrode structures comprises: generating a hard mask by performing a first lithography and etch sequence to adjust the gate length and performing a second lithography and etch sequence to adjust the gate width in the hard mask.

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