DE102019111079A1 - CMOS-compatible isolation leak enhancement for gallium nitride transistors - Google Patents

Abstract

An integrated circuit structure includes a silicon substrate and a III-nitride (III-N) substrate over the silicon substrate. A first III-N transistor and a second III-N transistor are on the III-N substrate. An insulator structure is formed in the III-N substrate between the first III-N transistor and the second III-N, the insulator structure comprising one of: a shallow trench filled with an oxide, nitride, or low-K dielectric is; or a first gap adjacent to the first III-N transistor and a second gap adjacent to the second III-N transistor.

Description

TECHNICAL AREA

Embodiments of the disclosure are in the field of integrated circuit structures, and more particularly, CMOS-compatible isolation leakage enhancements in gallium nitride (GaN) transistors.

BACKGROUND

Systems on a chip (SOC) have been implemented in a number of capacities over the last decades. SOC solutions offer the benefit of scaling, which can not be achieved by integrating board-level components. While analog and digital circuits have long been integrated on a same substrate to provide a form of SOC that provides mixed signal capabilities, SOC solutions remain for mobile computing platforms such as mobile computing platforms. Smartphones and tablets, elusive because these devices typically include components that operate with two or more of high voltage, high power and high frequency. Thus, conventional mobile computing platforms typically use Group III-V compound semiconductors, such as GaAs heterojunction bipolar transistors (HBTs), to produce sufficient power gain at GHz carrier frequencies, and laterally diffused silicon MOS (LDMOS) devices diffused silicon MOS) technology to manage voltage conversion and power distribution (battery voltage regulation including up and / or down voltage conversion, etc.). Conventional silicon field effect transistors implementing CMOS technology are then a third device technology used for logic and control functions within a mobile computing platform.

The majority of transistor technologies used in a mobile computing platform limit the scalability of the device as a whole, and therefore is an obstacle to greater functionality, higher levels of integration, lower cost, and smaller form factors, etc. While one SOC solution for the mobile computing space, the two or three Therefore, an obstruction to an SOC solution is the lack of scalable transistor technology that has both a sufficient speed (ie, sufficiently high gain cutoff frequency F _t ) and a sufficiently high breakdown voltage (BV ) having.

A promising transistor technology is based on Group III nitrides (III-N). However, this transistor technology has fundamental difficulties in scaling to feature sizes (e.g., gate length) of less than 100 nm, where the parasitic capacitance between adjacent III-N transistors will be difficult to control due to their proximity to each other. Previous university research techniques isolate adjacent III-N transistors only using an air-filled space, with no material deliberately being deposited between adjacent devices. However, materials between adjacent transistors are needed to make complex integrated circuits in which a flat surface is desired between each subsequent layer.

list of figures

• The 1A and 1B 12 are cross-sectional views of an integrated circuit structure including a pair of adjacent III-N transistors according to one embodiment.
• The 2A and 2 B 12 are cross-sectional views of an integrated circuit structure including a pair of adjacent III-N transistors having an improved insulator structure according to the first embodiment.
• 3 Figure 11 is a graph illustrating the improvement in leakage between a structure comprising a trench filled with standard materials.
• 4 FIG. 15 is a cross-sectional view of an integrated circuit structure including a pair of adjacent III-N transistors having an improved insulator structure according to the second embodiment. FIG.
• The 5A-5G 15 are diagrams illustrating cross-sectional views showing the fabrication of a pair of III-N transistors with a shallow trench isolation structure according to the first embodiment.
• The 6A-6F 15 are diagrams illustrating cross-sectional views showing the fabrication of a pair of III-N transistors separated by an isolation structure including at least two gaps in the III-N substrate and the dielectric material comprising the two transistors according to the second Embodiment separates.
• The 7A and 7B FIGs. 12 are plan views of a wafer and die including one or more III-N transistors with CMOS-compatible isolation structures in accordance with one or more embodiments disclosed herein.
• 8th Fig. 12 is a cross-sectional side view of an integrated circuit (IC; Integrated circuit) device that may include one or more III-N transistors with CMOS-compatible isolation structures, according to one or more embodiments disclosed herein.
• 9 illustrates a computing device according to an implementation of the disclosure.

DESCRIPTION OF THE EMBODIMENTS

CMOS-compatible isolation leakage enhancements for gallium nitride (GaN) transistors are described. In the following description, numerous specific details are set forth, such as specific material and tooling systems, to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to those skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as simple or dual damascene processing, are not described in detail so as not to unnecessarily obscure the embodiments of the present disclosure. Furthermore, it is believed that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale. In some cases, various operations are again described as multiple discrete operations, in a manner most helpful to understanding the present disclosure, however, the order of the description should not be construed to imply that these operations are necessarily of order are dependent. In particular, these operations do not have to be performed in the given order.

Certain terminology may also be used in the following description solely for purposes of reference and is not intended to be limiting. For example, terms such as "upper," "lower," and "above," "below," "below," and "above" refer to directions in the drawings to which reference is made. Terms such as "front," "back," "back," and "side" clearly describe the orientation and / or position of portions of the component within a consistent but arbitrary frame of reference, with reference to the text and associated drawings that describe the discussed component. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar meaning.

One or more of the embodiments described herein are directed to structures and architectures for fabricating III-N transistors such as gallium nitride (GaN) transistors with improved isolation leakage in a manner that is CMOS compatible. Embodiments may include or refer to one or more of III-V transistors, GaN transistors, isolation structures, shallow trench, air gap and system-on-chip (SoC) technologies, and RF filters. One or more embodiments may be implemented to implement high performance backend transistors to potentially increase the monolithic integration of backend logic plus memory in SoCs of future technology nodes.

To put this in context, the 1A and 1B Cross-sectional views of an integrated circuit structure comprising a pair of adjacent III-N transistors according to an embodiment. In an embodiment, a base includes the integrated circuit structure 100 a silicon substrate 102 and a III-nitride (III-N) substrate 104 over the silicon substrate 102 , A pair of III-N transistors, such as GaN transistors 106 , can each have source and drain (S / D) regions 108 , a polarization layer 110 between the S / D regions 108 and a gate electrode 112 over the polarization layer 110 include. In one embodiment, spacers 114 on both sides of the gate electrode 112 be arranged. Metallization or contacts 116 can on the respective S / D regions 108 be formed.

As in 1A shown as the GaN transistors 106 scaled to feature sizes (eg, gate length) of less than 100 nm and only by a dielectric material 118 parasitic capacitance (I _leak ) between the adjacent GaN transistors 106 due to their proximity, which can be difficult to control, induced.

1B shows another embodiment of the integrated circuit structure 101 containing the dielectric material 118 from 1A through a room filled with air 120 replaced to adjacent GaN transistors 106 isolate with no other material intentionally being deposited between the adjacent devices. However, this does not seem to be a viable solution because to fabricate vertically complex integrated circuits, a flat surface of each layer is required to fabricate each subsequent layer. The rooms 120 between the GaN transistors 106 create holes in the device layer that prevent the device layer from having a flat surface.

In accordance with one or more embodiments described herein, III-N transistors having CMOS-compatible isolation structures are described. The embodiments described herein may include isolation structures between III-N transistors that effectively reduce the parasitic capacitance between the transistors. In one embodiment described herein, the insulator structures are partially disposed in the III-N substrate and in a dielectric between the adjacent III-N transistors. The insulator structures are formed according to two embodiments. In one embodiment, the insulator structure comprises a shallow trench filled with an oxide, nitride, or low-K dielectric, or optionally a bilayer stack comprising the oxide, nitride or low-K dielectric, and a high-K liner includes. In a second embodiment, the insulator structure includes at least two gaps in the III-N substrate and the dielectric material, the first gap in contact with the first III-N transistor and a second gap in contact with the second III-N transistor is. In one embodiment, the gaps may include an air gap, but may include a gap filled with any other suitable gas, dielectric, and / or liquid.

The 2A and 2 B 12 are cross-sectional views of an integrated circuit structure including a pair of adjacent III-N transistors having an improved insulator structure according to the first embodiment. Similar to 1A and 1B includes a base of the integrated circuit structure 200 a silicon substrate 202 and a III-nitride (III-N) substrate 204 over the silicon substrate 202 , The III-N transistors 206 can each have source and drain (S / D) regions 208 , a polarization layer 220 on the III-N substrate 204 between the (S / D) 208 and a gate electrode 212 over the polarization layer 220 include. In one embodiment, spacers 214 on both sides of the gate electrode 212 be arranged. metal contacts 216 can on the respective (S / D) regions 208 be formed. It is understood that a GaN channel (not shown) under the polarization layer 220 Part of a GaN substrate 204 can be. In one embodiment, the III-N transistors 206 III-N semiconductor materials such as gallium nitride (GaN), indium nitride (InN), aluminum nitride (AlN) and their compounds.

To the surface area of the interface between the contacts 216 and S / D regions 208 can increase the S / D regions 208 formed as shown with a non-planar or roughened surface. A non-planar or roughened surface creates non-horizontal surfaces within the footprint of the S / D contact 208th As used herein, a "non-horizontal surface" is a surface that is not parallel to a major or primary surface of the underlying GaN substrate 204 is. The inclusion of non-horizontal surfaces provides additional surface area for the interface without increasing the footprint. As used herein, a roughened surface may refer to a surface that is not polished (eg, with a chemical mechanical planarization (CMP) process).

According to the first embodiment and as in 2A As shown, the III-N transistors 206 are separated by an insulator structure having a shallow trench 218 includes that with a material 221 is filled. As shown, the shallow trench 218 over the entire span between the III-N transistors 206 formed such that sides of the respective source and drain regions 208 of the first and second III-N transistors side walls of the shallow trench 218 form. In one embodiment, the width of the shallow trench may be about 300 nm to several micrometers. Because the material 221 with the sidewalls of the transistors 206 Being in contact becomes a material 221 selected to be compatible with gallium nitride. Compatibility in this context means that the material 221 produces a good interface with a gallium nitride, leaving little to no charge at the interface between the two either through a solid charge material or through the interaction between the material 221 and the gallium nitride. In one embodiment, the material 221 that fill the trench, include any oxide or nitride or low-K dielectric, and examples may include C-doped SiOx, SiN, and the like, however, it should be noted that low-K dielectrics are more relevant due to the capacity penalty.

In one embodiment, the trench is 218 filled so that the material 221 coplanar with a top of the metal contacts 216 on the respective source and drain regions 208 the III-N transistors 206 is to create a flat surface over the transistors III-N 206 to create.

As in 2 B can be shown, the shallow trench 218 in another embodiment, be filled with a double-layer stack comprising a high-K dielectric liner 222 standing at the sidewalls and a bottom of the shallow trench 218 is formed, and the material 221 , such as an oxide, nitride or low-K dielectric deposited on top of the layer of high-K dielectric liner 222 is formed around a remainder of the shallow trench 218 to fill. At a Embodiment, the high-K dielectric liner 222 one of alumina and hafnium oxide. In one embodiment, the high-K dielectric liner 222 a thickness of about 2 nm.

Both in the 2A and 2 B In the illustrated embodiments, the shallow trench is approximately 200 nm to 500 nm in height, but in one embodiment does not reach a depth of the Si substrate 202 ,

3 FIG. 12 is a graph illustrating the leak improvement between a structure including a trench filled with standard materials such as Al 2 O 3 (stack # 1) versus a shallow trench filled with the silicon nitride / silicon oxide (stack # 2) of the present embodiments. The y-axis is a leak from mesa to mesa in volts and the x-axis is the current. As shown, stack # 1 with conventional materials results in a lick of 1.00E-07, while stack # 2 reduces licking to approximately 1.00E-11. Since the scale is logarithmic, the reduction in leakage provided by the trench filled with silica, for example, is significant.

4 FIG. 12 is a cross-sectional view of an integrated circuit structure including a pair of adjacent III-N transistors having an improved insulator structure according to the second embodiment, wherein like components of FIGS 2A have the same reference numerals. Similar to 2A includes the base of the integrated circuit structure 400 a silicon substrate 202 and a III-nitride (III-N) substrate 204 over the silicon substrate 202 , A pair of III-N transistors, such as GaN transistors 206 , can each source and drain S / D regions 208 , a polarization layer 120 on the III-N substrate 204 between the S / D 208 and a gate electrode 212 over the polarization layer 120 include. In one embodiment, spacers 214 on both sides of the gate electrode 212 be arranged. metal contacts 216 can on the respective S / D regions 208 be formed.

According to the second embodiment and as in 4 shown are the III-N transistors 206 separated by an insulator structure comprising at least two spaces, a first space 404a adjacent to the first III-N transistor and a second gap 404b (collectively, as gaps 404 designated) adjacent to the second III-N transistor 206 , In one embodiment, the first gap is 404a in physical contact with the first III-N transistor and the second gap 404b is in contact with the second III-N transistor. The insulator structure comprises an interlayer dielectric (ILD). 402 between the first and second III-N transistors 206 , The ILD 402 can also use the gate electrodes and spacers 214 between the metal contacts 216 the III-N transistors 206 cover.

The first and second spaces 404a and 404b become partially in the III-N substrate 204 and partly in the ILD 402 educated. More specifically, in one embodiment, the first gap 404a and the second space 404b respective upper sections and bottom sections, with the upper sections in the ILD 402 at about ½ of a height of the respective source and drain regions 208 the first and second III-N transistors 206 are arranged, and the bottom portions in the III-N substrate 204 at about one-half the depth of the III-N substrate 204 are arranged such that the bottom portions of the silicon substrate 202 do not contact. As shown, the first and second spaces are 404a and 404b formed as an opening with borders by the ILD 402 are defined along the upper portion and along a first side; bounded by the III-N substrate 204 along the bottom sections; and bounded by both the source and drain regions 208 as well as the III-N substrate 204 along a second side.

The gaps 404 For example, they may include an air gap, but may include a gap filled with any other suitable gas, dielectric, and / or liquid. As mentioned earlier, the presence of the gap 404 In various embodiments, reducing the parasitic capacitance and thus the performance of the first and second III-N transistors 206 increase.

The 5A-5G 15 are diagrams illustrating cross-sectional views showing the fabrication of a pair of III-N transistors with a shallow trench isolation structure according to the first embodiment. As is apparent in view of the structures formed, the process discloses techniques for isolating III-N transistors. Various transistor geometries may benefit from the techniques described herein, including, but not limited to, HEMT, pHEMT, transistors employing the 2DEG architecture, transistors employing 3DEG (or 3D polarization FET) architecture, multiple transistors Use quantum wells (MQW) or superlattice architecture. Additionally, the techniques may be used to form CMOS transistors / devices / circuits, where the III-N materials, such as GaN, transistor structures described differently herein, are used, for example, for the CMOS n-MOS transistors.

5A FIG. 12 illustrates the manufacturing process after a GaN film is formed on epitaxial growth and a polarizing film is formed on the GaN film. In some embodiments, the substrate may be a bulk substrate of Si, SiGe, or Ge. The polarizing layer may comprise aluminum and a nitride alloy, such as aluminum indium nitride (Al _x Ini _x N) or aluminum gallium nitride (Al _x Ga _x N). A portion of the polarizing layer may comprise an aluminum nitride (AlN) interlayer which may be deposited on the GaN layer to facilitate formation of the remainder of the polarizing layer and to further promote mobility in the resulting channel. At the interface of the polarization layer and the GaN layer, a conductive channel is formed. Formation of the GaN layer and the polarization layer may include any suitable techniques, such as growth of the GaN layer and the polarization layer in a metal organic chemical vapor deposition (MOCVD) chamber, or any other suitable deposition process.

5B Figure 13 illustrates the manufacturing process after performing shallow trench isolation (STI), in which the polarization layer and the GaN layer are etched to define positions for the isolation regions and adjacent source and drain regions. The trenches isolate the polarization portion from other portions of the polarization layer. As described below, the source and drain regions may be formed adjacent to the trenches. The removal of portions of the polarization layer results in an isolated conductive channel.

5C Fig. 10 illustrates the fabrication process after performing filling and polishing of STI, in which the trenches are filled with a dielectric material, such as silicon oxide, or optionally first lined with a high-K material and then filled with an oxide, followed by removal of the excess dielectric using a technique such as chemical mechanical planarization (CMP). In one embodiment, the high-K dielectric liner may comprise one of alumina and hafnium oxide.

5D FIG. 12 illustrates the manufacturing process after the formation of a dummy gate formed by depositing a dummy gate oxide, a dummy gate electrode (eg, poly-Si), and spacers on each side of the dummy gate electrode.

5E FIG. 12 illustrates the manufacturing process after source and drain S / D regions adjacent to the trenches are formed by masking the structure of FIG 5D and etching to remove the polarization layer in the S / D regions, followed by epitaxial re-growth of n-type S / D material. The material may be, for example, indium gallium nitride (InGaN) doped with Si to form n-type S / D regions. In some embodiments, the S / D material may be n-type doped gallium nitride, n-type doped indium gallium nitride with a graded indium composition, or any other suitable material.

5F FIG. 12 illustrates the fabrication process after an interlayer dielectric (ILD) is deposited and planarized, eg, on top of the dummy gate electrode or on top of the current device level, and additional dielectric material of FIG 5C is added to the trenches.

5G FIG. 10 illustrates the manufacturing process according to a Replacement Metal Gate (RMG) process in which the dummy gate and gate oxide are removed to expose the channel region of the transistors and a gate dielectric and an exchange metal gate are formed in the exposed channel region, respectively. 5G Figure 12 also shows the process of etching the ILD to form holes and metal contacts (eg, M0) formed in the holes in contact with the S / D regions, completing the process. In one embodiment, the metal contacts may include tungsten or any other suitable conductive material.

Other embodiments may include a standard gate stack formed by any suitable process, such as a subtractive process in which the gate dielectric / gate metal is deposited and then followed by one or more etch processes. Any number of standard back-end processes may also be performed to complete the formation of one or more transistors.

Insulating adjacent III-N transistors with a shallow trench isolation structure filled with an oxide, nitride, or low-K material without a high-K liner in a manner as described above relies on CMOS-compatible processes as well the development of suitable materials for passivating III-N sidewalls and reducing leakage through these interfaces. The approach can be used in modern silicon 300-millimeter semiconductor manufacturing equipment. The process provides the ready integration of III-N devices with silicon CMOS.

The 6A-6F Fig. 3 are diagrams illustrating cross-sectional views showing the fabrication of a pair of III-N transistors formed by a pair of III-N transistors Isolation structure are separated, comprising at least two spaces in the III-N substrate and the dielectric material, which separates the two transistors according to the second embodiment. As is apparent in view of the structures formed, the process discloses techniques for isolating III-N transistors. Various transistor geometries may benefit from the techniques described herein, including, but not limited to, HEMT, pHEMT, transistors employing the 2DEG architecture, transistors employing 3DEG (or 3D polarization FET) architecture, multiple transistors Use quantum wells (MQW) or superlattice architecture. Additionally, the techniques may be used to form CMOS transistors / devices / circuits, where the III-N materials, such as GaN, transistor structures described differently herein, are used, for example, for the CMOS n-MOS transistors.

6A FIG. 12 illustrates the manufacturing process after a GaN film is epitaxially grown on a Si substrate and a polarizing film is formed on the GaN film. In some embodiments, the substrate may be a bulk substrate of Si, SiGe, or Ge. The polarizing layer may comprise aluminum + nitride alloy, such as aluminum indium nitride (Al _x Ini _x N) or aluminum gallium nitride (Al _x Ga _x N). A portion of the polarizing layer may comprise an aluminum nitride (AlN) interlayer which may be deposited on the GaN layer to facilitate formation of the remainder of the polarizing layer and to further promote mobility in the resulting channel. At the interface of the polarization layer and the GaN layer, a conductive channel is formed. The formation of the GaN layer and the polarization layer may include any suitable techniques, such as growing the GaN layer and the polarization layer in a metal organic chemical vapor deposition (MOCVD) chamber, or any other suitable deposition process.

6B Figure 13 illustrates the manufacturing process after performing the shallow trench isolation (STI), in which the polarization layer and the GaN layer are etched to define positions for the isolation regions and adjacent source and drain regions. The trenches isolate the polarization portion from other portions of the polarization layer. As described below, the source and drain regions may be formed adjacent to the trenches. The removal of portions of the polarization layer results in an isolated conductive channel.

6C FIG. 12 illustrates the manufacturing process after a sacrificial layer is formed and etched to form spacers on the sidewalls of the trenches.

6D Figure 12 illustrates the fabrication process after performing filling and polishing of STI in which a remainder of the trenches is filled with a dielectric material, followed by removal of the excess dielectric using a technique such as chemical mechanical planarization (CMP).

6E illustrates the manufacturing process after completion of the GaN transistor up to metal layer M0. Completion of the GaN transistor up to M0 may include: forming the source and drain S / D regions by masking the structure of 6D and etching to remove the polarizing layer in the S / D regions, followed by epitaxial re-growth of n-type S / D material; Formation of a dummy gate; Forming and planarizing an interlayer dielectric (ILD); Removing the dummy gate electrode to expose a channel region and forming an exchange metal gate over the exposed channel region; and formation of metal contacts (eg M0) in contact with the S / D regions.

6F FIG. 12 illustrates the manufacturing process after the spacers are etched from the sidewalls of the trenches to expose respective air gaps on each side of the GaN transistor. In one embodiment, the air gaps may be filled with any suitable gas and / or liquid or left with air only.

Other embodiments may include a standard gate stack formed by any suitable process, such as a subtractive process in which the gate dielectric / gate metal is deposited and then followed by one or more etch processes. Any number of standard back-end processes may also be performed to complete the formation of one or more transistors.

Isolating adjacent III-N transistors with at least two spaces, eg, air gaps, combines air isolation with CMOS-compatible operations. In particular, there is a development of air gap technology in which sacrificial materials are placed for structural rigidity and then removed at the end of the process to reduce parasitic capacitance. This is usually done in the BEOL, but according to the present embodiments, it is implemented as part of the STI stack. Such a compatible approach combines the benefits of III-N Silicon CMOS devices in modern silicon 300-millimeter semiconductor manufacturing equipment.

Both in the 5A-5G and 6A-6F For example, the GaN substrate layer may be formed over any suitable underlying substrate or structure (not shown). In one embodiment, an underlying substrate is a silicon ( 111 ) Substrate representing a general workpiece object used for manufacturing integrated circuits. The underlying substrate often includes a wafer or other piece of silicon or other semiconductor material. Suitable semiconductor substrates include, but are not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI), as well as similar substrates formed from other semiconductor materials such as germanium, carbon, or group III substrates -V materials include. The underlying substrate may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates.

The polarization layer 210 may include aluminum nitride (AlN), aluminum gallium nitride (AlGaN), indium aluminum nitride (InAlN), indium aluminum gallium nitride (InAlGaN), or any other suitable material, depending on the end use or target application. In the in the 2A . 2 B and 4 As shown, the gate stack may include a gate electrode and a gate dielectric formed directly under the gate electrode. The gate dielectric may be, for example, any suitable oxide, such as silicon dioxide, or high-K gate dielectric materials. Examples of high-k gate dielectric materials include, for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum. Oxide and lead-zinc niobate. In some embodiments, an annealing process may be performed on the gate dielectric layer to improve its quality when using a high-k material. In general, the thickness of the gate dielectric should be sufficient to electrically insulate the gate electrode from the source and drain contacts.

Further, the gate electrode may comprise a wide range of materials such as polysilicon, silicon nitride, silicon carbide or various suitable metals or metal alloys such as aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), titanium nitride (TiN) or tantalum nitride (TaN). Various back-end processes can also be performed, such as making contacts 216 in the S / D regions 208 using, for example, a silicidation process (generally deposition of contact metal and subsequent annealing).

The integrated circuit structures described herein may be included in an electronic device. As an example of such a device, are 7A and 7B Top views of a wafer and die comprising one or more III-N transistors with CMOS-compatible isolation structures according to one or more embodiments disclosed herein.

Referring to 7A and 7B , can be a wafer 700 consist of a semiconductor material and can one or more dies 702 with integrated circuit (IC) structures mounted on a surface of the wafer 700 are formed. Everyone of this 702 may be a repeating unit of a semiconductor product comprising any suitable IC (eg, ICs comprising one or more III-N transistors having CMOS-compatible isolation structures as described above). After the fabrication of the semiconductor product is completed, the wafer can 700 undergo a singulation process in which each of the dies 702 is separated from another to provide individual "chips" of the semiconductor product. In particular, structures comprising embedded nonvolatile memory structures having an independently scaled selector as disclosed herein may be the shape of the wafer 700 (eg not isolated) or the shape of the Dies 702 (eg isolated). The Die 702 may include one or more embedded nonvolatile memory structures based on independently scaled selectors, and / or supporting circuitry to route electrical signals, as well as any other IC components. In some embodiments, the wafer may 700 or the die 702 an additional memory device (eg, a static random access memory (SRAM) device), a logic device (eg, an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Several of these components can work on a single die 702 be combined. For example, a memory array formed by a plurality of memory devices may reside on a same die 702 as a processing device or other logic configured to store information in the memory devices or execute instructions stored in the memory array.

Embodiments disclosed herein may be used to a great variety produce different types of integrated circuits and / or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, and the like. In other embodiments, a semiconductor memory may be manufactured. Furthermore, the integrated circuits or other microelectronic devices may be used in a variety of electronic devices known in the art. For example, in computer systems (eg, desktop, laptop, server), cell phones, personal electronics, etc. The integrated circuits may be coupled to a bus and other components in the systems. For example, a processor may be coupled to a memory, chipset, etc. through one or more buses. Any of the processor, memory, and chipset can potentially be fabricated using the approaches disclosed herein.

8th FIG. 12 is a cross-sectional side view of an integrated circuit (IC) device arrangement that may include one or more III-N transistors with CMOS-compatible isolation structures, in accordance with one or more embodiments disclosed herein.

With reference to 8th includes an IC device arrangement 800 Components having one or more of the integrated circuit structures described herein. The IC device arrangement 800 has a number of components mounted on a circuit board 802 are arranged (which may be, for example, a motherboard). The IC device arrangement 800 includes components that are on a first surface 840 the circuit board 802 and an opposite second surface 842 the circuit board 802 are arranged. In general, components can be on one or both surfaces 840 and 842 be arranged. In particular, any suitable ones of the components of the IC device arrangement may be used 800 comprise a number of III-N transistors with CMOS-compatible isolation structures as disclosed herein.

In some embodiments, the circuit board may 802 a printed circuit board (PCB) comprising a plurality of metal layers separated by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to conduct electrical signals (optionally in conjunction with other metal layers) between the components connected to the circuit board 802 are coupled. In other embodiments, the circuit board 802 a non-PCB substrate.

The IC device arrangement 800 , in the 8th includes a package-on-interposer structure 836 that with the first surface 840 the circuit board 802 through coupling components 816 is coupled. The coupling components 816 can use the enclosure-on-interposer structure 836 electrically and mechanically with the circuit board 802 couple and may include solder balls (as in 8th shown), plug and socket, an adhesive, underfill material and / or any other suitable electrical and / or mechanical coupling structure.

The enclosure-on-interposer structure 836 can be an ic package 820 include that with an interposer 804 through coupling components 818 is coupled. The coupling components 818 may take any suitable form for the application, such as the forms referred to above with reference to the coupling components 816 were discussed. Although a single IC package 820 in 8th As shown, multiple IC packages can be used with the Interposer 804 be coupled. It should be noted that additional interposer with the interposer 804 can be coupled. The interposer 804 may provide an intervening substrate that is used to connect the circuit board 802 and the IC package 820 to bridge. The IC package 820 For example, a die (die 702 from 7B) or any other suitable component or include the same. In general, the Interposer 804 propagate a connection to another distance or redirect a connection to a different connection. For example, the Interposer 804 the IC package 820 (Eg a die) with a ball grid array (BGA) of the coupling components 816 for coupling to the circuit board 802 couple. At the in 8th illustrated embodiment, the IC package 820 and the circuit board 802 on opposite sides of the interposer 804 appropriate. In other embodiments, the IC package 820 and the circuit board 802 on the same side of the interposer 804 to be appropriate. In some embodiments, three or more components may use the interposer 804 be interconnected.

The interposer 804 may be formed of an epoxy resin, a glass fiber reinforced epoxy resin, a ceramic material or a polymeric material, such as polyimide. In some implementations, the interposer may be 804 may be formed of alternating rigid or flexible materials which may comprise the same materials described above for use with a semiconductor substrate, such as Silicon, germanium and other group III-V and group IV materials. The interposer 804 can metal interconnects 810 and vias 808 include, but are not limited to, through-silicon via (TSV) 806 , The interposer 804 can also embedded components 814 comprising both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, ESD (electrostatic discharge) devices, and memory devices. More complex components such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical system (MEMS) devices may also be present on the interposer 804 be formed. The enclosure-on-interposer structure 836 may take the form of any housing-on-interposer structures known in the art.

The IC device arrangement 800 can be an ic package 824 include that with the first surface 840 the circuit board 802 through coupling components 822 is coupled. The coupling components 822 may take the form of any of the embodiments discussed above with respect to the coupling components 816 and the IC package 824 may take the form of any of the embodiments described above with reference to the IC package 820 were discussed.

The IC device arrangement 800 , in the 8th includes a housing-on-housing structure 834 that with the second surface 842 the circuit board 802 through coupling components 828 is coupled. The housing-on-housing structure 834 can be an ic package 826 and an IC package 832 comprising, by coupling components 830 coupled together, such that the IC package 826 between the circuit board 802 and the IC package 832 is arranged. The coupling components 828 and 830 may take the form of any of the embodiments of the coupling components 816 assume that were discussed above, and the IC package 826 and 832 may take the form of any of the embodiments of the IC package discussed above 820 accept. The housing-on-housing structure 834 may be formed according to any of the housing-on-housing structures known in the art.

9 represents a computing device 900 according to an implementation of the disclosure. The computing device 900 Hoards a board 902 , The board 902 may include a number of components, including but not limited to a processor 904 and at least one communication chip 906 , The processor 904 is physical and electrical with the board 902 coupled. In some implementations, the at least one communication chip 906 also physically and electrically with the board 902 be coupled. In further implementations, the communication chip is 906 Part of the processor 904 ,

Depending on their applications, the computing device may 900 Include other components that are physically and electrically connected to the board 902 coupled or not. These other components include, but are not limited to, volatile memory (eg, DRAM), nonvolatile memory (eg, ROM), flash memory, graphics processor, digital signal processor, crypto processor, chipset, antenna, and the like Display, a touchscreen display, a touch screen control, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk, digital versatile disk, etc.).

The communication chip 906 enables wireless communication for the transmission of data to and from the computing device 900 , The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not include any wires, although they may not do so in some embodiments. The communication chip 906 can implement any number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA +, HSDPA +, HSUPA + , EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols referred to as 3G, 4G, 5G, and beyond. The computing device 900 can a plurality of communication chips 906 include. For example, a first communication chip 906 earmarked for shorter range wireless communication such as Wi-Fi and Bluetooth, and a second communication chip 906 may be earmarked for wireless communication with longer range such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 904 the computing device 900 includes an integrated circuit die, which is inside the processor 904 is housed. In some implementations of the disclosure, the integrated circuit die of the processor includes one or more III-N transistors having CMOS-compatible isolation structures according to implementations of the embodiments of the disclosure. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform that electronic data into other electronic data that may be stored in registers and / or memory.

The communication chip 906 Also includes an integrated circuit die, which is inside the communication chip 906 is housed. According to another implementation of the embodiments of the disclosure, the integrated circuit die of the communication chip comprises one or more III-N transistors with CMOS-compatible isolation structures according to implementations of the embodiments of the disclosure.

In further implementations, another component that is within the computing device 900 is housed an integrated circuit die comprising one or more III-N transistors with CMOS-compatible isolation structures in accordance with implementations of the embodiments of the disclosure.

In various implementations, the computing device may 900 a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a PDA (personal digital assistant), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player or a digital video recorder. In further implementations, the computing device 900 be any other electronic device that processes data.

Thus, the embodiments described herein include III-N transistors with CMOS-compatible isolation structures.

The foregoing description of illustrative implementations of embodiments of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations, and examples thereof, of the disclosure are described herein for illustrative purposes, various equivalent changes within the scope of the disclosure are possible as those skilled in the relevant art will recognize.

These changes may be made to the disclosure based on the description made above. The terms used in the following claims should not be considered to limit the disclosure to the specific implementations disclosed in the specification and claims. Instead, the scope of the disclosure should be determined entirely by the following claims, which are to be construed in accordance with established specifications of the claims interpretation.

Exemplary Embodiment 1: An integrated circuit structure includes a silicon substrate and a III-nitride (III-N) substrate over the silicon substrate. A first III-N transistor and a second III-N transistor are on the III-N substrate. An insulator structure is formed in the III-N substrate between the first III-N transistor and the second III-N, the insulator structure comprising one of: a shallow trench filled with an oxide, nitride, or low-K dielectric is; or a first gap adjacent to the first III-N transistor and a second gap adjacent to the second III-N transistor.

Exemplary Embodiment 2: The integrated circuit structure according to Exemplary Embodiment 1, wherein the first III-N transistor and the second III-N transistor include gallium nitride (GaN) transistors.

Exemplary Embodiment 3: The integrated circuit structure according to Exemplary Embodiment 1 or 2, wherein the silicon oxide is coplanar with an upper surface of metal contacts on the respective source and drain regions of the first III-N transistor and the second III-N transistor.

Exemplary Embodiment 4: The integrated circuit structure according to Exemplary Embodiment 1, 2 or 3, wherein the shallow trench is filled with a double-layer stack comprising a high-K dielectric liner formed on the sidewalls and a bottom of the shallow trench , and the oxide, nitride or low-K dielectric formed on the layer of high-K dielectric filling a remainder of the trench.

Exemplary Embodiment 5: The integrated circuit structure according to Exemplary Embodiment 4, wherein the high-K dielectric liner comprises one of alumina and hafnium oxide.

Exemplary Embodiment 6: The integrated circuit structure according to Exemplary Embodiment 4 or 5, wherein the high-K dielectric liner has a thickness of approximately 2 nm.

Exemplary Embodiment 7: The integrated circuit structure according to Exemplary Embodiment 1, 2, 3, 4, 5 or 6, wherein a height of the shallow trench is about 200 nm to 500 nm.

Exemplary Embodiment 8: The integrated circuit structure according to Exemplary Embodiment 1, 2, 3, 4, 5, 6, or 7, wherein sides of the respective source and drain regions of the first III-N transistor and the second III-N transistor are sidewalls of the shallow trench.

Exemplary Embodiment 9: The integrated circuit structure according to Exemplary Embodiment 1, 2, 3, 4, 5, 6, 7 or 8, wherein the width of the shallow trench is about 300 nm to several micrometers.

Exemplary Embodiment 10: The integrated circuit structure according to Exemplary Embodiment 1, wherein the first gap is in contact with a source and drain region of the first III-N transistor and the second gap is in contact with a source-drain region of the second III N-type transistor, wherein the first gap and the second gap are separated by a dielectric material.

Exemplary Embodiment 11: The integrated circuit structure according to Exemplary Embodiment 10, wherein the first gap and the second gallium nitride (gan) gap are filled at least one of air, a gas, a dielectric, and a liquid.

Exemplary Embodiment 12: The integrated circuit structure according to Exemplary Embodiment 10 or 11, wherein the first space and the second space have respective upper portions and bottom portions, the upper portions in an interlayer dielectric (ILD) at approximately ½ of a height of the respective source. and drain regions of the first III-N transistor and the second III-N transistor, and the bottom portions in the III-N substrate are disposed at approximately one-half the depth of the III-N substrate such that the bottom sections do not contact the silicon substrate.

Exemplary Embodiment 13: The integrated circuit structure according to Exemplary Embodiment 10, 11 or 12, wherein the first gap and the second gap are formed as an opening having boundaries formed by an interlayer dielectric (ILD) along an upper portion and along a first side bounded by the III-N substrate along bottom portions; and bounded by both the source and drain regions and the III-N substrate along a second side.

Exemplary Embodiment 14: The integrated circuit structure according to Exemplary Embodiment 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, or 13, wherein the first III-N transistor has source and drain regions , a polarization layer on the III-N substrate between the source and drain regions, and a gate electrode over the polarization layer.

Exemplary Embodiment 15: The integrated circuit structure according to Exemplary Embodiment 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 or 14, wherein the second III-N transistor has source and drain Regions, a polarization layer on the III-N substrate between the source and drain regions and a gate electrode over the polarization layer.

Exemplary Embodiment 16: A method for producing a gallium nitride (GaN) transistor includes forming a GaN layer on a Si substrate and forming a polarizing layer on the GaN layer. A shallow trench isolation is performed to etch the polarization layer and the GaN layer to define locations for isolation regions and adjacent source and drain regions. The trenches are filled with a dielectric material. A dummy gate is formed and spacers are formed on each side of the dummy gate. Source and drain regions are formed adjacent to the trenches. An interlayer dielectric (ILD) is formed on an upper surface of the dummy gate. The dummy gate is removed to expose a channel region, and an exchange metal gate is formed over the exposed channel region. And metal contacts are formed in contact with the source and drain regions.

Exemplary Embodiment 17: The method of embodiment 16, wherein filling the trenches with a dielectric material further comprises: filling the trenches with dielectric material comprising an oxide, nitride, or low-K dielectric.

Exemplary Embodiment 18: The method embodiment of claim 16 or 17, further comprising filling the trenches such that the oxide, nitride, or low-K dielectric is coplanar with an upper surface of the metal contacts on the respective source and drain regions.

Exemplary Embodiment 19: The method of embodiment 16, 17 or 18, further comprising: lining the trenches with a high K material and then filling the trenches with at least one of alumina and hafnia.

Exemplary Embodiment 20: The method of embodiment 16, 17, 18 or 19, wherein forming the source and drain regions further comprises: etching the polarization layer in the source and drain regions, followed by epitaxial re-growth of n- Type S / D material.

Exemplary Embodiment 21: The method of embodiment 16, 17, 18, 19 or 20, further comprising forming the shallow trench at a height of about 200 nm to 500 nm.

Exemplary Embodiment 22: A method of manufacturing a gallium nitride (GaN) transistor includes forming a GaN layer on a Si substrate and forming a polarizing layer on the GaN layer. A shallow trench isolation is performed to etch the polarization layer and the GaN layer to define locations for isolation regions and adjacent source and drain regions. A sacrificial layer is formed in the trenches and etching the sacrificial layer to form spacers on sidewalls of the trenches. The remainder of the trenches are filled with an interlayer dielectric (ILD). The formation of the GaN transistor up to metal layer M0 is then completed. The spacers are etched from the sidewalls of the trenches to expose respective gaps on each side of the GaN transistor.

Exemplary Embodiment 23: The method of embodiment 22, further comprising: filling the gaps with at least one of air, a gas, a dielectric, and a liquid.

Exemplary Embodiment 24: The method of embodiment 22 or 23, further comprising: forming the spacers such that as the spacers are removed, the gaps are in contact with the source and drain regions of the GaN transistor.

Exemplary Embodiment 25: The method of embodiment 22, 23 or 24, further comprising: forming the spacers so that, as the spacers are removed, the gaps are formed as an opening having boundaries defined by ILD along an upper portion and along a top first side defined by the III-N substrate along bottom portions; and bounded by both the source and drain regions and the III-N substrate along a second side.

Claims (25)

An integrated circuit structure comprising: a silicon substrate; a III-nitride (III-N) substrate over the silicon substrate; a first III-N transistor and a second III-N transistor on the III-N substrate; and an insulator structure formed in the III-N substrate between the first III-N transistor and the second III-N transistor, wherein the insulator structure comprises one of: a shallow trench filled with an oxide, nitride or low-K dielectric; or a first gap adjacent to the first III-N transistor and a second gap adjacent to the second III-N transistor. The integrated circuit structure according to Claim 1 wherein the first III-N transistor and the second III-N transistor comprise gallium nitride (GaN) transistors. The integrated circuit structure according to Claim 1 or 2 wherein the oxide, nitride or low-K dielectric is coplanar with an upper surface of metal contacts on the respective source and drain regions of the first III-N transistor and the second III-N transistor. The integrated circuit structure according to Claim 1 . 2 or 3 wherein the shallow trench is filled with a double-layer stack comprising a high-K dielectric liner formed on the sidewalls and a bottom of the shallow trench and the oxide, nitride or low-K dielectric on formed the high-K dielectric and fills a remainder of the shallow trench. The integrated circuit structure according to Claim 4 wherein the high-K dielectric liner comprises one of alumina and hafnium oxide. The integrated circuit structure according to Claim 4 or 5 wherein the high-K dielectric liner has a thickness of about 2 nm. The integrated circuit structure according to Claim 1 . 2 . 3 . 4 . 5 or 6 , wherein the shallow trench extends into the III-N substrate to a depth of about 200 nm to 500 nm. The integrated circuit structure according to Claim 1 . 2 . 3 . 4 . 5 . 6 or 7 wherein sides of the respective source and drain regions of the first III-N transistor and the second III-N transistor form sidewalls of the shallow trench. The integrated circuit structure according to Claim 1 . 2 . 3 . 4 . 5 . 6 . 7 or 8th wherein a width of the shallow trench is about 300 nm to several micrometers. The integrated circuit structure according to one of the preceding claims, wherein the first gap is in contact with a source and drain region of the first III-N transistor and the second gap is in contact with a source-drain region of the second III-N transistor. Transistor is, wherein the first gap and the second gap are separated by a dielectric material. The integrated circuit structure according to Claim 10 wherein the first gap and the second gap are filled with at least one of air, a gas, a dielectric, and a liquid. The integrated circuit structure according to Claim 10 or 11 wherein the first gap and the second gap have respective upper portions and bottom portions, the upper portions in an interlayer dielectric (ILD) at approximately ½ of a height of the respective source and drain regions of the first III-N transistor and second III-N transistor, and the bottom portions in the III-N substrate are disposed at approximately one-half of a depth of the III-N substrate, such that the bottom portions do not contact the silicon substrate. The integrated circuit structure according to Claim 10 . 11 or 12 wherein the first gap and the second gap are formed as an opening with boundaries defined by an interlayer dielectric (ILD) along an upper portion and along a first side bounded by the III-N substrate along bottom portions; and bounded by both the source and drain regions and the III-N substrate along a second side. The integrated circuit structure according to Claim 1 . 2 . 3 . 4 . 5 . 6 . 7 . 8th . 9 . 10 . 11 . 12 or 13 wherein the first III-N transistor includes source and drain regions, a polarization layer on the III-N substrate between the source and drain regions, and a gate electrode over the polarization layer. The integrated circuit structure according to Claim 1 . 2 . 3 . 4 . 5 . 6 . 7 . 8th . 9 . 10 . 11 . 12 . 13 or 14 wherein the second III-N transistor comprises source and drain regions, a polarization layer on the III-N substrate between the source and drain regions, and a gate electrode over the polarization layer. A method of making a gallium nitride (GaN) transistor, the method comprising: Forming a GaN layer on an Si substrate and forming a polarizing layer on the GaN layer; Performing shallow trench isolation to etch the polarization layer and the GaN layer to define locations for isolation regions and adjacent source and drain regions; Filling the trenches with a dielectric material; Forming a dummy gate and forming spacers on each side of the dummy gate; Forming source and drain regions adjacent to the trenches; Depositing and planarizing an interlayer dielectric (ILD) on an upper surface of the dummy gate; Removing the dummy gate to expose a channel region and forming an exchange metal gate over the exposed channel region; and Forming metal contacts in contact with the source and drain regions. The method according to Claim 16 wherein filling the trenches with the dielectric material further comprises: filling the trenches with dielectric material comprising an oxide, nitride, or low-K dielectric. The method according to Claim 16 or 17 further comprising filling the trenches such that the dielectric material is coplanar with an upper surface of the metal contacts on the respective source and drain regions. The method according to Claim 16 . 17 or 18 , further comprising: lining the trenches with a high K material and then filling the trenches with at least one of alumina and hafnia. The method according to Claim 16 . 17 . 18 or 19 wherein forming the source and drain regions further comprises: etching the Polarization layer in the source and drain regions, followed by epitaxial re-growth of n-type S / D material. The method according to Claim 16 . 17 . 18 . 19 or 20 further comprising forming the shallow trench at a height of about 200 nm to 500 nm. A method of making a gallium nitride (GaN) transistor, the method comprising: Forming a GaN layer on an Si substrate and forming a polarizing layer on the GaN layer; Performing shallow trench isolation to etch the polarization layer and the GaN layer to define locations for isolation regions and adjacent source and drain regions; Forming a sacrificial layer in the trenches and etching the sacrificial layer to form spacers on sidewalls of the trenches; Filling a remainder of the trenches with an interlayer dielectric (ILD); Completion of the formation of the GaN transistor up to metal layer M0; Etching the spacers from the sidewalls of the trenches to expose respective gaps on each side of the GaN transistor. The method according to Claim 22 , further comprising: filling the gaps with at least one of air, a gas, a dielectric, and a liquid. The method according to Claim 22 or 23 , further comprising: forming the spacers such that, as the spacers are removed, the gaps are in contact with the source and drain regions of the GaN transistor. The method according to Claim 22 . 23 or 24 further comprising: forming the spacers such that, as the spacers are removed, the gaps are formed as an opening having boundaries defined by ILD along an upper portion and along a first side bounded by the III-N substrate along floor sections; and bounded by both the source and drain regions and the III-N substrate along a second side.

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