DE102018111231B4 - Power semiconductor device and method for manufacturing a power semiconductor device - Google Patents

Abstract

Power semiconductor device (1) comprising the following:
- a semiconductor body (10) comprising the following:
- an active area (106) configured to carry a load current,
- a chip edge (109) that laterally closes off the semiconductor body (10), and
- a border termination area (108) that is arranged laterally between the chip edge (109) and the active area (106);
- a semi-insulating layer (15) covering at least part of the semiconductor body (10) within the edge termination region (108); and
- a first passivation layer (16) arranged on at least a part of the semi-insulating layer (15); wherein:
- the first passivation layer (16) comprises a silicon-doped amorphous aluminium oxide;
- a thickness of the first passivation layer (16) or, if a silicon nitride layer (19) is arranged on the first passivation layer (16), a total thickness of the first passivation layer (16) and the silicon nitride layer (19) is in the range of 1 nm to 60 nm;
- the first passivation layer (16) and/or the silicon nitride layer (19) are not structured.

Description

TECHNICAL AREA

This description relates to embodiments of a power semiconductor device and to embodiments of a method for manufacturing a power semiconductor device. In particular, this description relates to embodiments of a power semiconductor device with a semi-insulating layer within an edge termination region and embodiments of a method for manufacturing such a device.

BACKGROUND

Many functions of modern devices in automotive, consumer, and industrial applications, such as converting electrical energy and driving an electric motor or machine, depend on power semiconductor devices. Insulated-gate bipolar transistors (IGBTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), and diodes, to name just a few, have been used for a wide variety of applications, including, among others, switches in power supplies and power converters.

A power semiconductor device typically comprises a semiconductor body configured to conduct a load current along a load current path between two load terminals of the device. Furthermore, the load current path can be controlled by an insulated electrode, sometimes referred to as a gate electrode. For example, upon receiving an appropriate control signal, such as from a driver unit, the control electrode can switch the power semiconductor device into a conducting or a blocking state.

Furthermore, the power semiconductor device for conducting the load current can comprise one or more power cells, which may be arranged in a so-called active region of the power semiconductor device. The power semiconductor device may be laterally bounded by a border, and between the border and the active region containing the one or more power cells, a border termination region, which may include a border termination structure, may be arranged. Such a border termination structure may serve the purpose of influencing the distribution of an electric field within the semiconductor body, for example, to ensure reliable blocking capability of the power semiconductor device. The termination structure may comprise one or more components arranged within the semiconductor body and also one or more components arranged above a surface of the semiconductor body.

For example, in such a semiconductor device with an edge termination region, an active passivation layer, e.g., in the form of a semi-insulating layer covering at least part of the semiconductor body, can be arranged within the edge termination region. Such an active passivation layer can, for example, serve the purpose of attenuating the unwanted influence of charge carriers originating from outside the semiconductor body (e.g., a potting compound encapsulating the semiconductor body) on electrical properties, such as voltage-blocking capability, of the semiconductor device. A general purpose is to prevent leakage of an electric field within the edge termination region and to limit the electric field strength as a whole near the surfaces of the semiconductor body and, for example, within a passivation layer. Furthermore, it may be desirable for structures arranged within the edge termination region, such as edge termination structures and passivation layers, to withstand a humid environment that could potentially promote electrochemical reactions, such as corrosion, in such structures.

The US 2018 / 0 047 652 A1 Describes a power semiconductor device comprising a wafer, wherein a passivation layer structure is formed on at least a portion of a wafer surface in a termination region of the device; the passivation layer structure comprises, in sequence from the surface of the wafer in a direction away from the wafer, a semi-insulating layer, a silicon nitride layer, and an undoped silicate glass layer; wherein the power semiconductor device further comprises an organic dielectric layer; wherein the silicon nitride layer has a thickness of at least 0.5 µm; wherein the organic dielectric layer adjoins the undoped silicate glass layer, and the undoped silicate glass layer adjoins the silicon nitride layer.

The DE 10 2014 108 986 A1 This describes a power semiconductor device. The power semiconductor device comprises a semiconductor body with an active zone and a high-voltage peripheral zone laterally adjacent to each other, wherein the high-voltage peripheral zone laterally surrounds the active zone, a metallization layer on the front surface of the semiconductor body, bonded to the active zone, a first barrier layer comprising a high-melting-point metal or a high-melting-point alloy, arranged between the active zone and the metallization layer, and a second barrier layer comprising at least a portion the peripheral zone is covered, wherein the second barrier layer comprises an amorphous semi-insulating material, wherein the first barrier layer and the second barrier layer partially overlap and form an overlap zone, the overlap zone extending over the entire circumference of the active zone.

The US 2011 / 0 297 958 A1 as well as the US 2008 / 0 308 911 A1 describe the use of diamond near a control electrode.

The DE 11 2015 004 093 T5 This describes a MOS gate structure on the front surface of a silicon carbide semiconductor base, comprising a p-well layer, an n+ source region, a gate insulating film, and a gate electrode. An intermediate insulating film covers the gate electrode and is in contact with the gate insulating film. A titanium film covers the intermediate insulating film over a titanium nitride film. A source electrode is positioned on a surface of the titanium film, but not in contact with the intermediate insulating film. The source electrode is electrically connected to the p-well layer and the n+ source region via the titanium film and a front silicide layer. The titanium film serves to absorb/block hydrogen atoms/hydrogen ions generated from within the source electrode during high-temperature operation.

Further examples of passivation layers can be found in the documents C. Yang et al.: Characteristic Study of Silicon Nitride Films Deposited by LPCVD and PECVD in Silicon, Vol. 10(6), 2018, pp. 2561 to 2567. - ISSN: 1876-990X as well as J. Schmidt et al.: Effective surface passivation of crystalline silicon using ultrathin Al2O3 films and Al2O3/SiNx stacks in Phys. Status Solidi RRL, Vol. 3(9), 2009, pp. 287 to 289. - ISSN: 1862-6254 known.

SUMMARY

The invention is specified in the independent claims. Features of some embodiments are specified in the dependent claims.

For example, a power semiconductor device comprises the following: a semiconductor body having an active region configured to conduct a load current, a chip edge that laterally terminates the semiconductor body, and an edge termination region arranged laterally between the chip edge and the active region; a semi-insulating layer covering at least a portion of the semiconductor body within the edge termination region; and a first passivation layer arranged on at least a portion of the semi-insulating layer. The first passivation layer comprises silicon-doped amorphous aluminum oxide.

According to another example, a power semiconductor device comprises the following: a semiconductor body having an active region configured to conduct a load current, a chip edge that laterally terminates the semiconductor body, and an edge termination region arranged laterally between the chip edge and the active region; a semi-insulating layer covering at least a portion of the semiconductor body within the edge termination region; and a first passivation layer arranged on at least a portion of the semi-insulating layer. The first passivation layer comprises atoms capable of forming valence bonds with atoms of the semi-insulating layer, thereby preventing oxidation of the semi-insulating layer.

According to another example, a power semiconductor device comprises: a semiconductor body having an active region configured to conduct a load current, a chip edge terminating the semiconductor body laterally, and an edge termination region arranged laterally between the chip edge and the active region; a semi-insulating layer covering at least a portion of the semiconductor body within the edge termination region; and a first passivation layer arranged on at least a portion of the semi-insulating layer, the first passivation layer being formed by atomic layer deposition.

Another example relates to a method for fabricating a power semiconductor device, wherein the power semiconductor device comprises a semiconductor body having an active region configured to conduct a load current, a chip edge that laterally terminates the semiconductor body, and an edge termination region arranged laterally between the chip edge and the active region. The method comprises: forming a semi-insulating layer on at least a portion of the semiconductor body within the edge termination region; and forming a first passivation layer on at least a portion of the semi-insulating layer, wherein the first passivation layer comprises silicon-doped amorphous aluminum oxide.

Another example relates to a method for manufacturing a power semiconductor device, wherein the power semiconductor device comprises a semiconductor body containing an active region configured to conduct a load current, a chip edge that laterally encloses the semiconductor body, and The method comprises: forming a border termination region located laterally between the chip edge and the active region; and forming a first passivation layer on at least a portion of the semiconductor body within the border termination region; and forming a first passivation layer on at least a portion of the semi-insulating layer, wherein the first passivation layer comprises atoms capable of forming valence bonds with atoms of the semi-insulating layer, thereby preventing oxidation of the semi-insulating layer.

Another example relates to a method for fabricating a power semiconductor device, wherein the power semiconductor device comprises a semiconductor body having an active region configured to conduct a load current, a chip edge that laterally terminates the semiconductor body, and an edge termination region arranged laterally between the chip edge and the active region. The method comprises: forming a semi-insulating layer on at least a portion of the semiconductor body within the edge termination region; and forming a first passivation layer on at least a portion of the semi-insulating layer, wherein the formation of the first passivation layer comprises an atomic layer deposition process.

Additional features and advantages will become apparent to a specialist upon reading the following detailed description and examining the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

• 1 veranschaulicht schematisch und beispielhaft einen Abschnitt einer vertikalen Projektion der Leistungshalbleitervorrichtung gemäß einer oder mehreren Ausführungsformen;
• 2 veranschaulicht schematisch und beispielhaft einen Abschnitt einer vertikalen Projektion einer Leistungshalbleitervorrichtung gemäß einer oder mehreren Ausführungsformen;
• 3 veranschaulicht schematisch und beispielhaft einen Abschnitt einer vertikalen Projektion einer Leistungshalbleitervorrichtung gemäß einer oder mehreren Ausführungsformen;
• 4 veranschaulicht schematisch und beispielhaft einen Abschnitt eines vertikalen Querschnitts einer Leistungshalbleitervorrichtung gemäß einer oder mehreren Ausführungsformen;
• 5 veranschaulicht schematisch und beispielhaft einen Abschnitt eines vertikalen Querschnitts einer Leistungshalbleitervorrichtung gemäß einer oder mehreren Ausführungsformen;
• 6 veranschaulicht schematisch und beispielhaft einen Abschnitt eines vertikalen Querschnitts einer Leistungshalbleitervorrichtung gemäß einer oder mehreren Ausführungsformen; und
• 7 veranschaulicht schematisch und beispielhaft einen Abschnitt eines vertikalen Querschnitts einer Leistungshalbleitervorrichtung gemäß einer oder mehreren Ausführungsformen.

The parts in the figures are not necessarily to scale; instead, the emphasis is on illustrating the principles of the invention. Furthermore, identical reference numerals in the figures denote corresponding parts. The following applies to the drawings:

• 1 schematically and exemplarily illustrates a section of a vertical projection of the power semiconductor device according to one or more embodiments;
• 2 schematically and exemplarily illustrates a section of a vertical projection of a power semiconductor device according to one or more embodiments;
• 3 schematically and exemplarily illustrates a section of a vertical projection of a power semiconductor device according to one or more embodiments;
• 4 schematically and exemplarily illustrates a section of a vertical cross-section of a power semiconductor device according to one or more embodiments;
• 5 schematically and exemplarily illustrates a section of a vertical cross-section of a power semiconductor device according to one or more embodiments;
• 6 schematically and exemplarily illustrates a section of a vertical cross-section of a power semiconductor device according to one or more embodiments; and
• 7 schematically and exemplarily illustrates a section of a vertical cross-section of a power semiconductor device according to one or more embodiments.

DETAILED DESCRIPTION

In this respect, directional terminology such as "above," "below," "below," "in front of," "behind," "back," "leading," "attached," "under," "over," etc., is used with reference to the orientation of the described figures. Because parts of embodiments can be positioned in a number of different orientations, the directional terminology is used for illustrative purposes.

Various embodiments will now be discussed in detail, one or more of which are illustrated in the figures. Each example is provided as an explanation and is not intended to limit the invention. Features illustrated or described as part of one embodiment can, for example, be applied to other embodiments or combined with them to obtain yet another embodiment. The drawings are not to scale and are for illustrative purposes only. For clarity, the same elements or manufacturing steps have been designated with the same reference numerals in the various drawings, unless otherwise indicated.

The term "horizontal," as used in this description, is intended to describe an orientation essentially parallel to a horizontal surface of a semiconductor substrate or structure. This could be, for example, the surface of a semiconductor wafer or die. Both the first lateral direction X and the second lateral direction Y mentioned below could, for example, be horizontal directions, with the first lateral direction X and the second lateral direction Y being horizontal. The lateral direction Y can be perpendicular to each other.

The term "vertical," as used in this description, is intended to describe an orientation that is essentially perpendicular to the horizontal surface, i.e., parallel to the normal of the semiconductor wafer's surface. The extension direction Z mentioned below, for example, can be an extension direction that is perpendicular to both the first lateral direction X and the second lateral direction Y.

In this description, n-doped is referred to as a "first conductivity type," whereas p-doped is referred to as a "second conductivity type." Alternatively, reverse doping relationships can be used, so that the first conductivity type can be p-doped and the second conductivity type n-doped.

Furthermore, the term "doping concentration" in this description can refer to an average doping concentration, a mean doping concentration, or a surface charge carrier concentration of a specific semiconductor region or zone. Thus, for example, a statement that a specific semiconductor region has a certain doping concentration that is comparatively higher or lower than the doping concentration of another semiconductor region can indicate that the corresponding mean doping concentrations of the semiconductor regions differ from one another.

In the context of this description, the terms "in ohmic contact," "in electrical contact," "in ohmic connection," and "electrically connected" are intended to describe the existence of a low-resistance electrical connection or current path between two regions, sections, zones, portions, or parts of a semiconductor device, or between different terminals of one or more devices, or between a terminal, metallization, or electrode and a portion or part of a semiconductor device. Furthermore, the term "in contact" in the context of this description is intended to describe the existence of a direct physical connection between two elements of the semiconductor device in question; for example, a junction between two elements in contact may not include any further intermediate element or the like.

Additionally, in the context of this description, the term "electrical isolation" is used in its generally accepted sense, unless otherwise specified, and thus describes a situation where two or more components are positioned separately from one another and there is no ohmic connection connecting these components. However, components that are electrically isolated from one another may still be coupled, for example, mechanically coupled and/or capacitively coupled and/or inductively coupled. To give an example, two electrodes of a capacitor may be electrically isolated from one another and may simultaneously be mechanically and capacitively coupled to one another, e.g., by means of insulation, such as a dielectric.

Specific embodiments described in this description relate to a power semiconductor device having a strip-cell or needle-cell configuration, such as a power semiconductor transistor, which can be used within a power converter or power supply. Thus, in one embodiment, the semiconductor device is configured to carry a load current that is to be supplied to a load and/or that is accordingly provided by a power supply. For example, the semiconductor device may comprise one or more active power unit cells, such as a monolithically integrated diode cell and/or a monolithically integrated transistor cell and/or a monolithically integrated IGBT cell and/or a monolithically integrated RC-IGBT cell and/or a monolithically integrated MOS-gated diode (MGD) cell and/or a monolithically integrated MOSFET cell and/or derivatives thereof. Such a diode cell and/or such transistor cells may be integrated within a power semiconductor module. Several such cells may constitute a cell array arranged with an active region of the power semiconductor device.

The term “power semiconductor device,” as used in this description, is intended to describe a semiconductor device on a single chip with high voltage blocking and/or high current carrying capabilities. In other words, such a power semiconductor device is designed to handle high currents, typically in the ampere range, e.g., up to several tens or hundreds of amperes or even up to several kA, and/or high voltages, typically above 100 V, typically 500 V and above, e.g., up to at least 1 kV, up to at least 3 kV. For example, the semiconductor device described below may be a semiconductor device having a striped cell configuration or a needle cell configuration and may be configured to serve as a power component in an application with to be used at low, medium and/or high voltage.

For example, the term "power semiconductor device" as used in this description does not refer to logic semiconductor devices used, for example, for storing data, calculating data and/or for other types of semiconductor-based data processing.

1 to 3 Each of the following schematically and exemplarily illustrates a section of a vertical projection of a power semiconductor device 1 according to some embodiments. The illustrated vertical projection is parallel to a plane defined by a first lateral direction X and a second lateral direction Y, and perpendicular to a vertical direction Z. The power semiconductor device 1 comprises a semiconductor body 10 with a lateral chip edge 109. Furthermore, the semiconductor body 10 includes an active region 106 configured to conduct a load current (e.g., substantially along the vertical direction Z), and an edge termination region 108 arranged laterally between the chip edge 109 and the active region 106. As in each of the 1 to 3 It can be seen that the active area 106 may be laterally surrounded by the boundary closure area 108,

For example, the active area 106 comprises one or more power cells 14, each of which extends at least partially into the semiconductor body 10. The present description is not limited to a specific type of configuration of the one or more power cells 14. Rather, the power cells 14 can have any configuration that is common for a power semiconductor device, e.g., a diode configuration, a thyristor configuration, a MOS-gated diode (MGD) configuration, a transistor configuration such as an IGBT configuration, an RC (reverse conducting) IGBT configuration, a MOSFET configuration, and/or a configuration derived from these. A person skilled in the art is familiar with these types of configurations. Accordingly, in 1-3 The power cells 14 are only schematically illustrated, as the exact configuration is not the main subject of this description.

In the exemplary and schematic 1-3 The transition between the active region 106 and the termination region 108 shows sharp corners. According to some embodiments, the corners can have rounded shapes, as indicated by the dashed lines.

For example, the one in 1 The configuration shown corresponds to a power diode configuration comprising a single power cell 14. In contrast, the configuration shown in 2 and 3 The illustrated configurations include, for example, semiconductor switch configurations (such as a MOSFET and/or IGBT configuration), where the power cells 14 can be configured to control a load current by switching the power semiconductor device 1 into a conducting or a blocking state. Such power cells 14 can, for example, include a control structure, such as a MOS control structure. As exemplified in 2 As illustrated, the power cells 14 can have a stripe configuration that extends, for example, through the entire active area 106 along the second lateral direction Y. In another embodiment, as in 3 To illustrate, the power cells 14 can have the cellular configuration, e.g. with a horizontal cross-section that has a square shape, a rectangular shape, a rectangular shape with rounded corners, a circular shape or an elliptical shape.

The one or more power cells 14, which may be contained in the active area 106 of the power semiconductor device 1, may be configured to selectively conduct a load current and block a load voltage depending on, for example, a switching state of the power semiconductor device 1 and/or a direction in which a current and/or a voltage is applied to the power semiconductor device 1.

For example, the at least one power cell 14 can be configured for a blocking voltage of at least 300 V, at least 500 V, at least 1000 V, at least 1500 V, at least 3000 V, or even more than 6000 V. Furthermore, the at least one power cell 14 can have a compensation structure, also known as a "superjunction" structure.

For example, to control one or more power cells 14, a control terminal (not illustrated) can be provided, which can be configured to transmit a control signal to a control electrode structure of the one or more power cells 14. For example, the control terminal can be a gate terminal. This allows the power semiconductor device 1 to be set to the conducting or blocking state. In one embodiment, such a control signal can be generated by applying a voltage between the control terminal and a first load terminal 11 (in 1 to 3 not shown, see 4 to 6 ) will be provided.

An edge termination structure 18 can be arranged between the chip edge 109, which can be created, for example, by wafer cutting, and the active region 106. In other words, an edge termination structure 18 can be arranged in and/or on the edge termination region 108. For example, the edge termination region 18 (in 1 to 3 not shown 6 ) the active region 106 completely. According to one embodiment, the edge termination structure 18 is not configured to conduct a load current, but instead is configured to ensure reliable blocking capability of the power semiconductor device 1. For example, the edge termination structure 18 comprises a junction termination extension (JTE) structure, a variation-of-lateral doping (VLD) structure 180 (see 6 ) and/or a field ring/field plate termination structure. A person skilled in the art is familiar with these types of edge termination structures.

4 to 7 Figure 1 schematically and exemplarily illustrates a section of a vertical cross-section of the power semiconductor device 1 according to some embodiments. The illustrated cross-sections are parallel to a plane defined by the first lateral direction X and the vertical direction Z, with each of the illustrated components also extending along the second lateral direction Y.

The sections in 4 to 7 are in any case located near the lateral chip edge 109 of the semiconductor body 10 and in particular comprise a vertical cross-section of the edge termination region 108. In addition, a part of the active region 106 adjacent to the edge region 108 is illustrated.

The semiconductor body 10 is coupled to both a first load terminal 11 and a second load terminal 12 of the power semiconductor device 1. The first load terminal 11 can be, for example, an anode terminal, an emitter terminal, or a source terminal, located, for example, on a front face 10-1 of the semiconductor body 10. The second load terminal 12 can be, for example, a cathode terminal, a collector terminal, or a drain terminal, located, for example, on a back face 10-2 of the semiconductor body 10.

The semiconductor body 10 comprises a drift region 100, which includes dopants of a first conductivity type (e.g., n-type). In one embodiment, the drift region 100 is an n ^- doped region. As in 4 to 7 As shown, the drift region 100 can extend into both the active region 106 and the edge termination region 108 of the power semiconductor device 1. Each of the one or more power cells 14 can encompass a portion of the drift region 100. Furthermore, each of the one or more power cells 14, which may be contained within the active region 106 of the power semiconductor device 1, can be configured to conduct a load current across the drift region 100 between the load terminals 11 and 12 and to block a reverse voltage applied between the terminals 11 and 12.

For example, in the 5 to 6 In the illustrated embodiments, a larger power cell 14 is provided, which can be configured as a power diode cell. For example, the power diode cells 14 comprise an anode region 102 of a second conductivity type (e.g., p-type), wherein the anode region 102 is arranged in contact with the first load terminal 11. Furthermore, a junction between the anode region 102 and the drift region 100 forms a pn junction 103, which is configured to block a reverse voltage between the first load terminal 11 and the second load terminal 12.

At the in 7 In the illustrated exemplary embodiment, the power semiconductor device 1 is a switching device, such as an IGBT or a MOSFET. The active region 106 comprises several power cells 14, each power cell 14 comprising a trench-gate structure 140. For example, the trench-gate structure 140 can be arranged in a strip configuration, as shown in 2 illustrated, or a cellular configuration (which, for example, has a square or rectangular shape in a horizontal cross-section), as in 3 The arrangement is illustrated. For example, each of the power cells 14 includes a control electrode 141 arranged within a trench, the control electrode 141 being configured to receive a control signal, such as a gate voltage, from a (not shown) control terminal of the power semiconductor device 1. For example, within each power cell 14, the control electrode 141 is electrically isolated from the first load terminal by means of an insulation block 143.

Furthermore, each of the cells 14 comprises a body region 102 of the second conductivity type (e.g., p-type) and at least one source region 104, which is arranged in contact with the first load terminal 11, wherein the body region 102 isolates the at least one source region 104 from the drift region 100. A junction between the body region 102 and the drift region 100 forms a pn junction 103, which is configured to block a reverse voltage applied in the forward direction between the first load terminal 11 and the second load terminal 11. The control electrode can be electrically isolated from both the source region 104, the body region 102, and the drift region 100 by an insulating structure 142 contained in the trench. For example, the control electrode 141 can be configured to include a transport channel, such as an n-channel, in the body region 102 between the source region 104 and the drift region 100, depending on the control signal, thereby enabling the conduction state of the power semiconductor device 1. Instead of the one in 7 The semiconductor device 1, as shown in the trench cells, can be equipped with (not shown) so-called planar power switching cells, wherein the gate electrode is located vertically above the semiconductor body 10. A person skilled in the art is familiar with the principles and variants of configurations of such power switching cells 14.

The semiconductor body 10 can further comprise a back-side emitter region 107 of the second conductivity type (e.g., p-type) arranged on the back side 10-2 in contact with the second load terminal 12. In this case, the power semiconductor device 1 can be configured as an IGBT. In another variant, where the power semiconductor device 1 is configured, e.g., as a MOSFET, such a back-side emitter region 107 can be arranged, as exemplified in 7 Illustrated, but missing.

Now, with attention to the boundary boundary area 108, the boundary boundary area 108 encompasses all in 4 to 7 The illustrated embodiments feature a semi-insulating layer 15 covering a portion of the front face 10-1 of the semiconductor 10. The semi-insulating layer 15 is characterized by an electrical conductivity that allows a certain lateral current flow between the first load terminal 11, or a corresponding control terminal on the front face of the power semiconductor device, and the chip edge 109. The current should be sufficient to prevent static charges in the semi-insulating layer 15 and to avoid excessive power losses in the semi-insulating layer 15 caused by the magnitude of the electric current and the voltage drop between the first load terminal 11 and the chip edge 109 or the second load terminal 12, respectively. The power losses in the semi-insulating layer 15 at full reverse voltage should not exceed a few hundred mW or a few tens of mW. A person skilled in the art can easily calculate the maximum permissible specific conductivity of the semi-insulating layer 15 for the designed voltage drop between the first load terminal 11 and the second load terminal 12 using Ohm's law and the geometric dimensions of the semi-insulating layer 15 (thickness, width, length).

In one embodiment, the semi-insulating layer 15 comprises at least one of the following: amorphous silicon (a-Si), semi-insulating polycrystalline silicon (SIPOS) and an electroactive material, such as diamond-like carbon (DLC) or hydrogen-containing amorphous carbon (a-C:H).

For example, the semi-insulating layer 15 can be electrically connected to both the first load connection structure 11 and the second load connection structure 12. For example, the semi-insulating layer 15 can be arranged in contact with the first load connection 11, as in each of the 4 to 7 This is illustrated. Furthermore, in one embodiment, the semi-insulating layer 15 can be arranged in contact with a channel stop electrode 13, which is located on the front face 10-1 of the semiconductor body 10 within the edge termination region 108, wherein the channel stop electrode 13 is electrically connected to the second load terminal 12. For example, an electrical connection between the channel stop electrode 13 and the second terminal 12 can be provided by means of an ohmic path along the chip edge 109. For example, such an ohmic path along the chip edge 109, which can be directed substantially along the chip edge 109 in the vertical direction z, can be generated during chip singulation, such as by sawing or laser cutting of the semiconductor body 10, whereby crystal defects may occur at the chip edge 109. For example, the channel stop electrode 13 can be in contact with and electrically connected to the doped channel stop region 130, e.g. B. of the second conductivity type, which may be provided within the semiconductor body 10, as in 6 This is illustrated. For example, the channel stopper electrode 13 and the doped channel stopper region 130 can be configured and arranged to prevent the formation of an inversion channel in the edge termination region 108 during operation of the power semiconductor device 1. A person skilled in the art is familiar with such types of channel stopper structures within an edge termination region of a power semiconductor device.

In an embodiment in which the semiconductor body 10 includes a doped channel stopper region 130 as described above, the semi-insulating layer 15 extends laterally along the entirety of the doped channel stopper region 130 and the channel stopper electrode 13, as shown in 6 This illustrates the point.

Furthermore, a first passivation layer 16 is in each case arranged on at least a portion of the semi-insulating layer 15. The first passivation layer 16 can be configured to prevent oxidation of the semi-insulating layer 15. For example, the first passivation layer 16 can comprise atoms capable of forming valence bonds with atoms of the semi-insulating layer 15, thereby preventing oxidation of the semi-insulating layer 15.

In one embodiment _, the first passivation layer 16 comprises a silicon-doped amorphous aluminum oxide ( _Al₂O₃ ). For example, the first passivation layer 16 can be formed by an atomic layer deposition (ALD) process. In other words, the formation of the first passivation layer 16 in a method for fabricating the power semiconductor device 1 according to the invention can include an atomic layer deposition (ALD) process, such as the atomic layer deposition of aluminum oxide. For example, a silicon-comprising precursor can be used in such an ALD process.

In one embodiment as in 5 As illustrated, the first passivation layer 16 comprises an aluminum oxide layer, with an additional silicon nitride ( _Si₃N₄ ) layer 19 (also referred to as SNIT layer) arranged on top of the aluminum oxide layer 16. For example _, doping the aluminum oxide layer 16 with silicon can be achieved by means of the silicon nitride layer 19 arranged on top of it. For example, the silicon nitride layer 19 can be produced by means of a PECVD process (PECVD: Plasma Enhanced Chemical Vapor Deposition).

For example, the thickness of the first passivation layer 16, or, if a silicon nitride layer 19 is arranged on the first passivation layer 16, the total thickness of the first passivation layer 16 and the silicon nitride layer 19, can be in the range of 1 nm to 60 nm, such as 1 nm to 40 nm, 1 nm to 10 nm, 3 nm to 9 nm, 5 nm to 7 nm, e.g., 6 nm. For example, the first passivation layer 16, possibly in combination with a silicon nitride layer 19 arranged on it, can thus be easily bonded. Accordingly, in a method for fabricating such a power semiconductor device 1, it may not be necessary to provide a structured formation of the first passivation layer 16 (possibly in combination with the silicon nitride layer 19). Instead, the layers 16, 19 can be formed uniformly, i.e., even in areas that are not structurally sound. B. by wire bonding or tape bonding in a later process step or by other means. Furthermore, the thickness of the first passivation layer 16 (and optionally the silicon nitride layer 19) can allow for simple chip singulation, e.g. by sawing or laser cutting. Accordingly, there may be no need to structure the formation of layers 16, 19 near the chip edge 109.

According to one embodiment, forming the first passivation layer 16 in a method for manufacturing a power semiconductor device 1 according to the invention comprises forming a layer of amorphous aluminum oxide and subsequently doping the amorphous aluminum oxide with silicon by means of a process that supplies silicon ions to the amorphous aluminum oxide. For example, the doping of the amorphous aluminum oxide with silicon can be achieved by at least one of the following processes: plasma-enhanced chemical vapor deposition (PECVD) of a silicon nitride layer (SNIT layer) on the amorphous aluminum oxide layer; plasma-enhanced chemical vapor deposition (PECVD) of silicon oxide on the amorphous aluminum oxide layer; pulsed laser deposition (PLD) of silicon on the amorphous aluminum oxide layer; Exposure of the amorphous aluminum oxide layer to a silicon-containing plasma, wherein a potential difference between the plasma and a wafer with at least one of the power semiconductor devices 1 accelerates silicon ions from the plasma towards the wafer (so-called plasma doping); and implantation of silicon into the amorphous aluminum oxide layer. For example, the implantation can be carried out as a beamline implantation with a suitable (i.e., relatively low) energy.

In one embodiment, both the semi-insulating layer 15 and the first passivation layer 16 have a first common lateral extent X1 with the channel stopper electrode 13. In other words, there can be an overlap X1 between the channel stopper electrode 13 and both the semi-insulating layer 15 and the first passivation layer 16, whereby the overlap between the channel stopper electrode 13 and the semi-insulating layer 15 on the one hand and the overlap between the channel stopper electrode 13 and the first passivation layer 16 on the other hand need not be of the same extent. That is, in contrast to, for example, the embodiments of 4 to 7 The overlap between the channel stopper electrode 13 and the semi-insulating layer 15 can extend further along, for example, the first lateral direction X than the overlap between the The channel stopper electrode 13 and the first passivation layer 16 extend. In another embodiment, the overlap between the channel stopper electrode 13 and the first passivation layer 16 can extend further along, for example, the first lateral direction X than the overlap between the channel stopper electrode 13 and the first semi-insulating layer 15. In either case, there can be a first common lateral extension direction X1 of both the semi-insulating layer 15 and the first passivation layer 16 with the channel stopper electrode 13. For example, the first common lateral extension area X1 can be greater than the distance between the outer ends (i.e., ends pointing towards the chip edge 109) of the semi-insulating layer 15 and the first passivation layer 16, as measured along the first lateral direction X. For example, the distance between the outer ends of the semi-insulating layer 15 and the first passivation layer 16, as measured along the first lateral direction X, may be less than three times the thickness of the semi-insulating layer 15 and/or the first passivation layer 16.

In one embodiment, both the semi-insulating layer 15 and the first passivation layer 16 have a second common lateral extent X2 with the first load connection structure 11. Similar to what is described above with regard to the first common extent X1, it may not necessarily be the case that an overlap between the first load connection 11 and the semi-insulating layer 15 has the same extent (e.g., along the first lateral direction X) as an overlap between the first load connection 11 and the first passivation layer 16. That is, unlike, for example, the exemplary illustration in 4 to 7 In one embodiment, the overlap between the first load connection 11 and the semi-insulating layer 15 can be greater than the overlap between the first load connection 11 and the first passivation layer 16. In another embodiment, the overlap between the first load connection 11 and the first passivation layer 16 can be greater than the overlap between the first load connection 11 and the first semi-insulating layer 15. In either case, there can be a second common lateral extension direction X2 of both the semi-insulating layer 15 and the first passivation layer 16 with the first load connection 11. For example, the second common lateral extension area X2 can be greater than the distance between the inner ends (i.e., ends facing the active region 106) of the semi-insulating layer 15 and the first passivation layer 16, as measured along the first lateral direction X. For example, the distance between the inner ends of the semi-insulating layer 15 and the first passivation layer 16, as measured along the first lateral direction X, may be less than three times the thickness of the semi-insulating layer 15 and/or the first passivation layer 16.

For example, both the semi-insulating layer 15 and the first passivation layer 16 can be formed by a structured deposition process or by structuring after deposition using the same mask.

In one embodiment, the power semiconductor device 1 further comprises an edge termination structure 18 arranged in and/or on the edge termination region 108, wherein the edge termination structure 18 may comprise at least one of the following: a junction termination extension (JTE) structure, a variation lateral doping (VLD) structure 180, and a field ring/field plate termination structure. For example, in the 6 In the embodiment shown, an edge termination structure 18 is provided, comprising a variation lateral doping (VLD) configuration 180. For example, the VLD structure 180 comprises a second-conductivity-type (e.g., p-type) semiconductor region 180 located on the front face 10-1 within the semiconductor body 10. For example, a dopant concentration of the semiconductor region 180 (e.g., a second-conductivity-type dopant concentration, such as p-type) varies in the first lateral direction X. For example, the dopant concentration can decrease along the first lateral direction X, e.g., continuously and/or in a step-like manner. The VLD structure 180 can have a common lateral extent with the semi-insulating layer 15 in the first lateral direction X. For example, the semi-insulating layer 15 can be arranged in contact with at least part of the VLD termination structure 180, as exemplified in 6 This illustrates the point.

In one embodiment, the semiconductor device 1 further comprises a second passivation layer 17 arranged on top of the first passivation layer 16. For example, the second passivation layer 17 comprises polyimide and/or spin-on silicone (SOS). The polyimide and/or spin-on silicone may also be provided with a photoactive substance. Accordingly, it may be possible to expose and develop the polyimide and/or spin-on silicone layer similarly to a photoresist. Therefore, it may not be necessary to provide a dedicated mask for structuring the second passivation layer 17.

In a further embodiment, the second passivation layer 17 may further comprise, for example, at least one of the following: a glass, such as spin-on glass; an inorganic insulator, such as oxide, nitride or oxynitride (e.g. deposited by PECVD); an epoxy resin; or a stack of layers formed by at least two of the aforementioned species.

Embodiments of a method for fabricating a power semiconductor device correspond to the embodiments of the power semiconductor device 1 described above with reference to the other drawings. Therefore, for example, the features of the embodiments of the power semiconductor devices described above with reference to the other drawings can be achieved by appropriately implementing the method. Embodiments of a method for fabricating a power semiconductor device may include forming the respective structures arranged in/on the semiconductor body 10 as described above.

Previously, embodiments relating to a power semiconductor device, such as a diode, a MOSFET, or an IGBT, and corresponding processing methods were explained. These devices are based, for example, on silicon (Si). Accordingly, a monocrystalline semiconductor region or layer, e.g., the semiconductor body 10 and its regions/zones 100, 102, 104, 107, and 130, can be a monocrystalline Si region or Si layer. In other embodiments, polycrystalline or amorphous silicon can be used.

However, it is understood that the semiconductor body 10 and its doped areas/zones can be made of any semiconductor material suitable for manufacturing a power diode. Examples of such materials include elemental semiconductor materials, such as silicon (Si) or germanium (Ge); group IV compound semiconductor materials, such as silicon carbide (SiC) or silicon germanium (SiGe); binary, ternary, or quaternary III-V semiconductor materials, such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AIGaN), aluminum indium nitride (AllnN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN), or indium gallium arsenide phosphide (InGaAsP); and binary or ternary II-VI semiconductor materials, such as cadmium telluride (CdTe) and mercury cadmium telluride. (HgCdTe), to name just a few. The semiconductor materials mentioned above are also referred to as "homo-junction semiconductor materials." When two different semiconductor materials are combined, a hetero-junction semiconductor material is formed. Examples of hetero-junction semiconductor materials include aluminum gallium nitride (AlGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-gallium nitride (GaN), aluminum gallium nitride (AlGaN)-gallium nitride (GaN), indium gallium nitride (InGaN)-aluminum gallium nitride (AlGaN), silicon-silicon carbide (Si _{_x}C_{_1-x} ), and silicon-SiGe hetero-junction semiconductor materials. Currently, Si, SiC, GaAs and GaN materials are mainly used for power semiconductor device applications.

Spatially relative terms such as "under," "below," "above," "lower," "above," "upper," and the like are used for the sake of simplicity to explain the positioning of one element relative to another. These terms are intended to encompass various orientations of the corresponding device, in addition to those shown in the figures. Furthermore, terms such as "first," "second," and the like are also used to describe different elements, areas, sections, etc., and these are likewise not intended to be limiting. Throughout the description, identical terms refer to identical elements.

As used here, the terms “indicating”, “containing”, “encompassing”, “showing”, and the like are open expressions that indicate the presence of the specified elements or features, but do not exclude any additional elements or features.

Claims (15)

Power semiconductor device (1) comprising: - a semiconductor body (10) having: - an active region (106) configured to conduct a load current, - a chip edge (109) terminating the semiconductor body (10) laterally, and - an edge termination region (108) arranged laterally between the chip edge (109) and the active region (106); - a semi-insulating layer (15) covering at least a portion of the semiconductor body (10) within the edge termination region (108); and - a first passivation layer (16) arranged on at least a portion of the semi-insulating layer (15); wherein: - the first passivation layer (16) comprises silicon-doped amorphous aluminum oxide; - the thickness of the first passivation layer (16) or, if a silicon nitride layer (19) is arranged on the first passivation layer (16), the total thickness of the first passivation layer (16) and the silicon nitride layer (19) is in the range of 1 nm to 60 nm; - the first passivation layer (16) and/or the silicon nitride layer (19) are not structured. Power semiconductor device (1) according to Claim 1 , wherein the first passivation layer (16) is configured to prevent oxidation of the semi-insulating layer (15) by providing atoms that are able to form valence bonds with atoms of the semi-insulating layer (15). Power semiconductor device (1) according to one of the preceding claims, wherein the semiconductor body (10) has a front side (10-1) coupled to a first load connection structure (11) and a back side (10-2) coupled to a second load connection structure (12), and wherein the semi-insulating layer (15) is arranged on the front side (10-1) and is electrically connected to the first load connection structure (11) and the second load connection structure (12). Power semiconductor device (1) according to one of the preceding claims, wherein the semi-insulating layer (15) comprises at least one of the following: amorphous silicon, semi-insulating polycrystalline silicon, diamond-like carbon and hydrogen-containing amorphous carbon. Power semiconductor device (1) according to one of the preceding claims, wherein the semi-insulating layer (15) is arranged in contact with a channel stopper electrode (13) which is electrically connected to the second load terminal (12). Power semiconductor device (1) according to Claim 5 , wherein both the semi-insulating layer (15) and the first passivation layer (16) have a first common lateral extension area (X1) with the channel stopper electrode (13). Power semiconductor device (1) according to one of the preceding claims, wherein the semi-insulating layer (15) extends laterally along the entirety of both a doped channel stopper region (130) provided within the semiconductor body (10) and the channel stopper electrode (13). Power semiconductor device (1) according to Claim 3 , wherein the semi-insulating layer (15) is arranged in contact with at least a part of the first load connection structure (11). Power semiconductor device (1) according to Claim 8 , wherein both the semi-insulating layer (15) and the first passivation layer (16) have a second common lateral expansion area (X2) with the first load connection structure (11). Power semiconductor device (1) according to one of the preceding claims, wherein the first passivation layer (16) comprises an aluminum oxide layer and wherein the silicon nitride layer (19) is arranged on the aluminum oxide layer. Power semiconductor device (1) according to one of the preceding claims, further comprising an edge termination structure (18) arranged in and/or on the edge termination region (108), wherein the edge termination structure (18) comprises at least one of the following: a junction termination extension structure, a variation lateral doping structure (180) and a field ring/field plate termination structure. Power semiconductor device (1) according to one of the preceding claims, further comprising a second passivation layer (17) arranged on the first passivation layer (16), wherein the second passivation layer (17) comprises a polyimide, a spin-on silicone, a glass, an oxide, a nitride, an oxynitride and/or an epoxy resin. Method for fabricating a power semiconductor device (1), in which the power semiconductor device (1) comprises a semiconductor body (10) having: - an active region (106) configured to conduct a load current, - a chip edge (109) that laterally terminates the semiconductor body (10), and - an edge termination region (108) arranged laterally between the chip edge (109) and the active region (106); and wherein the method comprises: - forming a semi-insulating layer (15) on at least a portion of the semiconductor body (10) within the edge termination region (108); and - forming a first passivation layer (16) on at least a portion of the semi-insulating layer (15); in which the first passivation layer (16) comprises silicon-doped amorphous aluminum oxide; and the formation of the first passivation layer (16) comprises an atomic layer deposition of aluminum oxide; and wherein a precursor comprising silicon is used in the atomic layer deposition process. Procedure according to Claim 13 , wherein the formation of the first passivation layer (16) comprises forming a layer of amorphous aluminum oxide and subsequently doping the amorphous aluminum oxide with silicon by means of at least one of the following processes: - plasma-assisted chemical vapor deposition of silicon nitride on the layer of amorphous aluminum oxide; - plasma-assisted chemical vapor deposition of silicon oxide on the layer of amorphous aluminum oxide; - pulsed laser deposition of silicon on the layer of amorphous aluminum oxide; - exposure of the layer of amorphous aluminum oxide to a silicon-containing plasma; - implantation of silicon into the layer of amorphous aluminum oxide. Procedure according to Claim 13 or 14 , wherein the first passivation layer (16) is configured to prevent oxidation of the semi-insulating layer (15) by providing atoms that are able to form valence bonds with atoms of the semi-insulating layer (15).