DE102018117373B4 - Synchronizing adaptive filter switching and channel equalization in full duplex (FDX) cable modems - Google Patents

Abstract

Processor in a cable modem with an analog front end (AFE), a PHY and a MAC, operating in full duplex (FDX) mode and having a switchable filter block and variable equalizer coefficients in the PHY, the processor being configured to:Receive a command through the media access control (MAC) from the cable modem, the received command comprising a change in a resource block allocation (RBA), the RBA change comprising changing a first allocation of downstream and upstream transmission channels to a second, different allocation of downstream and upstream transmission channels, wherein changing the association includes changing a channel from a downstream transmission direction to an upstream transmission direction or vice versa; andtriggering the MAC to send a filter switching control signal to the analog front end based on the received command to;causing the AFE to switch a filter path in response to the filter switching control signal and insert a filter switching mark into one or more received samples; andcausing the PHY to change its variable equalizer coefficients to reflect current calibration data for the switched filter path in synchronization with receiving the samples including the filter switching mark from the AFE.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 USC §119 (e) to the pending U.S. patent application serial number 62/547,498, filed August 18, 2017 by the same inventors and bearing the same title as the present application and which is incorporated herein in its entirety Reference is made to it.

AREA

Embodiments of the present invention generally relate to, but are not limited to, communications architectures and methods for handling full duplex (FDX) cable modem signals with a receiver's switched filtering and equalization equalization coefficients based on the selected filter.

BACKGROUND

In certain non-limiting embodiments, cable communication systems are those such as those defined by Data over Cable Service Interface Specification (DOCSIS) 3.1 FDX, although the inventive embodiments are not limited to specific protocols defined. DOCSIS 3.1 FDX specifications impose additional filter design requirements that did not exist in previous versions of the standard.

DOCSIS 3.1 FDX enables dynamic resource block allocation (RBA) for downlink and uplink links in the FDX band. This means that a receiving channel can be changed and assigned to broadcast and vice versa. To cope with the changed electrical characteristics due to filter switching for RBA changes, it may be desirable to change the digital equalization for the channel response (i.e., adjust equalizer coefficients) according to the changes in the filter configuration.

Just as an example, consider a rudimentary case of a system that uses three resource block allocations (RBAs), where, for example, two RBAs, also referred to herein as "channels", are allocated downstream and one RBA is allocated upstream. For example, if the network changes the resource block allocation of the cable modem tuner to one downlink channel and two uplink channels, i.e. H. If one of the downlink channel assignments is changed to an uplink channel, the filtering at the receiver changes, as well as likely the need to adjust the equalizer coefficients to match electrical changes due to an alternative filter input. Since the downlink receives frequently most of the time, filter switching due to a change in resource allocation is likely to occur while the CM is receiving real-time data. Due to filter construction and matching, the impedance and frequency response seen at the tuner input after filtering will change with the RBA changes. This can lead to errors in signal demodulation because the change can affect the amplitude and phase of the signal at the analog-to-digital control (ADC) input if compensations for these changes are not made at the same time or near simultaneous time.

If the update of the equalization coefficients is not timed well to coincide with the filter switching, then there will most likely be a period of time in which inefficient or incorrect equalizer coefficients are used, thereby degrading the receiver's performance in receiving the downlink channel, including possible data loss. It would therefore be desirable to have a method/process and/or architecture to provide synchronization of filter switching and equalizer coefficient updates due to changes in the RBAs occurring during a DOCSIS 3.1 FDX operation or similar uplink/downlink -Communication systems that use FDX filter switching may be necessary.

This need is satisfied by the subject matter of the independent patent claims.

In the publication US 6791995 B1 entitled "Multichannel, multimode DOCSIS headend receiver" describes: A multichannel, mixed-mode cable modem termination system receiver capable of receiving multiple channels of digital data transmitted over one or more hybrid fiber coaxial cable systems with each of the channels being either single-mode or mixed-mode. Mixed-mode channels are time-division multiplexed and have overlapping bandwidth, and each subchannel of a mixed-mode channel may have a different center frequency, symbol rate, and/or multiplexing type.

The publication US 2003058959 A1 entitled “Combined digital adaptive pre-distorter and pre-equalizer system for modems in link hopping radio networks” describes the following. A method for a combined adaptive digital pre-distorter and pre-equalizer device in single and/or multiple link hopping radio systems, which includes hopping between a plurality of radio links to transmit variable length radio signal bursts on the plurality of radio links.

In the publication US 2002061012 A1 entitled “Cable modern with voice processing capability” describes the following. A network gateway is configured to facilitate bidirectional communication between a series of near-end data and telephony devices and far-end data termination devices over a hybrid fiber coaxial network and cable modem termination system. The described network gateway combines a QAM receiver, a transmitter, a DOCSIS MAC, a CPU, a voice and audio processor, a voice synchronizer, an Ethernet MAC and a USB controller to ensure high performance and robust operation guarantee.

In the publication DE 600 38 251 T2 entitled “Cable modern with voice processing capability” describes the following. A network gateway is configured to facilitate bidirectional online and offline communications between a series of near-end data and telephony equipment with far-end data termination equipment over a hybrid fiber-coaxial network and cable modem termination system. The described network gateway combines a QAM receiver, a transmitter, a DOCSIS MAC, a CPU, a voice and audio processor, a voice synchronizer, an Ethernet MAC and a USB controller to ensure high performance and robust operation guarantee.

BRIEF DESCRIPTION OF THE DRAWING FIGURES

• 1 ein einfaches Netzwerkdiagramm, in dem Ausführungsbeispiele der Erfindung benutzt werden können;
• 2 ein Funktionsblockdiagramm einer Kommunikationsvorrichtung gemäß verschiedenen Ausführungsformen der Erfindung;
• 3 einen Prozess zum Synchronisieren von Filteränderungen und Kanalentzerrerkoeffizienten gemäß einer oder mehreren Ausführungsformen der Erfindung;
• 4 ein Funktionsblockdiagramm einer Kommunikationsvorrichtung gemäß einer alternativen Ausführungsform;
• 5 ein anderes Verfahren zum Synchronisieren von Filteränderungen und Entzerrerkoeffizient-Aktualisierungen in einem FDX-System gemäß den erfinderischen Ausführungsformen;
• 6 ein beispielhaftes Rahmensynchronisationsbeispiel zum Synchronisieren von Filteränderungen und Entzerrerkoeffizienten gemäß einigen Ausführungsformen;
• 7 ein beispielhaftes Zeitdiagramm für Signalisierungs- und Schaltungsinteraktionen zwischen verschiedenen Elementen eines FDX-Kabelmodemsystems gemäß verschiedenen Ausführungsformen; und
• 8 ein beispielhaftes Funktionsblockdiagramm eines Modems, das ein analoges Frontend und einen Empfänger einer oder mehrerer Ausführungsformen der Erfindung aufweist.

Certain circuits, logic operations, devices and/or methods are described, by way of non-limiting example only, with reference to the accompanying drawing figures, in which:

• 1 a simple network diagram in which embodiments of the invention can be used;
• 2 a functional block diagram of a communication device according to various embodiments of the invention;
• 3 a process for synchronizing filter changes and channel equalizer coefficients according to one or more embodiments of the invention;
• 4 a functional block diagram of a communication device according to an alternative embodiment;
• 5 another method for synchronizing filter changes and equalizer coefficient updates in an FDX system according to the inventive embodiments;
• 6 an exemplary frame synchronization example for synchronizing filter changes and equalizer coefficients according to some embodiments;
• 7 an exemplary timing diagram for signaling and circuit interactions between various elements of an FDX cable modem system according to various embodiments; and
• 8th an exemplary functional block diagram of a modem having an analog front end and a receiver of one or more embodiments of the invention.

DETAILED DESCRIPTION OF THE INVENTION

Although embodiments of the invention may reference cable modems and related specifications, such as DOCSIS® 3.1 from Cable Television Laboratories, Inc., the filter switching and adaptive coefficient equalization techniques of the inventive embodiments are not limited thereto and may be used in any protocols, applications or architectures , in which similar principles are applied and their use can provide similar benefits. Therefore, the specific description herein is provided only in the context of an example implementation, and the claims contained therein are in no way limited thereto.

As in 1 Shown below is a basic network 100 with a network node 110, such as a cable provider cable modem termination system (CMTS) or an Internet service provider that provides web access via an Internet Protocol (IP) interface to end user devices 122, 124, including personal computers , laptops, wireless access points over a network connection 112, such as a combination of an optical fiber from a service provider headend to an exchange terminal, converted from optical to electrical signals and delivered to the end user, generally over a coaxial cable, although the inventive embodiments include are in no way limited to a particular network configuration. To receive, demodulate and access signals from network node 110 in the downlink Via connection 112, the end user terminals 122, 124, 126 may require customer premise equipment (CPE) such as a cable modem (CM) 115.

A cable modem termination system or CMTS 100 is a piece of equipment typically located at the head end or hub end of a cable company and used to provide high speed data services such as cable Internet or Voice over Internet Protocol to cable subscribers via their CM .

Referring to 2 A functional block diagram of a cable modem (CM) tuner 200 according to one or more inventive embodiments using DOCSIS 3.1 full duplex (FDX) will now be explained.

In certain embodiments, the cable modem transceiver 200 may perform full duplex (FDX) communication with a network provider. The transceiver 200 may include a high speed serial interface (HSIF) 232 for sending and receiving digital data between an analog front end (AFE) 205 and a digital radio 230 with a physical (PHY) layer demodulator 235 and media access layer (MAC) processing functionality 238 for Use decoding/encoding data between the customer premises device and the network provider.

As an example, in some embodiments, the digital radio 230 may be implemented as a system on a chip (SoC) that provides networking functions including media access control (MAC) and PHY layer functionality, e.g. B. demodulation and decoding, packet construction/destruction, etc. The transceiver 200 may further include an analog front end (AFE) 205, which in certain embodiments may include a full spectrum sampling tuner that includes a low noise amplifier (LNA)/automatic gain control (AGC), analog to digital conversion (ADC), Channelizer and, if desired, a high-speed serial interface HSIF integrated in the front end. The analog I/O side of the AFE 205 may include a block of switchable diplex filters 202, collectively referred to as a “tuner” in some portions of this disclosure.

In certain embodiments, filter block 202 includes a filter switching module with a feedback/input port (logical or physical) to enable selection of which filter paths are active based on received signaling. The digital radio includes a filter compensation equalizer 240 in front of the demodulator to adjust the equalizer coefficients in a synchronous manner to the filter switching to reduce the above-mentioned receiver problems due to changes in resource block allocation. In this configuration, when a resource allocation is changed by the CMTS, the MAC 238 may send a filter switching control signal 251 to the PHY 235, which in turn sends a filter switching control signal 252 to the filter block 202 to effect the filter path change.

A communication method according to certain embodiments is described with reference to 3 based on the in 2 Function block architecture shown shown. An incoming signal is sent to the cable modem via a coaxial connector, e.g. an F-connector, and is routed to one of the filter paths corresponding to the current FDX resource allocation allocations specified by the network, e.g. B. Designated path of the switchable filter according to the current resource block allocation. The filtered signal is then sampled, digitized and digitally down-converted. The samples (I/Q) are then transmitted to the receiver PHY/demodulator 230 via a high speed serial interface (HSIF) 232 using one or more lanes and a dedicated frame structure/protocol, although the inventive embodiments do not apply to the HSIF described herein are limited.

The block of switchable filters 202 is set to a specific filter (also commonly referred to herein as a “filter path” or “filter configuration”) based on a filter switching control signal (FSCS 252); 2 . In various embodiments, a first FSCS 251 is received from the cable modem MAC processor 238 based on resource block allocation (RBA) instructions provided by the CMTS (cable modem termination system). That is, the MAC layer sends 315 the filter switching control signal 251 to the PHY according to received commands from the network regarding RBA changes ( 3 ; 305 , 310 ).

Although not necessary, this disclosure assumes that the equalizer coefficients that should be used with each RBA (and therefore each possible filter switching configuration) are, e.g. B. known from factory marking/calibration or field calibration, which is referred to as “calibration data”. If switching of the equalizer coefficients occurs due to RBA changes, there may be a need to compensate the coefficients due to temperature changes, etc. These setting calculations do not affect time synchronization, but should the time at which the new RBA equalizer coefficients are loaded to minimize the time of using the coefficients, which may be imprecise.

The RBA change is typically controlled by commands from the CMTS 305. The CMTS messages are at the MAC layer, so the MAC subsystem is aware of the channel configuration change 310. The MAC layer may or may not be tightly coupled to the timing of the tuner system. Therefore, a cable modem using DOCSIS 3.1 FDX or comparable protocols may be given a "window of opportunity" by the CMTS to change the filters used, during which the resource block generally does not receive on the downlink and does not transmit on the uplink. In general, balancing the response characteristics of the physical channel and the current temperature, i.e. H. selecting or determining equalization coefficients applied at the PHY layer, which is highly synchronized compared to the MAC layer functionality.

An example process and the order of events from RBA that initiate switchable filtering is as follows:

The MAC layer receives 305 a channel configuration change instruction from the network provisioning entity. The cable modem's MAC generates its own filter switching control signal and sends 315 this to the PHY to reconfigure the FDX filter within the window of opportunity. During this window, the PHY must identify 320 any required changes in the equalizer coefficients to compensate for RBA changes and, if desired, adjust the coefficients for changes in platform temperature. In certain embodiments, the PHY also sends a filter switching control signal to execute the block of switchable filters. In the in 2 In the embodiment shown, this PHY sends the filter switching control signal to the filter block (202) and to the AFE (205). In other embodiments, the filter switching control signal is sent from the PHY of the digital radio to the AFE, and the AFE may signal the filter block to change its configuration 325. Various alternative signaling options for communicating a filter path change from the MAC may be based on the particular architecture and the used System construction can be made without deviating from the scope of the inventive embodiments.

In most cases the filter switching will have some "switching delay" and a "transient" response time until the response is settled into its steady state. In certain embodiments, adjusting or changing the equalizer coefficients to match the filter path change (referred to herein as “synchronizing” or “coordinating”) may be near-immediate or delayed by a predefined time period. During these stages, the ADC in the AFE continues to sample the input received from the network and performs digital signal processing. The processed data is then framed and sent to the demodulator via HSIF (Note: this path may also have some buffers/FIFO or other functional circuitry not shown because they are considered arbitrary). This allows marking 327 the point in time in the data at which a coefficient change should be made by determining the sampled data via HSIF for new samples filtered with the updated filter path. At 330, the marked I/Q data samples filtered with the new FDX configuration received at the digital radio allow the equalizer coefficients to be changed from those selected at step 320.

According to certain inventive embodiments, the synchronization of the timing of the coefficient change in PHY until the arrival of the relevant samples at the PHY using a specific display format from the tuner is now referred to 4 to 7 explained.

4 shows a functional block diagram of various embodiments of a cable modem transceiver 400 that includes a switched filter block 402, an analog front end (AFE) 405 in communication with a digital radio 430 through a high speed serial interface (HSIF) 432, similar to the earlier embodiments. It should be noted that in some cases herein the filter block AFE and the side of the HSIF may be referred to collectively as a "tuner", although they are in no way limited by such reference. In this embodiment, there is a filter switching control signal 440 from the MAC 438 to the AFE 405. The AFE 405 uses MAC signaling 440 to control the switching filter block 402.

In operation, referring to 5 , the transceiver begins in a steady state 505 and when the resource block allocation (RBA) command from the CMTS is received 510 by the MAC subsystem, instead of controlling the filter switch directly, 515 the MAC forwards the switch control command to the AFE or the tuner, either through general purpose input/output (GPIO) lines or through a control interface, depending on the discretion of the system architect. The AFE knows the exact time at which the switch command is issued on the switch control lines and "marks" 520 the sample (or a small group/range of samples) with a flag (e.g. a binary mark or, for example, with the specific filter configuration identifier) or another similar mechanism. The tuner then propagates 530 this mark (referred to herein as the “synchronization filter channel mark”) along with the sample or group of samples during digital signal processing. This allows the location or a reference point of the first sample(s) affected by the filter path change to be known.

When the samples, which may be true spectrum samples or complex I/Q channel samples, are sent to the PHY over the high-speed interface, the HSIF frame containing the marked sample carries an indication that allows the PHY to display the marked sample to recognize. When the demodulator receives 535 the marked sample, it can change the coefficients from that sample and further, and synchronization is achieved without decreasing receiver performance or losing data. In some embodiments, the demodulator may adjust the coefficient changes 525 from the pre-stored calibration memory or table 526 and, if desired, modify them through the sensor input 527, such as for thermal conditions.

In certain embodiments, it may be possible to interpolate or even characterize the response during the transition in addition to the known response at steady states. Depending on the signal processing implementation, a single labeled time domain spectrum sample may later be represented by a group of I/Q samples, possibly on a variety of channels.

Referring to 6 The samples may be transmitted from the AFE tuner to PHY over an HSIF interface using a frame structure 600 as shown, which frames the sample data and optionally additional control data.

In some non-limiting embodiments, the frame structure 600 may include a control message 610, which may include a control word, which may include: a control word ID (for alignment between PHY and/or MAC processing and the AFE), control message type, and control word data, where the data can depend on the message type. in the event of a filter change, the frame has a filter switch scan mark 612. In some embodiments, data could include the identifier 614 of the filter configuration used and the pointer 616 to the first marked sample within the frame. Various combinations and alternative message formats are also contemplated, and the inventive embodiments are not limited to any particular format or sequence.

For example, other considerations for one of ordinary skill in the art may include whether or not the control messages appear in each frame; the number of bits allocated to different parts of the control messaging; whether the size in bits of the control messages can be constant or not. The specific designs or optimal filter switching timing decision may be implementation dependent.

7 shows an example timing sequence 700 for the interaction between the PHY 735 and the MAC 738. The sequence 700 shows an example from the point at which the CMTS command to change the filter path/RBA allocation is received to the end point during the window of opportunity , where the coefficient change should have been made. These include filter switching, marking samples by the tuner during HSIF framing of data, and receiving the data during PHY HSIF deframing.

The above description of the architecture and processing for the digital radio may be implemented as, although not limited to, a system on a chip (SoC) receiver for cable modems using DOCSIS 3.1 Hybrid Fiber Coax FDX standards. Specific hardware and software implementations for functional block filter circuit synchronization elements discussed herein may include designs in application specific integrated circuits (ASICs), microcontrollers, programmable logic arrays, and/or as software/firmware for performing the processes described herein. In one embodiment, the filter switching signal, synchronization, and messaging may be programmed into software instructions and executed, or caused to occur in operation, by the processor or central processing unit (CPU) attached to the hardware demodulator.

Referring to 8th can be an example functional block diagram of a modem 800 for filter switching and time synchronization equalization coefficients, a receive interface 802 configured to receive a wired or wireless signal in the modem, a downconverter/demodulator/decode circuit 805-PHY having the capabilities described herein, and a modulator/upconverter circuit 818 for sending signals upstream over any type of desired PHY layer protocols.

In certain embodiments, the modem 800 may further provide various other functional elements such as the communications management circuitry 810 for constructing or deconstructing the packaging, framing, flow control management, and channel encoding/decoding of incoming or outgoing communication protocols for unidirectional or bidirectional data communication with the PHY layer or higher layer levels of the OSI communications model, a processor/memory 812 designed to control or provide processing/storage for various other functional elements of the modem 800, as desired. Further, the modem 800 may include security functionality 816 and client/user interface functionality 814, such as 10/100 GB based Ethernet PHY/MAC processing and respective interface(s) for providing user TCP/IP layer interface connectivity. It is understood that the modem 800 is only a representative functional example and various additional functionalities may be included as desired or those functionalities shown may be omitted if not needed or desired, as would be known to one skilled in the art. Thus, the specific example illustrated and described is not intended to limit the embodiments of the invention in any way.

DOCSIS 3.1 FDX was developed by CableLabs and partners to increase the multi-gigabit data era on existing hybrid fiber-coax (HFC) networks through improved spectral efficiency. Those skilled in the art would recognize modifications and substitutions of the elements, components and circuits described and possible herein, and the invention is in no way limited by the specific examples in the detailed description, but rather by the appended claims.

EXAMPLES OF EMBODIMENTS:

A first embodiment includes a cable modem having an analog front end (AFE), a PHY and a MAC, operating in full duplex (FDX) mode and having a switchable filter block and variable equalizer coefficients in the PHY, with a processor configured to : receiving a command by the media access control (MAC) from the cable modem; and triggering the MAC to send a filter switching control signal to the analog front end based on the received command; causing the AFE to switch a filter path in response to the filter switch control signal and insert a filter switch mark into one or more received samples; and causing the PHY to change its variable equalizer coefficients to reflect current calibration data for the switched filter path substantially synchronously with receiving the samples including the filter switching mark from the AFE.

A second example further defines the first example, wherein the received command includes a change in resource block allocation (RBA) from a cable modem termination system (CMTS).

A third example further defines the first or second example, wherein the cable modem is a 3.1 FDX compliant Data over Cable Service Interface Specification (DOCSIS) modem.

A fourth example further defines the first example, wherein the filter switching flag is inserted with the one or more received samples and is passed from the AFE to the PHY via a high speed interface framing structure.

In a fifth embodiment, the processor of the fourth example is further defined, wherein the filter switching marker includes a filter configuration identifier corresponding to the switched filter path and an offset of the marked sample from a frame synchronization portion of the frame structure.

In a sixth embodiment, the processor of the fifth example is further defined, wherein the calibration data includes predetermined equalizer coefficients corresponding to each available filter path that may be selected.

A seventh example further defines the processor of the second or fourth to sixth examples, wherein the calibration data includes a setting of the predetermined equalizer coefficients for temperature changes.

An eighth embodiment defines a communication system comprising: a block switchable filters for receiving and transmitting full duplex (FDX) signals according to a network-provided resource block allocation (RBA) protocol; and a tuner system in communication with the block of switchable filters, including physical layer (PHY) and media access control (MAC) functionality, the MAC functionality including signaling to cause the block of switchable filters to correspond to a filter path the provided RBA and mark received samples when the filter path changes, and the PHY synchronization equalizer coefficient changes to compensate for the changed filter path based on the marked samples.

A ninth example further defines the communication system of the eighth example, wherein the tuner system further includes an analog front end (AFE) to receive the MAC signaling, cause the filter path change in the block of switchable filters, and use the received samples an interface and framework structure for communicating the marked samples to the PHY.

In a tenth example, the communication system of the ninth example is further developed, wherein the interface comprises a high speed serial interface (HSIF) and wherein the frame structure comprises a filter path change control message having a filter configuration identifier and an offset.

An eleventh example further defines any of eighth to tenth examples, wherein at least a portion of the tuner system includes a system on a chip (SoC).

The eleventh embodiment is the communication system according to any one of eighth to tenth examples, wherein the communication system includes a 3.1 FDX compliant Data over Cable Service Interface Specification modem (DOCSIS modem).

According to a thirteenth example, the eighth example is further defined, wherein equalizer coefficient changes are selected by the PHY from precalibrated matching coefficients for each selectable filter path in the block of switchable filters.

A fourteenth example further defines any of the eighth to tenth or thirteenth examples, wherein equalizer coefficient changes are adjustable by the PHY based on a temperature sensor.

A fifteenth embodiment defines a method for synchronizing filter switching and updating channel equalization coefficients in a cable modem having a switchable filter block, an analog front end (AFE), and a digital tuner having PHY and MAC functionality, the method comprising: receiving a command by the cable modem from a cable modem termination system (CMTS); and sending a filter switching control signal from the MAC to the AFE based on the received command to; causing the AFE to switch a filter path in the switchable filter block in response to the filter switch control signal and insert a filter switch mark into one or more received samples; and causing the PHY to change its equalizer coefficients to compensate for the switched filter path substantially synchronously with receiving the samples including the filter switching mark from the AFE.

A sixteenth embodiment further defines the fifteenth example, wherein the received command includes a change in the resource block allocation (RBA) from the cable modem termination system (CMTS).

In a seventeenth example, the fifteenth and sixteenth examples are further defined, wherein the cable modem is a 3.1 FDX compliant Data over Cable Service Interface Specification (DOCSIS) modem.

In an eighteenth example, the fifteenth and sixteenth examples are detailed, wherein the filter switching flag is inserted with the one or more received samples and is passed from the AFE to the PHY over a high speed interface frame structure.

The eighteenth example may be further defined by a nineteenth example, wherein the filter switching marker includes a filter configuration identifier corresponding to the switched filter path and an offset of the marked sample from a frame synchronization portion of the frame structure.

A twentieth example further defines the fifteenth and sixteenth examples, wherein the PHY changes its equalizer coefficients using the predetermined equalizer coefficients consistent with each available filter path that may be selected.

A twenty-first example further develops the twentieth example, where the PHY calculates its equalizer coefficients using the previous ones correct equalizer coefficients that are modified for detected temperature changes.

A twenty-second embodiment is a system for synchronizing filter switching and updating channel equalization coefficients in a cable modem having a switchable filter block, an analog front end (AFE) and a digital tuner, having PHY and MAC functionality, the system comprising: means for receiving a Command by the cable modem from a cable modem termination system (CMTS); and means for sending a filter switching control signal from the digital tuner to the AFE based on the received command to: cause the AFE to switch a filter path in the switchable filter block in response to the filter switching control signal and insert a filter switching mark into one or more received samples; and causing the PHY to change its equalizer coefficients to compensate for the switched filter path substantially synchronously with receiving the samples including the filter switching mark from the AFE.

A twenty-third example further defines the twenty-second example, wherein the received command includes a change in the resource block allocation (RBA) from the cable modem termination system (CMTS).

A twenty-fourth example further defines the twenty-second or twenty-third example, wherein the cable modem is a 3.1 FDX compliant Data over Cable Service Interface Specification (DOCSIS) modem.

According to a twenty-fifth example, the twenty-second and twenty-third examples are further defined, wherein the filter switching mark is inserted with the one or more received samples and is passed from the AFE to the PHY via a high speed interface frame structure.

A twenty-sixth example further develops the twenty-fifth example, wherein the filter switching marker includes a filter configuration identifier corresponding to the switched filter path and an offset of the marked sample from a frame synchronization portion of the frame structure.

A twenty-seventh example further elaborates the twenty-second or twenty-third example, wherein the PHY changes its equalizer coefficients using the predetermined equalizer coefficients consistent with each available filter path that can be selected.

A twenty-eighth example further develops the twenty-seventh example, wherein the PHY changes its equalizer coefficients using the predetermined equalizer coefficients modified for sensed temperature changes.

A twenty-ninth embodiment further develops the processor according to any of the first to third examples, wherein the filter switching flag is inserted with the one or more received samples and is passed from the AFE to the PHY via a high speed interface frame structure.

A thirtieth example further defines the twenty-ninth example, wherein the filter switching marker includes a filter configuration identifier corresponding to the switched filter path and an offset of the marked sample from a frame synchronization portion of the frame structure.

A thirty-first embodiment further defines the first through fifth examples, wherein the calibration data includes predetermined equalizer coefficients corresponding to each available filter path that may be selected.

A thirty-second example further defines the processor of the first to fifth examples, wherein the calibration data includes a setting of the predetermined equalizer coefficients for temperature changes.

According to a thirty-third example, the method of the eighteenth to twentieth examples further includes inserting the filter switching mark with the one or more received samples and passing it from the AFE to the PHY via a high-speed interface frame structure.

In a thirty-fourth embodiment, the thirty-third example is further developed, wherein the filter switching marker includes a filter configuration identifier corresponding to the switched filter path and an offset of the marked sample from a frame synchronization portion of the frame structure.

A method of the thirty-fifth example further develops those of the eighteenth through twentieth and thirty-third through thirty-fourth examples, wherein the PHY predetermines its equalizer coefficients using the th equalizer coefficients that match each available filter path that can be selected.

A thirty-sixth embodiment further defines the thirty-fifth example, wherein the PHY changes its equalizer coefficients using the predetermined equalizer coefficients modified for detected temperature changes.

Disclaimer: The present disclosure has been described with reference to the accompanying drawing figures in certain exemplary terms, with like reference numerals used to refer to like elements throughout. The structures, devices and methods illustrated are not intended to be to scale or any specific circuitry or anything other than functional block diagrams for illustrating certain features, advantages and are intended to facilitate the disclosure of the inventive embodiments, and their illustration and description are not intended to be in any way limiting with respect to to the appended claims, except for 35 USC 112, sixth paragraph of the claims, where the exact wording "means" is used when appearing in a claim.

As used herein, the terms "component", "system", "interface", "logic", "circuit", "device" and the like are intended to refer only to a basic functional unit such as hardware, software (e.g. in Execution), logic (circuits or programmable firmware) alone or in combination correspond to the claimed functionalities. For example, a component, module, device, or processing unit may mean a microprocessor, controller, programmable logic array and/or circuit coupled thereto, or other logic processing device, and a method or process may include instructions running on a processor. Firmware programmed into a controller means an object, an executable file, a program, a storage device including instructions to be executed, a computer, a tablet PC and / or a mobile phone with a processing device.

To illustrate, a process, logic, method, or module can be any analog circuit, digital processing circuit, or a combination thereof. One or more circuits or modules may reside in a process, and a module may be located as a physical circuit, a programmable array, a processor. Further, elements, circuits, components, modules and processes/methods may be hardware or software, combined with a processor, executable from various computer-readable storage media with executable instructions and/or data stored thereon. Those of ordinary skill in the art will recognize various ways to implement the logical descriptions of the appended claims, and their interpretation should not be limited to any example or description, illustration or layout described above, in the abstract or in the drawing figures.

Claims (21)

Processor in a cable modem with an analog front end (AFE), a PHY and a MAC, operating in full duplex (FDX) mode and having a switchable filter block and variable equalizer coefficients in the PHY, the processor being configured to: Receiving a command by the media access control (MAC) from the cable modem, the received command comprising a change of a resource block allocation (RBA), the RBA change changing a first allocation of downstream and upstream transmission channels to a second, different allocation of downstream and Upstream transmission channels, wherein changing the assignment includes changing a channel from a downstream transmission direction to an upstream transmission direction or vice versa; and Triggering the MAC to provide a filter switching control signal to send analog frontend based on the received command to; causing the AFE to switch a filter path in response to the filter switch control signal and insert a filter switch mark into one or more received samples; and Causing the PHY to change its variable equalizer coefficients to reflect current calibration data for the switched filter path in synchronization with receiving the samples including the filter switching mark from the AFE. Processor after Claim 1 , wherein the received command includes a change in the resource block allocation (RBA) from a cable modem termination system (CMTS). Processor after Claim 1 or 2 , where the cable modem is a 3.1 FDX compliant Data over Cable Service Interface Specification (DOCSIS) modem. Processor according to one of the preceding claims, wherein the filter switching mark with is inserted into the one or more received samples and is passed from the AFE to the PHY via a high speed interface frame structure. A processor according to any preceding claim, wherein the filter switching marker includes a filter configuration identifier corresponding to the switched filter path and an offset of the marked sample from a frame synchronization portion of the frame structure. A processor according to any preceding claim, wherein the calibration data includes predetermined equalizer coefficients corresponding to each available filter path that can be selected. Processor according to one of the Claims 2 or 4 until 6 , wherein the calibration data includes an adjustment of the predetermined equalizer coefficients to temperature changes. Communication system, comprising: a block of switchable filters for receiving and transmitting full duplex (FDX) signals according to a network-provided resource block allocation (RBA) protocol; and a tuner system in communication with the block of switchable filters, including physical layer (PHY) and media access control (MAC) functionality, the MAC functionality including signaling to cause the block of switchable filters to correspond to a filter path the provided RBA and mark received samples when the filter path changes, and the PHY synchronization equalizer coefficient changes to compensate for the changed filter path based on the marked samples, an RNA change due to the signaling changing a first assignment of downstream and Upstream transmission channels to a second, different assignment of downstream and upstream transmission channels, wherein changing the assignment includes changing a channel from a downstream transmission direction to an upstream transmission direction or vice versa. communication system Claim 8 , wherein the tuner system further comprises an analog front end (AFE) for receiving the MAC signaling, causing the filter path change in the block of switchable filters, and the received samples using an interface and frame structure for communicating the marked samples to mark the PHY. communication system Claim 9 , wherein the interface comprises a high speed serial interface (HSIF) and wherein the frame structure comprises a filter path change control message having a filter configuration identifier and an offset. Communication system according to one of the Claims 8 until 10 , wherein at least a portion of the tuner system comprises a system on a chip (SoC). Communication system according to one of the Claims 8 until 11 , wherein the communication system includes a 3.1 FDX compliant data over cable service interface specification modem (DOCSIS modem). Communication system according to one of the Claims 8 until 12 , where equalizer coefficient changes are selected by the PHY from pre-calibrated matching coefficients for each selectable filter path in the block of switchable filters. Communication system according to one of the Claims 8 until 10 or 13 , where equalizer coefficient changes are adjustable by the PHY based on a temperature sensor. A method for synchronizing filter switching and updating channel equalization coefficients in a cable modem having a switchable filter block, an analog front end (AFE) and a digital tuner having PHY and MAC functionality, the method comprising: receiving a command by the cable modem from a cable modem -Completion System (CMTS), wherein the received command comprises a change of a resource block allocation (RBA), the RBA change comprising changing a first allocation of downstream and upstream transmission channels to a second, different allocation of downstream and upstream transmission channels, wherein changing the Assignment includes changing a channel from a downstream transmission direction to an upstream transmission direction or vice versa; and sending a filter switching control signal from the MAC to the AFE based on the received command to; causing the AFE to switch a filter path in the switchable filter block in response to the filter switch control signal and insert a filter switch mark into one or more received samples; and causing the PHY to use its equalizer coefficients to compensate for the switched filter path changes synchronously with receiving the samples including the filter switching mark from the AFE. Procedure according to Claim 15 , wherein the received command includes a change in the resource block allocation (RBA) from the cable modem termination system (CMTS). Procedure according to one of the Claims 15 or 16 , where the cable modem is a 3.1 FDX compliant Data over Cable Service Interface Specification (DOCSIS) modem. Procedure according to Claim 15 or 16 , wherein the filter switching mark is inserted with the one or more received samples and is passed from the AFE to the PHY via a high speed interface frame structure. Procedure according to one of the Claims 15 until 18 , wherein the filter switching marker has a filter configuration identifier corresponding to the switched filter path and an offset of the marked sample from a frame synchronization portion of the frame structure. Procedure according to one of the Claims 15 until 19 , where the PHY changes its equalizer coefficients using the predetermined equalizer coefficients consistent with each available filter path that can be selected. Procedure according to Claim 20 , where the PHY changes its equalizer coefficients using the predetermined equalizer coefficients modified for sensed temperature changes.

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