DE102017122011A1 - Method and apparatus for blocking high speed bus operation at high common mode voltages - Google Patents

Abstract

A device including a handshake window circuit breaker having a pair of differential inputs and an output for enabling the window, a common mode voltage detector coupled to a power input and a ground input and having a handshake inhibit output, and a handshake blocker coupled to the handshake window breaker, the common mode voltage detector, and the pair of differential inputs. If a common mode voltage is detected out of range ("too large"), high-speed handshake protocols are such that the bus operates at a slower data rate.

Description

Cross-reference to related applications

This application claims priority to US Provisional Patent Application No. 62 / 402,843, filed Sep. 30, 2016, which is incorporated herein by reference.

background

The Universal Serial Bus (USB) is an industry-standard protocol developed in the mid-1990s that defines cables, connectors, and communication protocols used in a bus to connect, communicate, and power between a computer (host) and computer an electronic device (client) can be used. Unlike other data buses (eg, Ethernet, HDMI), USB connections are directed, with both upstream and downstream interfaces coming from a single host. It is currently being developed by the USB Implementers Forum (USB IF).

The original specification USB 1.0, which was introduced in January 1996, defined data rates of 1.5 Mbps as "low speed" and 12 Mbps as "full speed." The specification USB 2.0 was introduced in April 2000 and from USB -IF End of 2001 ratified and defined an additional data rate of 480 MBit / s as "High Speed". USB 2.0 uses four shielded lines: two for power (VBUS and GND) and two for differential data signals (D + and D-), which provide half-duplex data transfers. The default data rate for a USB 2.0 bus is Full Speed after each bus reset, but can be increased to High Speed as determined by a "handshake" protocol that uses outband signals to verify that both host and client are capable of high-speed operation.

Although the USB 2.0 signals D + and D- are transmitted on a differential pair of wires, they can still be affected by large common-mode differential signals between the host and client, for example if the masses of the host and / or client are not connected to the ground line. This can occur in industrial environments, in aircraft, in heating, ventilation and air conditioning (HVAC) systems, to name but a few.

Common mode noise becomes more problematic at higher data rates, e.g. In high-speed operation of a USB 2.0 bus. There are situations, therefore, where it is desirable to run a USB 2.0 bus at the lower full-speed data rate, although the devices are high-speed capable. The automatic handshake protocol used after a bus reset, however, makes full-speed operation problematic if both host and client are high-speed capable.

These and other limitations of the prior art will become apparent to those skilled in the art after a reading of the following descriptions and an analysis of the various figures of the drawings.

Summary

A method and apparatus for blocking high speed bus operation in a USB 2.0 bus is provided.

An example of a method for blocking high-speed operation includes monitoring a Universal Serial Bus (USB) for a bus reset signal and blocking a high-speed handshake protocol on the USB during the time of a handshake. Window after detection of a reset if a high-speed blocking signal is present. The high-speed stall signal may be the result of detecting a high common-mode voltage on the bus, or may be for other reasons that may require smaller data rates.

A first exemplary device includes a handshake window breaker having a pair of differential inputs and an output for enabling the window, a common mode voltage detector coupled to a power input and a ground input and having a handshake inhibit output , and a handshake blocker coupled to the handshake window breaker, the common mode voltage detector, and the pair of differential inputs. If a common mode voltage is detected out of range ("too large"), high-speed handshake protocols will be blocked.

A second exemplary device includes: a handshake window breaker having a pair of differential inputs and an output for enabling the window, the handshake window breaker comprising a USB reset detector and a monoflop coupled to the USB reset detector ; a common mode voltage detector coupled to a power input and a ground input and having a handshake inhibit output, wherein the common mode voltage detector comprises a ground line resistor provided between the ground input and a ground output is a ground comparator coupled to the ground input, a power supply A comparator coupled to the power supply input and a latch having a set input coupled to the ground comparator and a reset input coupled to the power supply comparator; a handshake blocker coupled to the pair of differential inputs; and an AND gate having inputs coupled to the window enable output and the handshake blocking output and having an output coupled to a control input of the handshake blocker.

These and other embodiments, features, and advantages will become apparent to those skilled in the art after a reading of the following descriptions and an analysis of the various figures of the drawings.

Brief description of the drawings

Several exemplary embodiments will now be described with reference to the drawing, wherein like reference numerals are provided on like components. The exemplary embodiments are intended to illustrate, but not limit, the invention. The drawings include the following figures:

1 Fig. 12 is a block diagram of a first embodiment of apparatus for blocking high speed bus operation at high common mode voltages;

2 Fig. 12 is a block diagram of a second embodiment of apparatus for blocking high speed bus operation at high common mode voltages;

3 FIG. 10 is a flowchart of an exemplary process for detecting common mode voltages; FIG.

4 FIG. 10 is a flowchart illustrating an exemplary procedure for blocking high-speed operation; FIG.

5 Figure 9 is a timing diagram illustrating a high-speed handshake process on a USB 2.0 bus; and

6 is a timing diagram illustrating the high-speed handshake process blocked on a USB 2.0 bus.

Detailed description of embodiments

In 1 includes a device set forth by way of example and not limitation 10 To block high-speed bus operation, a handshake window unlocker 12 , a common-mode voltage detector 14 and a handshake blocker 16 , The handshake window unlocker 12 has a pair of differential inputs D + _IN and D-_IN and a window enable output WE. The common-mode voltage detector 14 is coupled between a power supply input VBUS_IN and a ground input GND_IN and has a handshake inhibit output HS_Inhibit. The handshake blocker 16 is through an AND gate 18 with the WE output of the handshake window breaker 12 and with the output HS_Inhibit of the common-mode voltage detector 14 and coupled to the differential line pair D + _IN and D-_IN.

The handshake window unlocker 12 includes, in this non-limiting example, a USB reset detector 20 and a monoflop 22 , The USB reset detector 20 has inputs coupled to lines D + _IN and D-_IN, and an output connected to one input of the monoflop 22 is coupled. The output of the monoflop 22 outputs the window enable signal WE. In this non-limiting example, the USB reset detector detects a bus reset when both D + _IN and D-_IN are at LO for approximately 2.5 microseconds and triggers the output WE of the monoflop 22 to go to HI for about 9 milliseconds. In this example, the 9 milliseconds include a "handshake window" during which high-speed handshakes can take place.

The common-mode voltage detector 14 includes a ground line resistor in this non-limiting example 24 between GND_IN and GND_OUT, a pair of comparators 26 and 28 , an OR gate 30 , a latch 32 and a comparator 34 , In this example are the comparators 26 and 28 referenced to +0.25V and -0.25V, giving the output of the OR gate 30 is at HI when GND_IN is out of the range of -0.25V to +0.25V (a range of acceptable common-mode voltages). When the common mode voltages are out of range, the OR gate becomes 30 the latch 32 set so that the signal HS_Inhibit is HI. The latch 30 is from the comparator 34 reset when VBUS_IN traverses a reference voltage of, for example, 3V. The term "high common mode voltage" as used herein means a high absolute value of the common mode voltage, either negative or positive.

The handshake blocker 16 includes a two-pole electronic circuit breaker 36 with normally closed contact, a four-pole electronic circuit breaker 38 with normally open contact, four ground resistors 40 and an inverter 42 , In this non-limiting example, the electronic switch includes 36 a first electronic differential line A switch coupling a first differential input D + _IN to a first differential output D + _OUT and a second electronic differential line switch coupling a second differential input D-_IN to a second differential output D-_OUT. In this non-limiting example, the electronic switch includes 38 Also, a first electronic switch, a second electronic switch, a third electronic switch and a fourth electronic switch, each of which is a series circuit with one of the four ground resistors 40 forms. For example, the handshake blocker 16 a series circuit of a first electronic switch and a first resistor coupling a first differential input of the pair of differential inputs to ground, a series connection of a second electronic switch and a second resistor coupling a second differential input of the pair of differential inputs to ground, a series connection of a third electronic switch and a third resistor that couples the first differential output to ground, and a series circuit of a fourth electronic switch and a fourth resistor that couples the second differential input of the pair of differential inputs to ground.

In operation when the output HD of the AND gate 18 HI is on (eg WE is HI and HS_Inhibit is HI, resulting in a handshake blocking signal), the electronic switch opens 36 and the electronic switch 38 closes to turn off each of D + _IN, D + _OUT, D-_IN and D-_OUT and connect them to ground. This effectively stops any handshake communication on lines D + and D- for the duration of the handshake window. When the output HD of the AND gate 18 is at LO, the electronic switch closes 36 and the electronic switch 38 opens what allows normal communication on lines D + and D-.

In 2 is an alternative device 10 ' shown blocking the high-speed bus operation, where in the 1 and 2 same reference numbers are used for the same devices. In this second embodiment, the device differs 10 ' of the first embodiment only in the design of the handshake blocker 16 ' , In this non-limiting embodiment, when the output HD is at HI (eg, a handshake blocking signal), a single-pole, normally-open, electronic changeover switch is provided 44 closed, shorting the D + and D- lines to ground and preventing any handshake communication for the duration of the handshake window. In this alternate embodiment, the electronic switch may include a pair of electronic switches that couple the pair of differential inputs to ground, the pair of electronic switches being controlled by the control input of the handshake blocker.

3 is a flowchart illustrating an example flow 46 for the detection of common-mode voltages, in this embodiment by the hardware of the DC voltage detector 14 is implemented. The detection of common-mode voltages is included 48 idle with HS_Inhibit set to "0" or "LO" until VBUS exceeds 3V. Next will be in one operation 50 the common mode voltage is checked to see if it is within the range, e.g. From -0.25V to +0.25V. If the common mode voltage is outside of the range, in process 52 HS_Inhibit is set to "1" or "HI", and if VBUS falls below 3V, process control returns to Operation 48 ,

4 is a flowchart illustrating an example flow 54 to block the high-speed operation, which in this embodiment by the hardware of the 1 or 2 is implemented. The process is in the process of blocking the high-speed operation in process 56 at rest until D- is at LO and D + falls, at which time in process 58 a reset is detected. When D- is LO and D + is LO for a period of time (eg, 2.5 μs), a process checks for the high common mode voltage mode. If HS_Inhibit is LO, the flow returns to operation 56 back. If HS_Inhibit is HI, a task locks 62 the high-speed operation by preventing the high-speed handshake protocol on the D + and D- buses. After the handshake window has expired (a / k / a 9 milliseconds timer), the process returns to operation 56 back.

The 5 and 6 FIG. 4 are timing diagrams illustrating the operation of the above-described apparatus and method. In 5 HS_Inhibit is LO and, as can be seen at the point "HS Handshake Start", lines D + and D- have permission to perform their handshake process to configure the bus for high speed operation. In 6 For example, shortly after the USB reset start, the HS_Inhibit line is at HI (due to the detection of a high common mode voltage, eg, an out of range common mode voltage), and the D + and D- lines are grounded, preventing any Handshake processes take place.

Although various embodiments have been discussed in which high-speed operation is blocked when high common-mode voltages are present on the bus, there are other reasons in which blocking of high-speed operation may be desirable. For example, if the host and client do not require high data rate communication, it may be desirable to block high speed operation to reduce power consumption, reduce radiation, increase bus length, etc. The HS_Inhibit signal Therefore, it can be generated in many ways, including simply connecting the HS_Inhibit line to the power bus.

Although various embodiments have been described using specific terms and devices, such description is for illustrative purposes only. The words used are words of description rather than limitation. It should be understood that changes and modifications may be made by ordinary skill in the art without departing from the spirit or scope of the invention as claimed. It should also be understood that aspects of various other embodiments may be substituted in whole or in part with each other. It is therefore intended that the claims be interpreted in accordance with their true spirit and scope of the invention and without limitation or limitation.

Claims (17)

A method of blocking high speed bus operation, comprising: Monitoring a Universal Serial Bus (USB) for a Bus Reset signal; and Blocking a high-speed handshake protocol on the USB during the time of a handshake window after detection of a reset if a high-speed blocking signal is present. The method for blocking the high-speed bus operation of claim 1, further comprising detecting a common-mode voltage on a Universal Serial Bus (USB) and outputting the high-speed stall signal when the common-mode voltage is out of range. Apparatus for blocking high speed bus operation at high common mode voltages, comprising: a handshake window breaker having a pair of differential inputs and a window enable output; a common mode voltage detector coupled to a power supply input and a ground input and having a handshake inhibit output; and a handshake blocker coupled to the handshake window breaker, the common mode voltage detector, and the pair of differential inputs. The apparatus for blocking high speed bus operation at high common mode voltage conditions of claim 3, wherein the handshake window circuit breaker includes a USB reset detector and a monoflop coupled to the USB reset detector. Apparatus for blocking high speed bus operation at high common mode voltage conditions as claimed in claim 3, wherein the common mode voltage detector includes a resistor provided between the ground input and a ground output, a ground comparator coupled to coupled to the ground input, a power supply comparator coupled to the power supply input, and a latch whose set input is coupled to the ground comparator and whose reset input is coupled to the power supply comparator. Apparatus for blocking high speed bus operation at high common-mode voltage conditions according to claim 3, further comprising an AND gate whose inputs are coupled to the window enable output and the handshake disable output and whose output is connected to a Control input of the handshake blocker is coupled. Apparatus for blocking high speed bus operation at high common mode voltage conditions as claimed in claim 3, wherein the handshake blocker includes a pair of electronic switches which couple the pair of differential inputs to ground, the pair of electronic switches being connected through the control input of the handshake. Blocker is controlled. An apparatus for blocking high speed bus operation at high common mode voltages, comprising: a handshake window breaker having a pair of differential inputs and a window enable output, the handshake window breaker comprising a USB reset detector and a Includes monoflop coupled to the USB reset detector; a common mode voltage detector coupled to a power input and a ground input and having a handshake blocking output, wherein the common mode voltage detector includes a ground line resistor provided between the ground input and a ground output , a mass comparator coupled to the ground input, a power supply comparator coupled to the power supply input, and a latch whose set input is coupled to the ground comparator and whose reset input is coupled to the power supply comparator; a handshake blocker coupled to the pair of differential inputs; and an AND gate whose inputs are coupled to the window enable output and the handshake disable output and whose output is coupled to a control input of the handshake blocker. Apparatus for blocking high speed bus operation under high common mode voltage conditions according to claim 8, wherein the handshake blocker includes a pair of electronic switches which couple the pair of differential inputs to ground, the pair of electronic switches being connected through the control input of the handshake. Blocker is controlled. Apparatus for blocking high speed bus operation at high common mode voltage conditions according to claim 9, wherein the pair of electronic switches comprises a single pole, normally open contact, electronic switch. The apparatus for blocking high speed bus operation at high common mode voltage conditions of claim 8, wherein the handshake blocker includes a series connection of a first electronic switch and a first resistor that couples a first differential input of the pair of differential inputs to ground, and a series connection of a second electronic switch and a second resistor coupling a second differential input of the pair of differential inputs to ground. The apparatus for blocking high speed bus operation at high common mode voltage conditions of claim 11, wherein the handshake blocker further includes a first electronic differential line switch coupling the first differential input to a first differential output and a second electronic differential line switch which couples the second differential input to a second differential output. The apparatus for blocking high-speed bus operation at high common-mode voltage conditions of claim 12, wherein the first differential electronic switch and the second electronic differential switch comprise a two-pole, normally-closed, electronic differential switch. The apparatus for blocking high speed bus operation at high common mode voltage conditions of claim 13, further comprising an inverter coupling the output of the AND gate to a control input of the normally closed two-pole differential electronic circuit breaker. The apparatus for blocking high speed bus operation at high common mode voltage conditions of claim 12, wherein the handshake blocker includes a series connection of a third electronic switch and a third resistor that couples the first differential output to ground and a series connection of a fourth one electronic switch and a fourth resistor which couples the second differential input of the pair of differential inputs to ground. The apparatus for blocking high-speed bus operation at high common-mode voltage conditions of claim 15, wherein the first electronic switch, the second electronic switch, the third electronic switch, and the fourth electronic switch comprise a normally-open four-pole electronic circuit breaker. Apparatus for blocking high speed bus operation at high common mode voltage conditions according to claim 16, wherein the output of the AND gate is coupled to a control input of the four pin electronic breaker with normally open contact.

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