DE102017106076B3 - Device for signal delay using a reference oscillator and its application in a TOF camera - Google Patents

Abstract

A method is provided for detecting the delay between a light pulse (LP) and a shutter-on signal (SON) to improve methods and apparatus for measuring the time-of-flight of light. A DLL generates based on a reference clock (RCK) a control signal (RS) for a master delay chain (MDL) so that their delay is in a predefinable or structurally predetermined fixed ratio to the period of the reference clock (RCK). With the control signal (RS), a second slave delay chain (SDL) is now readjusted in its delay and, since it is thermally well coupled to the master delay chain (MDL) by microintegration, thermally stabilized. The delay of the master delay chain (SDL) thus depends only on the period of the reference clock (RCK). The slave delay chain (SDL) is used to determine the delay between a shutter-on signal (SON) to control the exposure of the pixels of a time-of-flight camera on the one hand and the actual transmission of a light pulse (LP) to generate the On the other hand, to measure the optical measurement signal for this camera and, if necessary, readjust or follow-up. The detection of the emission of the light pulse can be optically controlled, voltage controlled or current controlled. The reference clock is preferably generated by a MEMS oscillator or a quartz oscillator. In the description, devices are proposed which are preferably suitable for use in the proposed method.

Description

preamble

The invention is directed to a method for detecting the delay between a light pulse LP and a shutter-on signal (SON) for improving methods and devices for measuring the light transit time. It falls into the class of systems in which the reflection or re-emission of electromagnetic, here optical waves is evaluated (G01S 17/00). Since the duration of light pulses is to be evaluated, it is also a system that allows the simultaneous measurement of the distance and other coordinates by means of a camera optics and an imaging sensor element (G01S 17/42). Typically, the measured data are displayed in pictorial form after image generation (G01S 17/89).

General introduction

Cameras based on the principle of light transit time measurement, hereafter referred to as time-of-flight cameras, indirectly measure the transit time (time delay Td) between the emitted light pulse LP and the received light signal 1 ). The light pulse LP is emitted by a light source. The light source used is preferably a light-emitting diode (also referred to below as LED) or a laser diode. The emitted light pulse LP falls on an object or object points whose distances are to be determined. Each of the objects or each of the object points now reflects part of the light of the previously emitted light pulse LP. Typically, but not necessarily, the camera and the device for emitting the light pulses LP form a unit. The reflection of the light pulse LP by the objects or the object points now takes place in such a way that the light of the light pulse LP reflected in this way reaches a photoelectric element, for example a PN junction. There electron-hole pairs are preferably generated, which can preferably be sucked by a built-in photoelectric element drift field. At least one polarity of the charge carriers thus produced is then preferably collected in a capacitance. The potential of a control electrode may allow or inhibit this collection. This control electrode is referred to below as a shutter which is controlled by a shutter-on signal or a signal derived therefrom. Thus, in a temporal relationship with the light pulse LP of the luminous means, preferably the light emitting diode or the laser diode, said electronic shutter is opened in the form of a first shutter and a first charge amount Q1 generated in the opening time in the photosensitive circuit of the photoelectric element, stored in a first capacity. In temporal relation to the end of the light pulse LP, the first shutter closes again. In the first capacity is then the first charge amount Q1. With the closing of the first shutter, a second shutter is opened and a second charge amount Q2 is collected, for example, in a second capacity. In the example of 1 the laser pulse should have a temporal laser pulse length Ttrig. In the example of 1 the first measuring signal MQ1 is used to open the first shutter. The first measurement signal MQ1 is used as the shutter-on signal SON for measuring the first charge quantity Q1.

In the example of 1 The first measurement signal MQ1 has a first measurement pulse MP1 during which the first charge amount Q1 in the first capacity is collected. The first measuring pulse MP1 starts in the example of 1 synchronously with the start of the emission of the light pulse LP and ends in synchronism with the end of the emission of the light pulse LP. The first measuring pulse MP1 thus has in the example of 1 the temporally first measuring pulse duration TMP1, which in the example of the 1 the temporal light pulse length Ttrig corresponds. Other first measuring pulses MP1 in temporal position and length relative to the temporal position of the light pulse LP and its temporal light pulse length Ttrig are known from the prior art.

In the example of 1 The second measurement signal MQ2 has a second measurement pulse MP2 during which the second charge amount Q2 in the second capacitance is collected. The second measurement signal MQ2 is used as the shutter-on signal SON for measuring the second charge quantity Q2. The second measuring pulse MP2 starts in the example of 1 synchronously with the end of the transmission of the light pulse LP and thus with the end of the first measuring pulse MP1. In the example of 1 has the second measuring pulse MP2 has the temporal second measuring pulse duration TMP2, which in the example of 1 the temporal light pulse length Ttrig corresponds. Other second measuring pulses MP2 in time position and length relative to the temporal position of the light pulse LP and its temporal light pulse length Ttrig or in temporal position and length relative to the first measuring pulse MP1 are known from the prior art.

In this way two charge quantities Q1 and Q2 are determined in space or time multiplex. The reflected light by the objects and / or object points reached as a reflected pulse RP, the photoelectric element delayed by a time Td. If this time delay Td is zero, then the second charge quantity is typically also zero. If the time delay Td is equal to or greater than the temporal light pulse length Ttrig, then the first charge is zero and the second charge is typically different from zero.

From the charge quantities Q1 and Q2, the time delay Td and thus the distance d can be calculated according to the following formula. Td corresponds to the light transit time between transmission of the light pulse LP and the reception of the reflected pulse RP by the photoelectric element of the time-of-flight camera. $$d=\frac{c}{2}TtriG\frac{Q2}{\mathrm{<figure-callout\; id="1"\; label="Q"\; filenames="DE102017106076B3\_0005.png,DE102017106076B3\_0013.png"\; state="\{\{state\}\}">Q</figure-callout>}1+Q2}$$

Here d stands for the distance to the object or object point which is to be determined and c for the speed of light.

The measurement of the distance d is based on the simultaneous opening of the first first charge amount shutter Q1 by the first measurement pulse MP1 of the first measurement signal MQ1 and the start of the emission of the light pulse LP. If one of the two signals is delayed by a time corresponding to a time delay error, then the measurement of the distance d by this delay error is incorrect. For example, a delay error of 1 ns corresponds to a length measurement error of 15 cm. However, such delay errors occur in the prior art.

For example, the following protection rights are known from the prior art, which are relevant for the understanding of this disclosure:
DE 10 2009 020 218 B3 . DE 10 253 437 B4 . US 6,373,557 B1 . EP 1 040 366 B1 . EP 2 191 298 B1 . US 6,452,666 B1 . US Pat. No. 7,060,957 B2 . US Pat. No. 7,095,487 B2 . US Pat. No. 7,683,954 B2 . US Pat. No. 7,947,939 B2 . US 8 638 425 B2

From the US 2006/0 164 141 A1 a device is known in which a reference signal generator (reference numeral 101 of the US 2006/0 164 141 A1 ) generates a measuring signal, which for a via a transmission path (reference numeral 110 of the US 2006/0 164 141 A1 ) and on the other hand via a controlled delay line (reference numeral 120 of US 2006/0 164 141 A1 ) to be led. A phase detector (reference numeral 130 of FIG US 2006/0 164 141 A1 ) now measures the delay between the signal after passing through the transmission path (reference numeral 110 of US 2006/0 164 141 A1 9 and the other signal after passing through the controlled delay path (reference numeral 120 of US 2006/0 164 141 A1 ). A controlled system (reference 140 of the US 2006/0 164 141 A1 ) then controls the delay in the controlled delay line (reference numeral 120 of US 2006/0 164 141 A1 ) to. With a suitable choice of the controlled variables, phase equilibrium or at least phase constancy arises after some time. In this state, the controlled delay line (reference numeral 120) then emulates the US 2006/0 164 141 A1 ) the delay in the transmission path (reference numeral 110 of US 2006/0 164 141 A1 ). The control signal is in accordance with the US 2006/0 164 141 A1 then used for a same controlled delay path (reference numeral 150 of FIG US 2006/0 164 141 A1 ) to delay another signal to use, wherein the delay of this further signal then corresponds to that in the transmission path or is at least in a fixed ratio thereto. The US 2006/0 164 141 A1 however, does not disclose a method and apparatus for detecting the timing of this further signal against a third signal.

From the US 2014/0 232 475 A1 For example, a suitable oscillator is known.

The proposed method is therefore based on the object to provide a solution which does not have the above disadvantages of the prior art by temperature and operating state-independent measurement and possibly compensation of the different delays to eliminate the delay errors and has further advantages.

This object is achieved by a device according to claim 1.

Solution of the problem of the invention

The object is achieved by a method for detecting the delay between a light pulse LP and a shutter-on signal (SON) for improving methods and devices for measuring the light transit time, wherein the shutter-on signal (SON) a first and has a second state. A photoelectric element generates electric charge carriers when irradiated with light. These electric carriers are accumulated or not collected in an amount of charge (Q1, Q2) depending on whether the shutter-on signal (SON) is in the first or second state. This collection takes place in the first state and not in the second state. The light pulse LP is generated in a temporal relationship with a light-emitting-on signal (LON) and emitted by a light source (LED). This temporal relationship is typically given by the time delays of the various circuit parts in generating the respective signals. Although the fixed temporal relationship is typically fixed in terms of circuitry, it can be distinguished from environmental and operating conditions, such as, for example, the temperature, depend. The lamp-on-signal (LON) is typically also in such a fixed temporal relationship with the shutter-on-signal (SON). With regard to this fixed temporal relationship, the same applies again: although this fixed temporal relationship is typically predetermined in terms of circuitry, it may depend on environmental and operating conditions, such as temperature. Of course, it is conceivable, but not very useful, to modify these fixed temporal relationships and thus to produce a modulation.

1. 1. Der Lichtpuls LP oder ein aus dem Lichtpuls LP durch Streuung oder sonstige optische Modifikation erzeugter Streulichtpuls SLP wird mittels einer Detektionsvorrichtung, insbesondere durch eine Fotodiode FD und durch eine erste Eingangsschaltung (ISM1) , erfasst und in ein erfasstes Lichtpulssignal LPI gewandelt.
2. 2. Der elektrische Strom durch das Leuchtmittel LED wird mittels einer Detektionsvorrichtung, insbesondere durch einen Übertrager TR oder ein Hall-Element oder einen Shunt-Widerstand SR oder eine andere Strommessvorrichtung, sowie durch eine erste Eingangsschaltung ISM1 erfasst und in ein erfasstes Lichtpulssignal LPI gewandelt.
3. 3. Das elektrische Potential eines elektrischen Anschlusses des Leuchtmittels LED oder eines Sendesignals LPS zur Ansteuerung des Leuchtmittels LED wird mittels einer Detektionsvorrichtung, insbesondere durch eine erste Eingangsschaltung ISM1, erfasst und in ein erfasstes Lichtpulssignal LPI gewandelt.

As a next step, a detected light pulse signal LPI is generated, which is to represent a signal for the transmission of the light pulse LP and should be as synchronous as possible with its transmission. There are essentially three methods of doing this:

1. 1. The light pulse LP or a generated from the light pulse LP by scattering or other optical modification scattered light pulse SLP is detected by means of a detection device, in particular by a photodiode FD and by a first input circuit (ISM1), and converted into a detected light pulse signal LPI.
2. 2. The electric current through the light emitting means LED is detected by means of a detection device, in particular by a transformer TR or a Hall element or a shunt resistor SR or another current measuring device, and by a first input circuit ISM1 and converted into a detected light pulse signal LPI.
3. 3. The electrical potential of an electrical connection of the luminous means LED or a transmission signal LPS for controlling the luminous means LED is detected by means of a detection device, in particular by a first input circuit ISM1, and converted into a detected light pulse signal LPI.

The time delay between the shutter-on signal (SON) and the detected light pulse signal LPI is detected in the form of the value of a measured value signal (MD), in particular using a drive circuit SD for the shutter and in particular using a synchronous optical receiver SOR. In order to achieve an optimal correction, the shutter-on signal SON or a light-on-signal LON, which is used to control the light-emitting means LED, by a central clock unit CCU of the proposed time-of-flight camera using this both signals (LON, SON) preferably generated, readjusted. Thus, the shutter-on signal SON is delayed in time as a function of the value of the measured value signal MD, or the illuminant-on signal LON is generated in time as a function of the value of the measured value signal MD. Both signals can also be regulated.

Particularly preferably, the two signals are generated by the control of the central clock unit CCU of the proposed time-of-flight camera so that the shutter-on signal SON pulses with a shutter-to-signal pulse width and with a time start of these pulses having. The detected light pulse signal LPI then also has pulses with a light pulse signal pulse width and with a temporal beginning of the pulses on the basis of a suitable pulse control of the lamp-on signal LON. The shutter-on signal SON is generated in the central clock unit CCU of the proposed time-of-flight camera in dependence on the value of the measured value signal MD delayed in time such that for at least one pair of a pulse of the shutter-on signal SON and a pulse of the detected light pulse signal LPI, the time interval between the beginning of the pulse of the shutter-on signal SON and the beginning of the pulse of the detected light pulse signal LPI less than 10%, better less than 5%, better less than 2%, better less than 1% of the light pulse signal pulse width and less than 10%, better less than 5%, better less than 2%, better still less than 1% of the shutter-to-signal pulse width.

1. 1. Das Erfassen des Lichtpulses LP oder eines aus dem Lichtpuls LP durch Streuung oder sonstige optische Modifikation erzeugten Streulichtpulses SLP mittels einer Detektionsvorrichtung, insbesondere durch eine Fotodiode FD und durch eine erste Eingangsschaltung ISM1, und Wandlung in ein erfasstes Lichtpulssignal LPI, wodurch das erfasste Lichtpulssignal LPI einen Empfangspuls aufweist, der mit dem Lichtpuls LP oder dem Streulichtpuls SLP in einem festen zeitlichen Zusammenhang steht.
2. 2. Das Erfassen des elektrischen Stroms durch das Leuchtmittel LED mittels einer Detektionsvorrichtung, insbesondere durch einen Übertrager TR oder ein Hall-Element oder einen Shunt-Widerstand SR oder eine andere Strommessvorrichtung, sowie durch eine erste Eingangsschaltung ISM1, und Wandlung in ein erfasstes Lichtpulssignal LPI, wodurch das erfasste Lichtpulssignal LPI einen Empfangspuls aufweist, der mit dem Lichtpuls LP oder dem Streulichtpuls SLP in einem festen zeitlichen Zusammenhang steht.
3. 3. Das Erfassen des elektrischen Potentials eines elektrischen Anschlusses des Leuchtmittels LED oder eines Sendesignals LPS zur Ansteuerung des Leuchtmittels LED mittels einer Detektionsvorrichtung, insbesondere durch eine erste Eingangsschaltung ISM1, und Wandlung in ein erfasstes Lichtpulssignal LPI, wodurch das erfasste Lichtpulssignal LPI einen Empfangspuls aufweist, der mit dem Lichtpuls LP oder dem Streulichtpuls SLP in einem festen zeitlichen Zusammenhang steht.

In addition to this regulation, an essential part of the proposed method is a sub-method for detecting the delay between a light pulse LP and a shutter-on signal SON for improving methods and devices for measuring the light transit time. The shutter-on signal SON again has at least one shutter-to-signal pulse with a start of the shutter-to-signal pulse and a shutter-to-signal pulse width. Likewise, the light pulse LP has a temporal beginning and a temporal light pulse width. The sub-method comprises providing a reference clock RCK, providing a DLL (delay-locked loop) comprising a master delay chain MDL as a delay adjustable delay chain. In this case, the delay of the master delay chain MDL depends on a control signal RS formed in the DLL. The sub-method further comprises synchronizing the DLL with the reference clock RCK and generating the control signal RS, as well as providing a slave delay chain SDL. The slave delay chain SDL has an input and a chain of nodes within the slave delay chain SDL. Furthermore, the slave delay chain SDL has an enable input EN which freezes the nodes of the slave delay chain SDL, ie a change in the logic values of the output nodes of the special inverters (SI ₁ , SI ₂ ,... SI ( _{n -1} ), SI _n ) within the slave delay chain (SDL) prevents when it is in a first logical state and the transport allows logical information from node to node within the slave delay chain SDL when in a second logical state. The sub-method further comprises feeding the shutter-on signal SON or a signal derived therefrom (SOND, SONDI) into the input of the slave delay chain SDL. The delay during the passage of the shutter-on signal SON or the signal derived therefrom (SOND, SONDI) through the slave delay chain SDL depends on the control signal RS. In the next step of the partial method, the detected light pulse signal LPI is determined again. Here are three basic steps in question:

1. Detecting the light pulse LP or a scattered light pulse SLP generated by the light pulse LP by scattering or other optical modification by means of a detection device, in particular by a photodiode FD and by a first input circuit ISM1, and conversion into a detected light pulse signal LPI, whereby the detected light pulse signal LPI has a reception pulse which is in a fixed temporal relationship with the light pulse LP or the scattered light pulse SLP.
2. 2. The detection of the electric current through the light emitting means LED by means of a detection device, in particular by a transformer TR or a Hall element or a shunt resistor SR or other current measuring device, and by a first input circuit ISM1, and conversion to a detected light pulse signal LPI whereby the detected light pulse signal LPI has a receiving pulse which is in a fixed temporal relationship with the light pulse LP or the scattered light pulse SLP.
3. 3. The detection of the electrical potential of an electrical connection of the luminous means LED or a transmission signal LPS for controlling the luminous means LED by means of a detection device, in particular by a first input circuit ISM1, and conversion into a detected light pulse signal LPI, whereby the detected light pulse signal LPI has a received pulse, which is in a fixed temporal relationship with the light pulse LP or the scattered light pulse SLP.

As further steps, the proposed sub-method comprises feeding the detected light pulse signal LPI into the enable input EN of the slave delay chain SDL in such a way that before the start of the received pulse, the detected light pulse signal LPI and thus the enable input of the slave delay chain SDL is in the second state and that after the start of the received pulse, the detected light pulse signal LPI and thus the enable input of the slave delay chain SDL is in the first state. The generation of a measured value signal MD as a function of the logical states of the nodes within the slave delay chain SDL after the start of the received pulse and preferably before the end of the received pulse completes the sub-method for determining this measured value, so that this value of the measured value signal MD or of a signal derived therefrom can be used as the measured value of the delay between the light pulse LP and the shutter-on signal SON.

Particularly preferably, the reference clock RCK is generated by means of a quartz oscillator or by means of a MEMS oscillator. The latter can particularly preferably be co-integrated micronically on a substrate or at least housed in a microsystem housing with a device that performs essential parts of the method.

This sub-method can now be extended so that the regulation described above becomes possible again. Therefore, the sub-method can be the steps of detecting the delay between the light pulse LP and a shutter-on signal SON by means of the partial method described above and the additional generation of the Light pulse LP in the manner that the beginning of the light pulse LP depends on the value of the measured value signal MD, to be supplemented. Instead of controlling the light pulse LP, the shutter-on signal (SON) can also be regulated. The sub-method then comprises a sub-method for generating a shutter-on signal (SON) with pulses comprising the steps of detecting the delay between a light pulse LP and the shutter-on signal SON by means of the sub-method described above and generating a pulse on the latter Shutter-on-signal SON in such a way that the beginning of the pulse on the shutter-on signal SON depends on the value of the measured value signal (MD).

The core of a device for carrying out the methods proposed above is thus a device for delaying a signal, here a detected shutter signal SONDI. The proposed device comprises a reference oscillator OSZ, which generates a reference clock RCK. This reference oscillator OSZ is preferably designed as a quartz oscillator or as a MEMS oscillator. The quartz oscillator or the MEMS oscillator is preferably accommodated in the same microsystem housing as the IC of the time-of-flight camera. In the case of a MEMS oscillator, the MEMS oscillator is preferably placed on the same substrate as the rest of the circuit of the time-of-flight camera. Furthermore, the proposed device comprises a DLL (delay-locked loop). The DLL has a phase detector (PD, IDLL). In the example discussed further below, the phase detector provides PD itself a voltage signal, while the loop filter LF requires a current input signal. Therefore, in the example below, the output of the phase detector PD of the DLL is converted into a current output by means of a current source IDLL switchable by the phase detector PD. As such, the phase detector PD of the example below and the switchable current source IDLL may be construed as a single current output phase detector. The phase detector (PD, IDLL) supplies with its phase position measurement a loop filter LF of the DLL. The output of the loop filter LF of the DLL represents the control signal RS of the DLL. In this respect, the transfer characteristic of the loop filter LF is important for the later stability of the control loop. The DLL also has a master delay chain MDL with an input and an output DLO. The delay in the master delay chain MDL of the DLL depends on the control signal RS. The phase detector (PD, IDLL) of the DLL feeds the loop filter LF of the DLL as a function of the phase position of at least one pair from a rising and / or falling edge of the reference clock RCK compared to at least one rising and / or falling edge of the output DLO of the master clock. Delay chain MDL of DLL. Which combination of rising or falling edges is used depends on the design of the phase detector. Also, depending on the design, not every flank must be used. The proposed device further comprises a slave delay chain SDL with an input which is connected in the case discussed here with the detected shutter signal SONDI on the one hand and with at least one output of the slave delay chain SDL or one end of the slave delay chain SDL on the other , In the case discussed here, preferably all the outputs of all special inverters (SI ₁ , SI ₂ ,... SI _(n - ₁₎ , SI _n ) within the slave delay chain SDL are selected from these special inverters (SI ₁ , SI ₂ , .... SI _(n-1) , SI _n ) is used as the output. The delay of the special inverters (SI ₁ , SI ₂ ,... SI _(n-1) , SI _n ) and thus the delay in the slave delay chain SDL in the proposed device depends on the control signal RS of the DLL. As the specific inverter (SI _1, SI ₂ SI .... _(n-1), SI _n) of the slave delay line SDL matchend to the specific inverters (MI _1, MI _2, MI .... _{(n- 1)} , MI _n ) of the master delay chain MDL and to be fabricated on the same semiconductor substrate, the delay time of the slave delay chain SDL is subject to the same thermal fluctuations and operational influences as the delay time of the master delay chain MDL. Furthermore, the control sensitivity of the delay time of a specific inverter (SI ₁ , SI ₂ ,... SI _(n-1) , SI _n ) of the slave delay chain SDL in dependence on the control signal RS is equal to the control sensitivity of the delay time of a specific inverter ( MI ₁ , MI ₂ , .... MI _(n-1) , MI _n ) of the master delay chain MDL in response to the control signal RS. Since the master delay chain MDL is regulated by the DLL control to equal delay as a function of the period of the reference clock RCK, so is the delay of the slave delay chain SDL by the DLL control to the same delay as a function of the period of the reference clock RCK adjusted. Thus, the delay of the slave delay chain is determined only by the period of the reference clock RCK. For this reason, it is particularly useful to use a high-quality oscillator for feeding the reference clock RCK. Especially quartz and MEMS oscillators come into question here.

So that the delay of the slave delay chain is no longer subject to thermal fluctuations, the circuit of the slave delay chain SDL and the circuit of the master delay chain MDL must be thermally coupled to one another. This is done by manufacturing on a common semiconductor substrate.

list of figures

• 1 shows the indirect time-of-flight principle according to the prior art.
• 2 shows the schematic diagram of the clock generation of the proposed device.
• 3 shows the components of the proposed device for measuring the delay.
• 4 shows the slave delay chain SDL and the DLL with the master delay chain MDL.
• 5 shows an exemplary special tri-state inverter, as it can be used in the master delay chain MDL and the slave delay chain SDL.
• 6 shows an exemplary first input circuit ISM1 for optical coupling of the light pulse LP or the scattered light pulse SLP via a photodiode FD.
• 7 shows an exemplary second input circuit ISM2 for the shutter signal path for delay compensation and for use together with the exemplary first input circuit ISM1 6 ,
• 8th shows an exemplary first input circuit ISM1 for electrical coupling of the signal of the electric current through the light emitting diode LED by means of a shunt resistor SR.
• 9 shows an exemplary second input circuit ISM2 for the shutter signal path for delay compensation and for use with the exemplary first input circuit ISM1 8th or off 10 ,
• 10 shows an exemplary first input circuit ISM1 for electrical coupling of the signal of the current through the light emitting diode LED by means of a transformer TR.
• 11 corresponds to the upper part of the 2 with the difference that the measurement signal MD and the control signal RS are generated in the synchronous optical receiver SOR and are fed back to the central clock unit CCU of the proposed time-of-flight camera to determine the relative time position of the pulses on the lamp-on signal LON and the pulses on the shutter-on signal SON with the goal of synchronicity to regulate.
• 12 shows an exemplary device for delaying the pulses on the bulb-on signal LON and the pulses on the shutter-on signal SON against the pulses on the bulb-on signal LON in response to the measured value signal MD by means of a controllable clock unit delay chain CDL from special inverters (CI ₁ , CI ₂ , ..... CI _(n-1) , CI _n ) and a multiplexer MUX.
• 13 shows the stabilized with the DLL and an oscillator OSZ slave delay line SDL the 4 separately.

Description of the figures

The invention will now be explained in more detail with reference to FIGS. On 1 has already been discussed in connection with the prior art.

2 shows the basic circuit of the clock generation of a time-of-flight camera. With a central clock unit ( CCU ), the control signals ( LON . SON ) for the light pulse LP , the light pulse on signal LON, and for the shutter, the shutter-on signal SON , generated. At the output of the clock generation ( CCU ) are these control signals ( LON . SON ) are generally synchronous in time without regulation.

On the camera IC are the driver SD for the shutter as well as a preliminary stage for the preferably IC -external driver of the light source for generating the light pulse LP , preferably for the laser or for the LED ( LD ). For supplying the light source for generating the light pulse LP, preferably a light emitting diode ( LED ) or a laser, with electrical energy is usually required a separate from the rest of the electrical circuit power driver, since the transmission currents of the lamp, preferably the light emitting diode or the laser, are generally at some A or some 10A, and on an integrated circuit of Time -of-flight camera are no longer useful without thermal problems and cost problems due to the necessary chip area to handle. In the following, this preferably microelectronic integrated part of the time-of-flight camera with IC designated.

Both the internal, in the IC integrated drivers, as well as the external, located outside the IC drivers lead to undesirable, typically unequal respective time delays, the distance measurement by a corresponding asynchronism of the first measuring pulse MPQ1 and second measuring pulse MPQ2 with the light pulse LP distort. The output LOND the IC internal driver circuit LD for the light source, preferably for the laser or for the LED , is thus opposite the original bulb-on signal LON the central clock unit CCU delayed the proposed time-of-flight camera. The exit SOND the driver circuit ( SD ) for the shutter is opposite to the shutter-on signal SON the central clock unit CCU the proposed time-of-flight camera also, but typically just delayed differently. Thus, a delay error is generated here. That of the actual lamp, so typically the laser or the light emitting diode ( LED ), transmitted light pulse LP is opposite to the signal at the output LOND the IC internal driver circuit LD for the light source, preferably the laser or the light emitting diode, delayed again.

Thus, the said, construction-related temporal delay error results Te that addresses distance measurement errors at the specific distance d reflected.

In the above description, it is irrelevant whether the first or the second shutter or both shutters are affected by such delay errors, and therefore the description above speaks of a shutter only for the sake of simplicity. The above applies to both shutters and thus to the determination of both charge quantities, the first charge amount Q1 and the second charge amount Q2 ,

The determination of the design-related time delay error Te is the subject of the proposed method and device.

The course of the laser pulse LP is through a suitable first input circuit ISM1 as a digitized, detected light pulse signal LPI from the transmission signal LPS of the light pulse LP determined. To compensate for the time delay between the temporal behavior of the transmission signal LPS of the light pulse LP and the detected light pulse signal LPI in this first input circuit ISM1 is a preferably matching and thus circuit technology and layout technically the same second input circuit ISM2 also for the same amount time delay of the output signal SOND the driver circuit ( SD ) for the respective shutter to the detected shutter signal Sondi used.

The delay between the transmission signal LPS of the light pulse LP and the output signal SOND the driver circuit ( SD ) for the shutter is measured as a measured value signal MD by a delay measuring device DEC determined.

Because the light pulse LP generally by the power driver external to the IC PLD for controlling the light source LED is delayed more than the output signal SOND the driver circuit ( SD ) for each shutter forms the respective shutter signal SOND the start signal and the transmission signal LPS of the light pulse LP forms the stop signal for the measurement of the time delay between the transmission signal LPS of the light pulse LP and the output signal SOND of the driver circuit ( SD ) for the shutter in the form of a measured value signal MD through the delay measuring device DEC ,

The delay measuring device DEC is in 4 shown schematically in more detail and will be further explained below. The circuit of 4 consists essentially of three parts.

First, the in 4 schematically illustrated delay measuring device DEC a DLL (delay-locked loop) for generating the control value of a control signal RS for compensation of temperature, operating voltage, manufacturing and other influences on the running time in a master delay chain MDL within the integrated circuit in which the proposed device is made. The DLL Controls the delay of the master delay chain MDL via a control signal RS so that the phase of the output signal DLO the master delay chain MDL with the phase of a reference clock RCK matches. The reference clock RCK is preferably generated by means of a quartz oscillator or a co-integrated with other circuit parts MEMS oscillator. To do this, a phase detector compares PD as is well known in the art, the phase of the arrival of the edges of the reference clock RCK and the edges of the output signal DLO the master delay chain MDL of the DLL , Depending on the thus determined phase position he controls in the in 4 Example shown a switchable power source IDLL that have a positive or negative current depending on the drive through the phase detector PD supplies. This stream is through a loop filter LF , which is symbolized here by a capacity, in the already mentioned control signal RS whose voltage level is the delay of the master delay chain MDL and the slave delay chain SDL. Other implementations of the phase detector PD and the loop filter LF , as well as the control of the loop filter LF through the phase detector PD are conceivable.

Second, the in 4 schematically illustrated delay measuring device DEC the already mentioned slave delay chain SDL. The delay of the slave delay chain SDL is, as already indicated, by means of the DLL certain control signal RS certainly. Because this control signal RS so to the reference clock RCK coupled is that the time delay in the master delay chain MDL in a fixed, typically integer ratio to the period of the reference clock RCK stands, so that the time delay in the slave delay chain SDL is in a fixed ratio to the period of the reference clock RCK , It is particularly advantageous if the reference clock RCK has the most exact 50% duty cycle possible. Depending on the detected light pulse signal LPI Now the signal in the slave delay chain SDL is either propagated (= transported further) or frozen. The detected shutter signal Sondi becomes active first. The corresponding edge of the detected shutter signal Sondi can therefore still run into the slave delay chain SDL, so that the first node within the slave delay chain can still change their logical state. How many are depends on the time delay of the temporal edge of the detected shutter signal Sondi to the edge of the detected light pulse signal LPI from. While the edge of the detected shutter signal Sondi now passing through the delay chain, the detected light pulse signal LPI which arrives later, active and freezes the edge of the detected shutter signal Sondi during this movement in the slave delay chain SDL. The master delay chain MDL is made of special inverters ( MI ₁ . MI ₂ , ..... MI _(n-1) . MI _n ) built up. The slave delay chain SDL ( SI ₁ . SI ₂ , ..... SI _(n-1) . SI _n ) is made up of the same special inverters. All these special inverters (master inverters ( MI ₁ . MI ₂ , ..... MI _(n-1) . MI _n ) like slave Inverter ( SI ₁ . SI ₂ , ..... SI _(n-1) . SI _n )) are designed to match each other. This ensures that at the same value of the control signal RS each of the inverters ( MI ₁ . MI ₂ , ..... MI _(n-1) . MI _n . SI ₁ . SI ₂ , ..... SI _(n-1) . SI _n ) of the master delay chain MDL and the slave delay chain SDL should have the same partial time delay in each intended operating position. It should be mentioned that the special inverters (master inverters MI ₁ . MI ₂ , ..... MI _(n-1) . MI _n ) like slave inverters ( SI ₁ . SI ₂ , ..... SI _(n-1) . SI _n )) as an enable input EN Have designated input, which prevents the freezing of the signal in the respective delay chain and further transport. In the case of the slave delay chain SDL is the respective enable input EN the respective slave inverter ( SI ₁ . SI ₂ , ..... SI _(n-1) , SI _n ) in the example of 4 with the detected light pulse signal LPI connected and thus allows the already described freezing of the incoming shutter signal Sondi , In the case of the master delay chain MDL is the respective enable input EN the respective master inverter ( MI ₁ . MI ₂ , ..... MI _(n-1) . MI _n ) connected in the way with a fixed potential that no freezing of the signal in the master delay chain MDL takes place.

Third, the in 4 schematically illustrated delay measuring device DEC a readout circuit ROC , This detects the values at the outputs of the slave inverters ( SI ₁ . SI ₂ , ..... SI _(n-1) , SI _n ) of the slave delay chain (SDL) and determines the position of the incoming edge of the detected shutter signal Sondi within the slave delay chain SDL after freezing by the detected light pulse signal LPI , The readout circuit ROC generates the measured value signal from this MD whose value is the delay between the detected light pulse signal LPI and the detected shutter signal Sondi represents for the shutter. The measured value signal MD may be digital, binary or analog or a data bus with a data word as content whose logical value corresponds to the measured value.

This measured value in the form of the measured value signal MD In the following, for example, it can be used to correct the determined measured values for the distance d or for controlling the shutter-on signal SON in the central clock unit CCU be used (see also 11 and 12 ). For this purpose, the measured value signal MD to the central clock unit CCU (please refer 2 ) together with the control signal RS to be led back. It is particularly advantageous when in the central clock unit CCU a third clock unit delay chain CDL (please refer 12 ), which is the bulb-on signal LON to the shutter-on signal SON delayed. The clock unit delay chain CDL consists again preferably of special inverters ( CI ₁ . CI ₂ , ..... CI _(n-1) , CI _n ) of the clock unit delay chain CDL mating again with the special master inverters ( MI ₁ . MI ₂ , ..... MI _(n-1) . MI _n ) of the master delay chain MDL and the special slave inverters ( SI ₁ . SI ₂ , ..... SI _(n-1) . SI _n ) of the slave delay chain SDL should be made. The delay of this clock unit delay chain CDL is again on the already mentioned control signal RS set. The enable input EN the special inverter ( CI ₁ . CI ₂ , ..... CI _(n-1) . CI _n ) of the clock unit delay chain CDL is in the way with a fixed potential (in the 12 as an example the supply voltage Vbat ), so that no freezing of the signal in the clock unit delay chain CDL takes place, but that the signal in the clock unit delay chain CDL is continuously transported from node to node in the chain of special inverters within the delay chain. By means of a multiplexer MUX that of the measured value signal MD or a signal derived therefrom, then the appropriate delay of the shutter-on signal SON at the outputs of special inverters ( CI ₁ . CI ₂ , ..... CI _(n-1) . CI _n ) of the clock unit delay chain CDL with a suitable design of the control of the multiplexer MUX tapped and used with it. In particular, with suitable control of the multiplexer MUX Stability can be achieved in this control loop.

An exemplary special inverter, as used for the delay chains ( MDL , SDL, CDL ) Can be used is in 5 exemplified. It is an exemplary CMOS inverter with a first transistor T1 which is typically a P-channel MOS transistor and a second transistor T2 which is also typically a P-channel transistor and a third transistor T3 which is typically an N-channel transistor, and a fourth transistor T4, which is typically an N-channel transistor. The transistors are connected in series, with the two P-channel transistors ( T1 . T2 ) between the connection for the control signal RS and the output O and the two N-channel transistors ( T3 . T4 ) between the output O and the connection for the reference potential GND are located. In the example of 5 are the first transistor T1 and the fourth transistor T4 connected with its control electrode to the input. The potential at the gate of a transistor controls the current flow between the other two terminals of the transistor therethrough. This is either the first transistor T1 or the fourth transistor T4 conductive, whereby the inverting effect of the circuit of 5 is achieved. The second transistor T2 is with its control electrode with the enable input EN connected. The third transistor T3 is with its control electrode via an auxiliary inverter INV with the enable input EN connected. It may be useful to have this auxiliary inverter INV central to all auxiliary inverters INV the slave delay chain SDL and instead make a negated enable input ENQ additionally in each special inverter ( MI ₁ . MI ₂ , ..... MI _(n-1) . MI _n , SI ₁ , SI ₂ , ..... SI _(n-1) . SI _n . CI ₁ . CI ₂ , ..... CI _(n-1) . CI _n ). In this case, in the case of the slave delay chain SDL, the output of the central inverter would be connected, which would then receive the detected light pulse signal LPI instead of the auxiliary inverters INV would invert. For the special inverters ( MI ₁ , MI ₂ , ..... MI _(n-1) . MI _n . CI ₁ . CI ₂ , ..... CI _(n-1) . CI _n ) of the other delay chains ( MDL . CDL ) would this negated enable input ENQ then also placed on a fixed potential in the way that the respective third transistor T3 the respective special inverter ( MI ₁ . MI ₂ , ..... MI _(n-1) . MI _n . CI ₁ . CI ₂ , ..... CI _(n-1) , CI _n ) of these delay chains ( MDL . CDL ) then always leads. The second transistor T2 and the third transistor T3 prevent, in the off state, a recharge of the parasitic capacitance of the output node of the output O of the respective inverter ( MI ₁ . MI ₂ , ..... MI _(n-1) . MI _n . SI ₁ . SI ₂ , ..... SI _(n-1) , SI _n . CI ₁ . CI ₂ , ..... CI _(n-1) . CI _n ) and thus freezes the logic state of the output of the respective inverter and thus the entire affected delay chain.

The switching state of the slave delay chain SDL is preferably read out and stored digitally by the read-out circuit ROC. Because there are usually many light pulses for an image acquisition LP are required, an averaging or an integrating low-pass filtering offers. As a result, even with a limited number of stages (number of special inverters) in the slave delay chain SDL (a few tens of steps), a very fine resolution of the delay between the detected light pulse signal is obtained LPI and the detected shutter signal Sondi ,

An example of a first input circuit ISM1 for an optical coupling of the light pulse LP shows 6 , At the same time the light pulse becomes LP by means of a photodiode FD optically recorded. For this purpose, for example, the scattered light of the lamp, preferably the laser or the LED , if this as a light source for generating the light pulse LP be used. Preferably, these are housed with the photoelectric elements of the camera IC in a housing, which typically has an optical window, on which then these variations arise. The one from the light pulse LP resulting scattered light pulse SLP can thus through the photodiode FD or another suitable photoelectric device is detected and into a digital signal, eg the detected light pulse signal LPI , be implemented. Due to the high transmission power (some 10W) that is typically used to generate the light pulse LP used bulbs are obtained even if only 1/1000 of the transmitted light on the photodiode FD directs, very strong photocurrents that can be detected with a simple circuit.

The example here in the 6 illustrated first input circuit ISM1 includes the photodiode FD, the fifth transistor T5 which is a bipolar transistor here, a source of quiescent current IB1 and a resistance to work RV1 , The working resistance RV1 is to the supply voltage Vbat connected. The other link of working resistance RV1 is to the collector of the fifth transistor T5 connected. The emitter of the fifth transistor T5 is at the output of the quiescent current source IB1 connected. To the emitter of the fifth transistor T5 is the cathode of the photodiode FD connected. The anode of the photodiode FD is with the reference potential GND connected. The photodiode FD becomes with the scattered light pulse SLP of the light pulse LP irradiated when this occurs. This creates the photodiode FD an additional photocurrent, which is the potential of the emitter of the fifth transistor T5 raises and thus the current flow through the fifth transistor T5 , diminished, reducing the output, the detected light pulse signal LPI , in this example is raised. The base of the fifth transistor T5 is at a constant potential VB opposite the reference potential GND held.

The example here in the 7 illustrated second input circuit ISM2 includes the sixth transistor T6 which is a bipolar transistor here, a source of quiescent current IB2 and a working resistor RV2. The load resistor RV2 is connected to the supply voltage Vbat connected. The other terminal of the load resistor RV2 is connected to the collector of the sixth transistor T6 connected. The emitter of the sixth transistor T6 is at the output of the quiescent current source IB2 connected. To the emitter of the sixth transistor T6 is the output signal SOND the driver circuit ( SD ) connected to the shutter. A positive pulse on the output signal SOND the driver circuit ( SD ) for the shutter raises the potential of the emitter of the sixth transistor T6 and thus reduces the flow of current through the sixth transistor T6 , whereby the output, the captured shutter signal Sondi , in this example is raised. The base of the sixth transistor T6 is at a constant potential VB opposite the reference potential GND held.

Instead of the optical coupling by means of a photodiode FD Alternatively, the current through the respective lighting means for generating the light pulse LP , For example, a laser or a light emitting diode, for generating the detected light pulse signal LPI (Used as a stop signal for the slave delay chain SDL) are used. In this case it is assumed that current and light pulse LP (almost) occur at the same time. Such use is therefore only approximately accurate. For evaluation of the electrical current through the lamp LED offers the use of an electrical shunt resistor SR in series with the light source LED at.

8th shows a principal circuit in which the shunt resistor SR Capacitive via a coupling capacity CK to the first input circuit ISM1 is coupled. The base of the fifth transistor T5 this is about a resistor R1 energized. The emitter of the fifth transistor T5 is directly connected to the reference potential GND connected. The collector of the fifth transistor T5 is about the working resistance RV1 with the supply voltage Vbat connected. The collector of the fifth transistor T5 is also the receipt of a latch LT1 connected. Its output forms the output of the thus modified input circuit ISM1 in the form of the detected light pulse signal LPI , As soon as current flows through the light source, the voltage increases and the fifth transistor increases T5 leads stronger. The level tilts and the latch LT1 saves the event. Before sending a new light pulse LP should the latch LT1 preferably reset.

In this case, the second input circuit must be ISM2 be changed because the delays of the first input circuit ISM1 and the second input circuit ISM2 should be the same.

9 shows the second input circuit ISM2 in this case. The base of the sixth transistor T6 this is about a resistor R1 from a reference voltage source VB energized. The emitter of the sixth transistor T6 is directly related to the reference potential GND connected. The collector of the sixth transistor T6 is across the load resistor RV2 with the supply voltage Vbat connected. The collector of the sixth transistor T6 is further connected to the input of a latch LT2. Its output forms the output of the thus modified second input circuit ISM2 in the form of the detected shutter signal. Once the output signal SOND the driver circuit ( SD ) shows an increased voltage pulse for the shutter, the sixth transistor conducts T6 stronger. The level tilts and the latch LT2 saves the event. Before sending a new light pulse LP should the latch LT2 preferably reset.

The high current through the bulb LED For example, by a laser or a light emitting diode of some 10A and the steep rise time of some ns also allow an inductive coupling of the light pulse signal LPS for detecting the current through the lighting means LED , wherein the coupling inductances can be very small. Possibly. Already the parallel guidance of interconnects as transformer TR to achieve a sufficient coupling.

11 shows such a construction schematically. A transformer TR, which, as already mentioned, may possibly only consist of lines routed in parallel, couples instead of the coupling capacity CK of the 8th now the signal in the first input circuit ISM1 one. The rest of the procedure is analog.

Instead of the current signal and the transmission signal LPS for the generation of the detected light pulse signal LPI be used. However, this is often not so well correlated with the actual light signal as the previously discussed signals.

The proposed device and the proposed method can therefore be summarized so that a circuit for measuring the time delay between the emission of a light pulse LP and operating an electric shutter for a time-of-flight camera (camera line) by means of a shutter-on signal SON or derived signals ( SOND . Sondi ).

The circuit contains input circuits ( ISM1 . ISM2 ) and a slave delay chain (SDL) controlled with respect to a reference clock RCK in its time delay. Therefore, using a crystal oscillator or MEMS oscillator to generate this reference clock RCK, this high-Q delay chain can measure the delay.

The delay measuring device DEC to measure the delay Line operates according to a master-slave principle using a master delay chain MDL and a slave delay chain SDL and is provided with special inverters ( SI ₁ . SI ₂ , .... SI _(n-1) . SI _n . MI ₁ . MI ₂ , ... MI _(n-1) . MI _n ) are constructed as tri-state gate structures ( 4 and 5 ), by means of an enable input EN in each case a tri-state state can be brought, which respectively freezes the logic level of the respective output node of the respective special inverter within the respective delay chain and signal propagation through the respective delay chain (SDL, MDL ) stops.

By averaging many measurements in the readout circuit ROC , which is typically done by an integrating low-pass filtering, a high resolution of the measured delay is achieved. The readout circuit ROC generates a measured value signal MD ,

With the measured delay in the form of the measured value signal MD a calibration of the distance is unnecessary or simplified or improved.

The shutter-on signal SON , can then with the help of another clock unit delay chain CDL and with the aid of the measured value signal thus determined MD , as well as with the help of the control signal RS by appropriate delay from the bulb-on signal LON for controlling the bulb LED be generated and readjusted.

If the camera contains components for setting the shutter / light source delay, an optimal time sequence can be achieved by using the measured delay for readjustment.

For the input circuits ( ISM1 . ISM2 ) different principles are possible. These are listed here for the sake of completeness.

13 shows the with the DLL and an oscillator OSZ stabilized slave delay line SDL the 4 separately.

glossary

Time-of-flight camera

For the purposes of this disclosure, time-of-flight cameras are cameras based on the principle of light transit time measurement. These indirectly measure the transit time between the emitted light pulse LP and the received light signal, the reflected light pulse RP , for each pixel or for groups of pixels of the camera. As a result, in addition to the actual brightness image, which can also contain spectral information, a pixel map with distance information or transit time information is also generated.

Matchend

• Halbleiterbauelemente (Widerstände, Transistoren , Kondensatoren) in bevorzugt ganzzahligen Verhältnissen konstruiert werden
• und durch eine dem Verhältnis entsprechende unterschiedliche Anzahl an gleich konstruierten Subbauelementen realisiert werden.

Matching refers to particular layout techniques for reducing the variation of differences between microelectronic structures within a microelectronic circuit. A good overview can be found for example under the link http://avlsi.ini.uzh.ch/classwiki/doku.php. There chapter 5 (downloadable under http://avlsi.ini.uzh.ch/classwiki/lib/exe/fetch.php?id=spring2008%3Astart&cache=cache&medi a = spring2008: 5-layouttechniquestransistormismatch.pdf) describes the matching Techniques very good. Matching exists in particular when:

• Semiconductor devices (resistors, transistors, capacitors) are constructed in preferred integer ratios
• and realized by a different number of the same constructed sub-components corresponding to the ratio.

Possibly. non-integer residual values are added to or subtracted from a single subcomponent if an integer ratio can not be achieved. However, this does not represent optimal matching.

Furthermore, the same sub-components that are to match, positioned as close to each other on the integrated circuit and aligned as possible. Preferably, more complex, similar structures to match are scrambled with respect to the sub-components.

These measures ensure that all sub-components in production are manufactured with almost the same errors. And this prefers then lift away.

LIST OF REFERENCE NUMBERS

CCU

central clock unit of the proposed device.

CDL

Clock unit delay chain in the central clock unit CCU for the controlled delay of the shutter-on-signal ( SON ).

CI ₁

first special inverter of the clock unit delay chain CDL ,

CI ₂

second special inverter of the clock unit delay chain CDL ,

CI _(n-1)

(n-1) -ter special inverter of the clock unit delay chain CDL ,

CI _n

nth special inverter of the clock unit delay chain CDL ,

CK

Coupling capacitance.

d

Distance of the object or object point.

DEC

Delay measuring device.

DLL

Delay locked loop.

DLO

Output signal of the master delay chain MDL of the DLL ,

EN

Enable input of the respective special inverter ( MI ₁ . MI ₂ , ..... MI _(n-1) . MI _n . SI ₁ . SI ₂ , ..... SI _(n-1) . SI _n . CI ₁ . CI ₂ , ..... CI _(n-1) . CI _n ) of the respective delay chain ( MDL , SDL, CDL ).

ENQ

negated enable input of the respective special inverter ( MI ₁ . MI ₂ , ..... MI _(n-1) . MI _n , SI ₁ , SI ₂ , ..... SI _(n-1) . SI _n . CI ₁ . CI ₂ , ..... CI _(n-1) . CI _n ) of the respective delay chain ( MDL , SDL, CDL ) (only with central inversion).

FD

Photodiode.

GND

Reference potential.

IB1

Quiescent current source in the first input circuit ISM1 ,

IB2

Quiescent current source in the second input circuit ISM2 ,

IC

microelectronic integrated part of the time-of-flight camera.

IDLL

Switchable power source in the DLL , The switchable current source provides a positive or negative current as determined by the phase detector PD determined phase position.

INV

Auxiliary inverter of the respective special inverter ( MI ₁ . MI ₂ , ..... MI _(n-1) . MI _n . SI ₁ . SI ₂ , ..... SI _(n-1) , SI _n , CI ₁ , CI ₂ , ..... CI _(n-1) . CI _n ) of the respective delay chain ( MDL , SDL, CDL ). The auxiliary inverter inverts the enable signal at the enable input EN ,

ISM1

first input circuit (see 3 ).

ISM2

second input circuit (see 3 ).

ISMO1

Output of the first input circuit ISM1 ,

ISMO2

Output of the second input circuit ISM2 ,

LED

Led. Instead of a light emitting diode, a laser diode is preferably used. In general, can LED be understood in the text as a light source, which is suitable for emitting the required light pulses with the required intensity gradient.

LD

IC internal driver circuit for the laser or the LED ,

LON

Illuminant on signal (laser on signal or if necessary LED -an signal).

LF

Loop filter the DLL Regulation. The loop filter is passed through the phase filter PD and in this example via the switchable current source in the DLL IDLL controlled and generates the control signal RS ,

LP

Light pulse emitted by the light source, eg a light-emitting diode ( LED ) or a laser diode is emitted. Other light sources - eg electroluminescent components, plasma discharge sources, etc. - are conceivable.

LPI

detected light pulse signal. The detected laser pulse signal is, for example, by means of the first input circuit ISM1 determined.

LPS

Transmission signal for the light pulse LP ,

LT1

Latch.

LT2

Latch.

MD

Measurement signal for the delay between the light pulse LP or the scattered light pulse SLP or the transmission current through the lighting means during the light pulse LP or the transmission signal LPS of the light pulse LP on the one hand and the output signal SOND the driver circuit ( SD ) for the shutter on the other hand.

MDL

Master delay chain of DLL ,

MI ₁

first special inverter of the master delay chain MDL ,

MI ₂

second special inverter of the master delay chain MDL ,

MI _(n-1)

(n-1) -ter special inverter of the master delay chain MDL ,

MI _n

nth special inverter of the master delay chain MDL ,

MP1

first measuring pulse of the first measuring signal MQ1 , while the first charge amount Q1 , which is generated by the photoelectric element upon incidence of light, is collected in the first capacitance.

MP2

second measuring pulse of the second measuring signal MQ2 , while the second charge quantity Q2 which is generated by the photoelectric element upon incident light, is collected in the second capacitance.

MQ1

first measuring signal for opening the first shutter for measuring the first charge amount Q1 , The first measurement signal is a shutter-on signal for the first shutter.

MQ2

second measuring signal for opening the second shutter for measuring the second charge amount Q2 , The second measurement signal is a shutter-on signal for the second shutter.

MUX

Multiplexer.

OSZ

Oscillator. The oscillator is preferably a quartz oscillator or a MEMS oscillator. A MEMS oscillator is preferred along with the master delay path MDL and the slave delay line SDL and the other circuit parts on the same semiconductor substrate or underlaid at least in the same microsystem housing.

PD

Phase detector.

PLD

outside of the IC located power driver for controlling the bulb, preferably a laser or a light emitting diode ( LED ).

Q1

first charge amount collected in the first capacitor during opening of the first shutter after being collected in the photoelectric element.

Q2

second amount of charge accumulated during opening of the second shutter in the second capacitance after being collected in the photoelectric element. There are known from the prior art devices and methods that use the first capacity as a second capacity by a time instead of a space multiplex.

R1

Resistance.

R2

Resistance.

RCK

Reference clock.

ROC

Readout circuit.

RP

reflected pulse. The reflected pulse represents the light signal, which the photoelectric element by the reflection of the light pulse LP received at the objects and / or the object points.

RS

Control signal. The value of the control signal represents the control variable with which the master delay chain MDL of the DLL is controlled by the controller so that a phase shift of the reference clock RCK in the way that the phase detector PD essentially identifies phase equality. This control signal is for the control of the slave delay chain SDL and possibly for the control of the clock unit delay chain CDL used.

RV1

Working resistor in the first input circuit ISM1 ,

SD

Driver circuit for the shutter.

SI ₁

first special inverter of the slave delay chain SDL.

SI ₂

second special inverter of the slave delay chain SDL.

SI _(n-1)

(n-1) -ter special inverter of slave delay chain SDL.

SI _n

nth special inverter of the slave delay chain SDL.

SLP

Scattered light pulse.

SON

Shutter-on signal.

SOND

Output signal of the driver circuit ( SD ) for the shutter.

Sondi

captured shutter signal. The detected shutter signal is different from the output signal SOND the driver circuit ( SD ) for the shutter by passing it through a second input circuit ISM2 in the same way compared to the output signal SOND the driver circuit ( SD ) is delayed for the shutter, such as the detected light pulse signal LPI opposite to the transmission signal LPS of the light pulse LP or with respect to the light pulse LP or to the electric current through the lamp LED for generating the light pulse LP through the first input circuit ISM2 is delayed. Apart from this delay, the detected shutter signal should otherwise be the output signal SOND the driver circuit ( SD ) correspond to the shutter.

SOR

synchronous optical receiver (typically in the IC ).

SR

Shunt resistor.

T1

first transistor of the respective special inverter ( MI ₁ . MI ₂ , ..... MI _(n-1) . MI _n . SI ₁ . SI ₂ , ..... SI _(n-1) . SI _n . CI ₁ . CI ₂ , ..... CI _(n-1) . CI _n ) of the respective delay chain ( MDL , SDL, CDL ).

T2

second transistor of the respective special inverter ( MI ₁ . MI ₂ , ..... MI _(n-1) . MI _n . SI ₁ . SI ₂ , ..... SI _(n-1) . SI _n . CI ₁ . CI ₂ , ..... CI _(n-1) . CI _n ) of the respective delay chain ( MDL , SDL, CDL ).

T3

third transistor of the respective special inverter ( MI ₁ . MI ₂ , ..... MI _(n-1) . MI _n . SI ₁ . SI ₂ , ..... SI _(n-1) . SI _n . CI ₁ . CI ₂ , ..... CI _(n-1) . CI _n ) of the respective delay chain ( MDL , SDL, CDL ).

T4

fourth transistor of the respective special inverter ( MI ₁ . MI ₂ , ..... MI _(n-1) . MI _n . SI ₁ . SI ₂ , ..... SI _(n-1) . SI _n . CI ₁ . CI ₂ , ..... CI _(n-1) . CI _n ) of the respective delay chain ( MDL , SDL, CDL ).

T5

fifth transistor in the first input circuit ISM1 ,

T6

sixth transistor in the second input circuit ISM2 ,

td

Time delay between the beginning of the transmission of the light pulse LP and the arrival of the start of the reflected light signal as a reflected pulse RP on the photoelectric element.

Te

construction-related time delay error.

TMP1

first time measuring pulse duration of the first measuring pulse MP1 of the first measurement signal MQ1.

TMP 2

second time measuring pulse duration of the second measuring pulse MP2 of the second measurement signal MQ2 ,

Ttrig

temporal light pulse length.

VB

constant potential.

Vbat

Supply voltage.

List of cited literature

• DE 10 2009 020 218 B3 .
• DE 10 253 437 B4 .
• US 6,373,557 B1 .
• EP 1 040 366 B1 .
• EP 2 191 298 B1 .
• US 6,452,666 B1 .
• US Pat. No. 7,060,957 B2 .
• US Pat. No. 7,095,487 B2 .
• US Pat. No. 7,683,954 B2 .
• US Pat. No. 7,947,939 B2 .
• US 8 638 425 B2 ,

Claims (1)

Device for delaying a signal (SONDI) and generating a measured value signal (MD) - with a reference oscillator (OSZ), which generates a reference clock (RCK) and - with a DLL, - wherein the DLL has a phase detector (PD, IDLL) and wherein the phase detector (PD, IDLL) feeds a loop filter (LF) of the DLL, and wherein the output of the loop filter (LF) of the DLL is a control signal (RS) and wherein the DLL has a master delay chain (MDL) and wherein Master delay chain (MDL) of the DLL has an input and an output (DLO) and - wherein the delay in the master delay chain (MDL) of the DLL depends on the control signal (RS) and - wherein the phase detector (PD, IDLL) of the DLL the loop filter (LF) of the DLL as a function of the phase position of at least one pair spe from a rising edge of the reference clock (RCK) compared to at least one rising edge of the output (DLO) of the master delay chain (MDL) or • is fed from a rising edge of the reference clock (RCK) compared to at least one falling edge of the output (DLO) of the master delay chain (MDL) of the DLL or • from a falling edge of the reference clock (RCK) compared to at least one feeding the rising edge of the output (DLO) of the master delay chain (MDL) of the DLL or • feeding from a falling edge of the reference clock (RCK) compared to at least one falling edge of the output (DLO) of the master delay chain (MDL) of the DLL and - having a slave delay chain (SDL) having an input (SONDI) and at least one output, - the slave delay chain (SDL) having nodes (O), and - wherein the delay of transporting logical information from node to node in the slave delay chain (SDL) depends on the control signal (RS) of the DLL and - the slave delay chain (SDL) has an enable input (EN), • the nodes of the slave delay chain (SDL) freezes when it is in a first logical state, and • allows the transport of logical information from node to node within the slave delay chain SDL when it is in a second logical state, and - Slave delay chain (SDL) and the master delay chain (MDL) are thermally coupled together and - with a read-out circuit (ROC), • depending on the values at the nodes (O) of the slave delay chain (SDL) a measured value signal ( MD), • whose value represents the delay between a second signal (LPI) at the enable input (EN) and the signal (SONDI).

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