DE102016123178A1 - Encryption device for encrypting a data packet - Google Patents

Abstract

The invention relates to an encryption device (100) for encrypting a data packet. The encryption device (100) comprises a network interface (101), which is designed to receive the data packet via a communication network, a circuit (103), which is designed to link the received data packet with a cryptographic key in order to obtain an encrypted data packet , and a bus interface (105) configured to communicate with a data processing device via a communication bus, wherein the bus interface (105) is adapted to store the encrypted data packet in a memory of the data processing device by means of a memory direct access.

Description

The present invention relates to the field of cryptography, in particular for tapping and manipulation protected transmission of a data packet over untrusted hardware components and communication buses.

Field Programmable Gate Arrays (FPGAs) are programmable electronic devices that can be configured at runtime. If an FPGA is used in conjunction with a data processing device, then this is usually connected via a communication bus to a processor of the data processing device. In order to be able to communicate via the communication bus using a predefined bus protocol, there are ready-made design components, so-called IP cores, which can be used in the design of the configuration of the FPGA in order to implement the bus protocol. The building blocks are usually considered untrusted because their source code is mostly unknown. However, a separate implementation of a bus protocol for an FPGA is very expensive.

Analogously, the design of application-specific integrated circuits (ASICs) typically takes place. Here, too, IP cores can be used to implement a bus protocol. The only difference is that the configuration is not loaded dynamically, but is permanently potted in the ASIC.

This has the disadvantage that confidential data packets can be recorded or removed, for example, through a backdoor in untrusted IP cores.

In the publication A. Waksman, S. Sethumadhavan, "Silencing Hardware Backdoors", IEEE Symposium on Security and Privacy, 2011, pp. 49-63 describes an approach for encrypting input data from hardware components.

It is an object of the present invention to provide an efficient concept for tapping and tamper-resistant transmission of a data packet over untrusted hardware components and communication busses.

This object is solved by the features of the independent claims. Advantageous forms of further development are the subject of the dependent claims, the description and the figures.

The invention is based on the finding that the above object can be achieved by encrypting a data packet and a direct memory access (DMA) to a memory of a data processing device for storing the encrypted data packet. Consequently, the data packet can also be transmitted to the data processing device tapping and manipulation-protected using untrusted IP cores. The encryption can for example be done using a separate IP core. By way of example, the data processing device can read out and decrypt the encrypted data packet from the memory using a program code in the form of a software driver.

This ensures that confidential data packets can not be recorded or routed through a backdoor in untrusted IP cores, for example.

According to a first aspect, the invention relates to an encryption device for encrypting a data packet. The encryption device comprises a network interface configured to receive the data packet via a communication network, a circuit configured to associate the received data packet with a cryptographic key to obtain an encrypted data packet, and a bus interface that is configured to communicate with a data processing device via a communication bus, wherein the bus interface is adapted to store the encrypted data packet by means of a direct memory access in a memory of the data processing device.

According to one embodiment, the circuit comprises a memory in which the cryptographic key is stored. This provides the advantage that the cryptographic key for encrypting the data packet can be provided efficiently. For example, the cryptographic key may be permanently inserted into memory during synthesis of the circuit.

According to one embodiment, the circuit is configured to combine the received data packet with the cryptographic key using a block cipher algorithm, in particular an Advanced Encryption Standard (AES) encryption algorithm. However, the linking can also be done using a suitable stream cipher algorithm. This provides the advantage that an efficient algorithm for encrypting the data packet can be used.

According to one embodiment, the communication network is an Ethernet communication network. This provides the advantage that the data packet can be efficiently provided.

According to one embodiment, the communication bus is a Peripheral Component Interconnect (PCI) communication bus. This achieves the advantage that the encrypted data packet can be efficiently transferred to the memory of the data processing device.

According to one embodiment, the communication bus is a Peripheral Component Interconnect Express (PCIe) communication bus. This achieves the advantage that the encrypted data packet can be efficiently transferred to the memory of the data processing device.

According to one embodiment, the encryption device, in particular the network interface, the circuit and / or the bus interface, is implemented by means of a Field Programmable Gate Array (FPGA) or by means of an Application-Specific Integrated Circuit (ASIC). The encryption device, in particular the network interface, the circuit and / or the bus interface, can also be implemented by means of a microcomputer or a system-on-chip (SoC). Thereby, the advantage is achieved that the encryption device can be realized efficiently.

The network interface, the circuit and / or the bus interface can be implemented, for example, using IP cores. In this case, untrusted IP cores for the implementation of the bus interface and dedicated IP cores for the implementation of the network interface and / or the circuit can be used.

According to one embodiment, the encryption device comprises an encryption unit and a network card, wherein the encryption unit comprises the network interface and the circuit, and wherein the network card comprises the bus interface. This provides the advantage that separate components can be used to implement the encryption device.

According to one embodiment, the encryption unit and the network card are configured to communicate with one another via a further communication network. This has the advantage that the encryption unit and the network card can be efficiently connected to each other. The further communication network may be, for example, another Ethernet communication network.

According to a second aspect, the invention relates to a data processing device for decrypting an encrypted data packet, wherein the encrypted data packet is encrypted using a cryptographic key. The data processing device comprises a bus interface, which is designed to communicate via a communication bus with an encryption device, the bus interface being designed to grant a memory direct access by the encryption device, a memory which is writable by the memory direct access by the encryption device, wherein the memory is formed is to store the encrypted data packet, and a processor, which is configured to associate the encrypted data packet with the cryptographic key to obtain a decrypted data packet.

According to one embodiment, the processor is configured to execute a program code for linking the encrypted data packet with the cryptographic key. This provides the advantage that the encrypted data packet can be decrypted efficiently. The program code can be provided, for example, in the form of a software driver.

According to one embodiment, the cryptographic key is stored in the memory. This provides the advantage that the cryptographic key can be provided efficiently.

In one embodiment, the processor is configured to associate the encrypted data packet with the cryptographic key using a block cipher algorithm, in particular an Advanced Encryption Standard (AES) decryption algorithm. However, the linking can also be done using a suitable stream cipher algorithm. This provides the advantage that an efficient algorithm for decrypting the encrypted data packet can be used.

According to a third aspect, the invention relates to a system for transmitting an encrypted data packet via a communication bus. The system comprises an encryption device according to the first aspect of the invention, and a data processing device according to the second aspect of the invention, wherein the encryption device and the data processing device are interconnected via the communication bus.

According to one embodiment, the encryption device and the data processing device are configured to determine the cryptographic key by means of a Diffie-Hellman key exchange. This achieves the advantage that the cryptographic key for encryption or decryption can be exchanged efficiently between the encryption device and the data processing device.

According to one embodiment, an exchange of the cryptographic key between the encryption device and the data processing device takes place during an initialization of the encryption device and the data processing device during production. As a result, the advantage is achieved that the cryptographic key can already be firmly inserted in the encryption device and the data processing device during production.

According to one embodiment, the encryption device and the data processing device each comprise a communication interface for exchanging the cryptographic key. This provides the advantage that the communication interface can be dedicated to the exchange of the cryptographic key.

According to one embodiment, the exchange of the cryptographic key between the encryption device and the data processing device takes place using a replaceable memory module or a smart card. This provides the advantage that the exchange of the cryptographic key between the encryption device and the data processing device can be performed by means of dedicated hardware components.

According to a fourth aspect, the invention relates to a method for encrypting a data packet using an encryption device. The encryption device comprises a network interface, a circuit and a bus interface, wherein the bus interface is configured to communicate with a data processing device via a communication bus. The method comprises receiving the data packet via a communication network through the network interface, linking the received data packet with a cryptographic key through the circuit to obtain an encrypted data packet, and storing the encrypted data packet by means of a direct memory access in a memory of the data processing device Bus Interface.

The method may be performed by the encryption device. Further features of the method result directly from the features and / or functionality of the encryption device.

According to a fifth aspect, the invention relates to a method for decrypting an encrypted data packet using a data processing device, wherein the encrypted data packet is encrypted using a cryptographic key. The data processing device comprises a bus interface, a memory and a processor, wherein the bus interface is adapted to communicate via a communication bus with an encryption device, wherein the bus interface is adapted to grant a memory direct access by the encryption device, wherein the memory by means of the memory direct access by the encryption device is writable. The method comprises storing the encrypted data packet in the memory by means of the memory direct access, and associating the encrypted data packet with the cryptographic key by the processor to obtain a decrypted data packet.

The method may be performed by the data processing device. Further features of the method result directly from the features and / or the functionality of the data processing device.

According to a sixth aspect, the invention relates to a computer program with a program code for carrying out the method according to the fourth aspect of the invention or the method according to the fifth aspect of the invention.

The encryption device and / or the data processing device can be set up in terms of programming in order to execute the computer program.

The invention may be implemented in hardware and / or software.

• 1 ein schematisches Diagramm einer Verschlüsselungsvorrichtung zum Verschlüsseln eines Datenpakets;
• 2 ein schematisches Diagramm einer Datenverarbeitungsvorrichtung zum Entschlüsseln eines verschlüsselten Datenpakets;
• 3 ein schematisches Diagramm eines Systems zum Übertragen eines verschlüsselten Datenpakets über einen Kommunikationsbus;
• 4 ein schematisches Diagramm eines Systems zum Übertragen eines verschlüsselten Datenpakets über einen Kommunikationsbus;
• 5 ein schematisches Diagramm eines Systems zum Übertragen eines verschlüsselten Datenpakets über einen Kommunikationsbus;
• 6 ein schematisches Diagramm eines Systems zum Übertragen eines verschlüsselten Datenpakets über einen Kommunikationsbus;
• 7 ein schematisches Diagramm eines Verfahrens zum Verschlüsseln eines Datenpakets unter Verwendung einer Verschlüsselungsvorrichtung; und
• 8 ein schematisches Diagramm eines Verfahrens zum Entschlüsseln eines verschlüsselten Datenpakets unter Verwendung einer Datenverarbeitungsvorrichtu ng.

Further embodiments will be explained with reference to the accompanying figures. Show it:

• 1 a schematic diagram of an encryption device for encrypting a data packet;
• 2 a schematic diagram of a data processing device for decrypting an encrypted data packet;
• 3 a schematic diagram of a system for transmitting an encrypted data packet over a communication bus;
• 4 a schematic diagram of a system for transmitting an encrypted data packet over a communication bus;
• 5 a schematic diagram of a system for transmitting an encrypted data packet over a communication bus;
• 6 a schematic diagram of a system for transmitting an encrypted data packet over a communication bus;
• 7 a schematic diagram of a method for encrypting a data packet using an encryption device; and
• 8th a schematic diagram of a method for decrypting an encrypted data packet using a Datenverarbeitungsvorrichtu ng.

1 shows a schematic diagram of an encryption device 100 for encrypting a data packet. The encryption device 100 includes a network interface 101 which is adapted to receive the data packet via a communication network, a circuit 103 which is adapted to combine the received data packet with a cryptographic key to obtain an encrypted data packet, and a bus interface 105 , which is adapted to communicate with a data processing device via a communication bus, wherein the bus interface 105 is configured to store the encrypted data packet by means of a direct memory access in a memory of the data processing device.

2 shows a schematic diagram of a data processing device 200 for decrypting an encrypted data packet, wherein the encrypted data packet is encrypted using a cryptographic key. The data processing device 200 includes a bus interface 201 , which is adapted to communicate via a communication bus with an encryption device, wherein the bus interface 201 is designed to grant a memory direct access by the encryption device, a memory 203 , which is writable by the memory direct access by the encryption device, wherein the memory 203 is configured to store the encrypted data packet, and a processor 205 which is configured to associate the encrypted data packet with the cryptographic key to obtain a decrypted data packet.

3 shows a schematic diagram of a system 300 for transmitting an encrypted data packet over a communication bus 301 , The system 300 includes an encryption device 100 and a data processing device 200 , wherein the encryption device 100 and the data processing device 200 over the communication bus 301 connected to each other.

The encryption device 100 includes a network interface 101 configured to receive a data packet via a communication network, a circuit 103 which is adapted to combine the received data packet with a cryptographic key to obtain the encrypted data packet, and a bus interface 105 which is formed with the data processing apparatus 200 via the communication bus 301 to communicate, with the bus interface 105 is formed, the encrypted data packet by means of a memory direct access in a memory 203 the data processing device 200 save.

The data processing device 200 includes a bus interface 201 which is formed over the communication bus 301 with the encryption device 100 to communicate, with the bus interface 201 is formed, the memory direct access by the encryption device 100 to grant the store 203 , which by means of the memory direct access by the encryption device 100 is writable, the memory 203 is configured to store the encrypted data packet, and a processor 205 which is configured to associate the encrypted data packet with the cryptographic key to obtain a decrypted data packet.

The system 300 Furthermore, a bidirectional communication between the encryption device 100 and the data processing device 200 enable.

The processor 205 the data processing device 200 may be configured to provide another data packet and with the to combine cryptographic keys to obtain an encrypted further data packet. The processor 205 may further be configured, the encrypted further data packet in the memory 203 store. The bus interface 105 the encryption device 100 can be formed by means of a memory direct access the encrypted further data packet from the memory 203 the data processing device 200 read. The circuit 103 can be configured to associate the read encrypted further data packet with the cryptographic key to obtain a decrypted further data packet. The network interface 101 can be configured to send the decrypted further data packet via the communication network. Consequently, communication is in the opposite direction from the data processing device 200 to the encryption device 100 possible. The encryption device 100 or the circuit 103 can therefore be used both for encrypting and for decrypting.

4 shows a schematic diagram of a system 300 for transmitting an encrypted data packet over a communication bus 301 , The system 300 includes an encryption device 100 and a data processing device 200 , wherein the encryption device 100 and the data processing device 200 over the communication bus 301 connected to each other.

The encryption device 100 includes a network interface 101 , a circuit 103 , and a bus interface 105 , The data processing device 200 includes a bus interface 201 , a store 203 , and a processor 205 , The bus interface 105 and the bus interface 201 are each designed as PCI bridges or PCI bridges. The communication bus 301 is a PCI or a PCIe communication bus.

Through the system 300 allows to use untrusted IP cores and at the same time a trustworthy system 300 to realize. In the illustrated system 300, data packets are received from outside and preprocessed appropriately in a separate FPGA or ASIC component. Before the received data packets then direction memory, such as main memory, the data processing device 100 are copied by means of a memory direct access or a similar method, such as I / O port, they are encrypted by a implemented in FPGA / ASIC circuit 103 as a crypto-component. The encrypted data packets are then processed by the processor 205 For example, the main CPU, the data processing device 200 decrypted again.

The exchange of the cryptographic keys can take place at runtime, for example during initialization, or during the synthesis or implementation time of the FPGA or ASIC and an associated software driver.

5 shows a schematic diagram of a system 300 for transmitting an encrypted data packet over a communication bus 301 , The system 300 includes an encryption device 100 and a data processing device 200 , wherein the encryption device 100 and the data processing device 200 over the communication bus 301 connected to each other.

The encryption device 100 is through an encryption unit 501 and a network card 503 formed, wherein the encryption unit 501 a network interface 101 and a circuit 103 and wherein the network card 503 is a bus interface 105 includes. The encryption unit 501 can be an external component and the network card 503 can be a standard network card. The encryption unit 501 can be implemented in hardware and / or software. The circuit 103 Consequently, it will not work together with the bus interface 105 implemented in an FPGA or ASIC, but is considered an external component in front of the network card 503 looped. The data processing device 200 includes a bus interface 201 , a store 203 , and a processor 205 , The bus interface 105 and the bus interface 201 are each designed as PCI bridges or PCI bridges. The communication bus 301 is a PCI or a PCIe communication bus.

The data packet is through the network interface 101 via a communication network, such as an Ethernet communication network. The communication between the encryption unit 501 and the network card 503 takes place via a further communication network, for example a further Ethernet communication network. The communication via the communication network and / or the further communication network can be carried out using a standard communication protocol.

The concept thus allows an interaction of untrusted components with a data processing device 100 For example, a computer system and the operating system running on it. Furthermore, the concept makes it possible to secure already finished hardware components by means of an external component. Since encrypted data packets are transmitted through the untrusted components, they may not be included in any security analyzes.

6 shows a schematic diagram of a system 300 for transmitting an encrypted data packet over a communication bus 301 , The system 300 includes an encryption device 100 and a data processing device 200 , wherein the encryption device 100 and the data processing device 200 over the communication bus 301 connected to each other. The encryption device 100 forms a Network Interface Card (NIC) in an FPGA.

The encryption device 100 includes a network interface 101 , a circuit 103 , and a bus interface 105 , The network interface 101 includes an input / output interface (I / O) and logic for pre-processing the received data packets. The circuit 103 can be designed as an encoder / decoder (E / D). The circuit 103 can for bidirectional communication between the encryption device 100 and the data processing device 200 both for encrypting and for decrypting data packets are used. The bus interface 105 may include a direct memory access DMA controller. The data processing device 200 includes a bus interface, not shown 201 , a store 203 , and a processor 205 , The memory 203 may be a main memory, for example in the form of a Double Data Rate (DDR) memory, the data processing device 200 be. The processor 205 can implement / execute an Encoder / Decoder (E / D) as well as an operating system (OS). The implementation can be done by means of a software driver. The bus interface 105 and the bus interface 201 are each designed as PCI bridges or PCI bridges. The communication bus 301 is a PCI or a PCIe communication bus.

In the implementation, for example by means of the FPGA, components of third-party manufacturers, which represent a potential risk, can be used for certain tasks. The concept can increase the security of communication.

The encryption device 100 is implemented, for example, on an FPGA with third-party components. The encryption device 100 has a circuit 103 or Encoder / Decoder (E / D), which is arranged in the data path, preferably close to the network interface 101 the encryption device 100 , The processor 205 runs an operating system and implements a corresponding Encoder / Decoder (E / D).

For communication with the operating system, the received data packets are encrypted by the encryption device 100 encrypted and in the operating system by the processor 205 decrypted. Unencrypted communications, which may come from third-party components, are rendered unusable in the operating system by the subsequent decryption.

For communication via the encryption device 100 appropriate data packets in the operating system by the processor 205 encrypted and through the circuit 103 the encryption device 100 again decrypted and unencrypted by the network interface 101 sent out via the communication network. However, decryption does not re-encrypt communications that are not from the operating system and thus render them useless. Thus, also by the operating system in the memory 203 stored data packets are saved.

The concept can generally be implemented in all types of network cards, regardless of the type of implementation, such as in an FPGA.

7 shows a schematic diagram of a method 700 for encrypting a data packet using an encryption device. The encryption device comprises a network interface, a circuit and a bus interface, wherein the bus interface is configured to communicate with a data processing device via a communication bus.

The procedure 700 includes receiving 701 of the data packet over a communication network through the network interface, linking 703 the received data packet with a cryptographic key through the circuit to obtain an encrypted data packet, and a store 705 the encrypted data packet by means of a memory direct access in a memory of the data processing device through the bus interface.

8th shows a schematic diagram of a method 800 for decrypting an encrypted data packet using a data processing device, wherein the encrypted data packet is encrypted using a cryptographic key. The data processing device comprises a bus interface, a memory and a processor, wherein the bus interface is adapted to communicate via a communication bus with an encryption device, wherein the bus interface is adapted to grant a memory direct access by the encryption device, wherein the memory by means of the memory direct access by the encryption device is writable.

The procedure 800 includes a save 801 the encrypted data packet in the memory by means of the memory direct access, and a link 803 the encrypted data packet containing the cryptographic key by the processor to obtain a decrypted data packet.

All the features shown or described in connection with individual embodiments of the invention may be provided in different combinations in the article according to the invention in order to simultaneously realize their advantageous effects.

LIST OF REFERENCE NUMBERS

100

encryptor

101

Network Interface

103

circuit

105

bus interface

200

Data processing device

201

bus interface

203

Storage

205

processor

300

system

301

communication

501

encryption unit

503

network card

700

Method for encrypting a data packet

701

Receive

703

Link

705

to save

800

Method for decrypting an encrypted data packet

801

to save

803

Link

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited non-patent literature

• A. Waksman, S. Sethumadhavan, "Silencing Hardware Backdoors", IEEE Symposium on Security and Privacy, 2011, p. 49-63. [0005]

Claims (15)

Encryption device (100) for encrypting a data packet, comprising: a network interface (101) configured to receive the data packet via a communication network; a circuit (103) configured to associate the received data packet with a cryptographic key to obtain an encrypted data packet; and a bus interface (105) which is designed to communicate with a data processing device (200) via a communication bus (301), the bus interface (105) being adapted to store the encrypted data packet in a memory (203) of the data processing device (200 ) save. Encryption device (100) according to Claim 1 wherein the circuit (103) comprises a memory in which the cryptographic key is stored. An encryption apparatus (100) according to any one of the preceding claims, wherein the circuit (103) is adapted to associate the received data packet with the cryptographic key using a block cipher algorithm, in particular an Advanced Encryption Standard (AES) encryption algorithm. The encryption apparatus (100) of any one of the preceding claims, wherein the communication bus (301) is a Peripheral Component Interconnect (PCI) communication bus, or wherein the communication bus (301) is a Peripheral Component Interconnect Express (PCle) communication bus. The encryption device (100) according to one of the preceding claims, wherein the encryption device (100), in particular the network interface (101), the circuit (103) and / or the bus interface (105), by means of a Field Programmable Gate Array (FPGA). or implemented by means of an application-specific integrated circuit (ASIC). The encryption apparatus (100) of any one of the preceding claims, wherein the encryption apparatus (100) comprises an encryption unit (501) and a network card (503), wherein the encryption unit (501) comprises the network interface (101) and the circuit (103), and wherein the network card (503) comprises the bus interface (105). Encryption device (100) according to Claim 6 wherein the encryption unit (501) and the network card (503) are configured to communicate with each other via another communication network. Data processing apparatus (200) for decrypting an encrypted data packet, wherein the encrypted data packet is encrypted using a cryptographic key, comprising: a bus interface (201) configured to communicate with an encryption device (100) via a communication bus (301), the bus interface (201) being adapted to provide a memory direct access by the encryption device (100); a memory (203) writable by the memory direct access by the encryption device (100), the memory (203) being adapted to store the encrypted data packet; and a processor (205) configured to associate the encrypted data packet with the cryptographic key to obtain a decrypted data packet. Data processing device (200) according to Claim 8 wherein the processor (205) is adapted to execute a program code for linking the encrypted data packet with the cryptographic key. Data processing device (200) according to one of Claims 8 or 9 , wherein the cryptographic key is stored in the memory (203). A system (300) for transmitting an encrypted data packet over a communication bus (301), comprising: an encryption device (100) according to any one of Claims 1 to 7 ; and a data processing device (200) according to one of Claims 8 to 10 ; wherein the encryption device (100) and the data processing device (200) are interconnected via the communication bus (301). System (300) after Claim 11 wherein the encryption device (100) and the data processing device (200) are adapted to determine the cryptographic key by means of a Diffie-Hellman key exchange. Method (700) for encrypting a data packet using an encryption device (100), wherein the encryption device (100) comprises a network interface (101), a circuit (103) and a bus interface (105), wherein the bus interface (105) is formed, to communicate with a data processing device (200) via a communication bus (301), comprising: Receiving (701) the data packet over a communication network through the network interface (101); Linking (703) the received data packet with a cryptographic key through the circuit (103) to obtain an encrypted data packet; and storing (705) the encrypted data packet by means of a memory direct access in a memory (203) of the data processing device (200) through the bus interface (105). A method (800) for decrypting an encrypted data packet using a data processing device (200), wherein the encrypted data packet is encrypted using a cryptographic key, wherein the data processing device (200) comprises a bus interface (201), a memory (203) and a processor ( 205), wherein the bus interface (201) is adapted to communicate with an encryption device (100) via a communication bus (301), the bus interface (201) being adapted to provide a memory direct access by the encryption device (100), wherein the Memory (203) is writable by the memory direct access by the encryption device (100), with: Storing (801) the encrypted data packet in the memory (203) by means of the memory direct access; and Linking (803) the encrypted data packet with the cryptographic key by the processor (205) to obtain a decrypted data packet. A computer program having a program code for performing the method (700) Claim 13 or the method (800) Claim 14 ,

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