DE102015003134A1 - Global shutter pixel and correction method - Google Patents

Abstract

An image sensor with global shutter includes a pixel array (201) and a timing circuit (210) on a semiconductor substrate (SUB). Each pixel (200) contains a photosensitive element (PPD) and a sensor node (FDN). A first transfer gate (TG) is disposed between the photosensitive member (PPD) and the sensor node (FDN). A buffer amplifier (N1) is connected to the sensor node. The output (IMN) of the buffer amplifier can be connected to a column line (COL) via an output switch (N2). A sampling stage (SST) is connected to the output (IMN) of the buffer amplifier (N1). The output (STN) of the sampling stage (SST) can be connected to the sensor node (FDN) via a feedback switch (N3). Advantageous further embodiments of pixels are disclosed. Furthermore, methods are described for operating the pixel array and thereby outputting a corrected signal.

Description

FIELD OF USE

The present disclosure relates to a pixel and an array of pixels for semiconductor image sensors. In particular, it relates to a global shutter pixel having two internal storage nodes for a true correlated double sampling function.

STATE OF THE ART

Electronic camera functions originally used for video or photo camera products are now ubiquitous and can be found in virtually every portable electronic device such as a mobile phone, an organizer and others.

In the past, solid-state image sensors were special devices produced by a CCD manufacturing process. Today, image sensors are typically manufactured using a standard CMOS process, with some image sensor-specific options added. Therefore, such sensors can participate in the continuous progress of CMOS processes, reducing critical dimensions and power dissipation. In contrast, the speed of the circuit elements and the complexity of a circuit continue to increase. In this way, very high resolution sensors have become possible at a low cost and almost every sensor can detect fast video signals.

The vast majority of CMOS image sensors use the so-called rolling-out reading technique. The lines of a pixel field are read sequentially. At the maximum frame rate, signal read operations, their analog-to-digital conversion, and data transport through the digital interfaces are uninterrupted. With a simple pixel circuit, the period of light integration ends with the reading of the associated line. The period of the light integration will be referred to as integration period or integration time hereinafter.

In this way, the rolling shutter method results with simple pixels. The integration times of the lines are shifted in time relative to each other. For example, the integration time of the last line of an image is only slightly different from the integration time of the first line of the following image.

The rolling-shutter method leads to artifacts with any kind of movement, be it moving objects in the scene, a movement of the camera, z. As a camera swing, or lighting with temporally modulated light, z. B. with a fluorescent lamp, which is operated with alternating current.

An image sensor according to the "global shutter method" avoids these disadvantages. It is even possible to use a bright flash light source to suppress disturbing background light. With the global shutter method is meant a method which is also referred to as a "pipelined" global shutter method. By this it is meant that the reading of a previous image occurs during the integration time of the currently current image.

This feature is required for fast video capture.

In many applications, such as in the industry, in television studios, for scientific instruments, etc., there has long been interest in sensors with global shutter. However, the global shutter method basically requires a more complex pixel, which in turn enforces trade-offs between different technical and economic characteristics.

First, a pixel to be used for the global shutter method must be able to store a signal value for a certain time. The time begins with the command to all pixels to end the integration time, and the time ends with the reading of the signal value, which is line sequential. This storage occurs on a node of an electronic circuit that stores either a voltage or a charge. In the following, the term storage node is used.

An effect known by pixels in image sensors is the so-called kTC noise. This kTC noise can be found everywhere, where a capacity is charged via a switch. The effect will be relatively stronger with smaller capacities. Now, photosensitive elements and sensor nodes of pixels are usually reset by switches for initialization. Such a node has a small capacity, typically about a femto-farad. The effect of kTC noise would make the realization of small pixels impossible, if one did not use the CDS method for compensation. CDS means Correlated Double Sampling. The CDS method stores the reset value of a pixel directly after the reset. After the integration time, the signal value is taken with the exposure and the reset value subtracted therefrom, so that the mentioned noise component falls out. The reset value is often called the reference value.

The reset value can be stored in an image memory, which is usually digital and located outside the image sensor chip. In this way, the global shutter method can be realized with a storage node in the pixel (apart from the photosensitive element itself). One can also refer to a chip as a semiconductor substrate or substrate.

• – Ein Pixel soll klein sein, um eine hohe Auflösung, geringere Abmessungen des Chips und geringe Systemkosten zu ermöglichen.
• – Ein kleines Pixel ist möglich, wenn die Anzahl der darin vorhandenen Bauelemente klein ist.
• – Spezielle nicht-standard Bauelemente sollten vermieden werden. Ein CMOS Prozess mit üblichen Bildsensoroptionen ist oft wünschenswert.
• – Speicherknoten sollten unempfindlich gegenüber Lichteinwirkung sein. Sonst kann die gespeicherte Information zerstört werden.
• – Externes Correlated-Double-Sampling sollte vermieden werden, weil dies eine höhere Arbeitsgeschwindigkeit und einen Bildspeicher erfordert.
• – Für den Speicherknoten ist eine große Kapazität wünschenswert, damit dieser nur geringe Beiträge zum kTC-Rauschen leistet.
• – Eine Belichtungszeiteinstellung sollte möglich sein, das heißt, der Sensor kann mit einer einstellbaren Dauer der Integrationszeit betrieben werden, die kleiner ist als die Bilddauer.
• – Der Einfluss von Leckströmen der Sperrschichten sollte gering sein.

Alternatively, the reset value can also be stored in the pixel itself. This then means that in addition to the photosensitive element then two storage nodes must be present. When a line of pixels is read out, each reset value and its exposed value are read directly out of each pixel. The subtraction of the two values can be done with analog circuit means. There are a number of aspects to consider when specifying a global-shutter pixel:

• One pixel should be small to allow high resolution, smaller chip size, and low system cost.
• A small pixel is possible if the number of components present therein is small.
• - Special non-standard components should be avoided. A CMOS process with common image sensor options is often desirable.
• - Storage nodes should be insensitive to light. Otherwise the stored information can be destroyed.
• - External Correlated Double Sampling should be avoided because this requires a higher operating speed and image memory.
• - For the storage node, a large capacity is desirable so that it makes only small contributions to the kTC noise.
• - An exposure time setting should be possible, that is, the sensor can be operated with an adjustable duration of the integration time, which is smaller than the image duration.
• - The influence of leakage currents of the barrier layers should be low.

In " Yang, G .; A Snap-Shot CMOS Active Pixel Imager for Low Noise, High-Speed Imaging; IEEE; IEDM; 1998 "Is a CMOS image sensor with" snap-shot shutter "described. A pixel consists of a photo-gate, two transfer gates, a reset gate, a metal-shielded sensor node, a source follower, and a row select transistor.

US7045753B1 discloses a CMOS pixel with five transistors that avoids artifacts of the rolling shutter method and wants to allow adjustment of the exposure time.

These pixels use the sensor node for signal storage. Accordingly, such pixels can be used in conjunction with an external image memory to realize the global shutter method and CDS.

US7045754B2 discloses the use of a CCD-like signal storage node as part of a CMOS image sensor.

EP2587794A2 describes embodiments of global shutter pixels having two storage nodes in the pixel itself. Therefore, no external image memory is required. One of the embodiments is in 1 played. The pixel is based on a photosensitive element with a transfer gate TG. The two memory devices are realized as capacitors. The transistor M4 and the capacitor C1 form a first sampling stage which is intended to store the reference signal. The transistor M3 and the capacitor C2 form a second sampling stage for storing the bright signal.

OBJECT OF THE INVENTION

There is a need for low complexity pixels that simultaneously implement the global shutter method and support the pixel's Correlated Double Sampling.

SOLUTION OF THE TASK

In this publication, a pixel array is described which consists of a plurality of pixels arranged in rows and columns. The pixel array and a timing circuit are arranged on a semiconductor substrate. The timing circuit drives the plurality of pixels so that these pixels have identical integration times. Each of the plurality of pixels includes a photosensitive element and a sensor node. Between the photosensitive element and the sensor node, a first transfer gate is arranged. An input of a buffer amplifier is connected to the sensor node. A sampling stage consisting of a sampling switch and a storage capacitor is connected to an output of the buffer amplifier. An output switch is disposed between the output of the buffer amplifier and a column line. Furthermore, a feedback switch is arranged between an output of the sampling stage and the sensor node.

Optionally, a discharge switch is provided which is connected to the output of the sampling stage.

There is also a reset switch with a first and a second connection. The first connection of the reset switch is connected to a second supply voltage.

According to the first exemplary embodiment of a pixel, the second terminal of the reset switch is connected to the sensor node.

According to the second embodiment of a pixel, the second terminal of the reset switch is connected to the output of the sampling stage.

Other aspects of the invention are advantageous embodiments using MOS field effect transistors.

Variants of the first and second embodiments of a pixel are described as third and fourth embodiments, respectively.

Another aspect of the invention relates to operating methods for operating a pixel and a pixel array according to the invention.

Another aspect of the invention are advantageous operating methods that correct signals from a pixel and a pixel array.

ADVANTAGES OF THE INVENTION

A pixel array according to the invention enables operation according to the global shutter method and at the same time supports correlated double sampling on the chip, that is to say without the need of an image memory.

The realization of the Correlated Double Sampling method implies the suppression of the entire fixed pattern noise from the pixel, which is due in particular to the mismatching of threshold voltages of the source follower stages. Advantageously, only one storage capacitor is present in a pixel. In addition, only five or six MOS transistors of the same type are present except for the transfer gates. The small number of devices is a major advantage of a pixel of the invention when compared to prior art pixels. The small number of components enables the realization of small pixels with good quantum efficiency.

Advantageously, a pixel according to the invention uses only one buffer amplifier between the sensor node and the column line. Therefore, the voltage of the sensor node is lowered only by a transistor threshold voltage. This helps to keep the dynamic range of the pixel as much as possible. When the column line is driven at a very low voltage, clipping occurs, that is, truncation of the signal, and associated distortion of the signal. In solutions with two buffer amplifiers, clipping is more likely to occur because two threshold voltages are involved.

Advantageously, a pixel according to the invention has only a low temporal noise, because only one buffer amplifier contributes transistor noise.

Advantageously, a pixel is based on a common four-transistor or five-transistor configuration. Non-standard process steps of the production technology or special components are avoided. The pixel array according to the invention can therefore be produced directly by means of an industry-standard manufacturing process.

Embodiments of pixels according to the invention support an exposure time adjustment by an electronic shutter.

The second embodiment of a method for correcting offset components has the additional advantage of suppressing fixed pattern noise with column structure.

Noise components of the buffer amplifier with a 1 / f characteristic are largely suppressed by the successive reading of light and reference values.

All embodiments of pixels according to the invention include means to avoid overflow of pixels and blooming effects, which is done by means of an anti-blooming function.

Advantageously, the embodiments of pixels use pinned photodiodes, which at present represent the preferred choice for photosensitive elements.

Advantageously, it is possible to generate noise-reduced sets of calibration values.

BRIEF DESCRIPTION OF THE DRAWINGS

The following drawings relate to the prior art and the preferred embodiments of the invention.

1 shows a global shutter pixel according to the prior art;

2 Fig. 12 is a block diagram of one embodiment of an image sensor system having a pixel array and pixels according to the invention;

3 shows a first embodiment of a pixel according to the invention;

4 Fig. 10 is a timing chart for an embodiment of a first operation method for a pixel according to the first embodiment;

5 shows a second embodiment of a pixel according to the invention;

6 Fig. 10 is a timing chart showing pulses for an embodiment of a second operation method for a pixel according to the second embodiment;

7 shows a third embodiment of a pixel according to the invention;

8th shows a fourth embodiment of a pixel according to the invention;

9 shows a flowchart for an embodiment of a third method of operation of a pixel; and

10 shows a flowchart for an embodiment of a fourth method of operation of a pixel.

DESCRIPTION OF EMBODIMENTS

The block diagram 2 shows an embodiment of an image sensor system disposed on a substrate SUB and a pixel array 201 with pixels 200 includes according to the invention. The pixels 200 are arranged in rows and columns. On the same semiconductor substrate SUB are also a timing circuit 210 and a column block 221 arranged. The column block 221 consists of a large number of column circuits 220 , During the read operation, each of the pixels becomes 200 located in a selected row over a column line COL with an associated column circuit 220 connected. So are the pixels 200 generated signals to the column block 221 sent and in formatted signals 230 transformed.

The timing circuit 210 has the task pulses to the pixel field 201 to send and the pixel field 201 operate in a global shutter method. That is, all pixels 200 should have identical integration times.

The formatted signals 230 leave the column block 221 and the semiconductor substrate SUB and to the processing block 231 Posted. Connected to the processing block 231 is a calibration value memory 232 , The processing block provides digital signals 233 starting from the formatted signals 230 and of signals stored in the calibration value memory 232 are stored.

In 3 is a first embodiment of a pixel 200 imaged according to the invention. A photosensitive member PPD, a first transfer gate TG, and a sensor node FDN are disposed on the semiconductor substrate SUB. The first transfer gate TG has its input connected to a seventh control signal Tx.

Preferably, a so-called "pinned" photodiode is used as the photosensitive member PPD, but other types of photosensitive members may be used without departing from the spirit of the invention.

Exposure generates electron-hole pairs in the semiconductor substrate. Charges of one type are collected in the photosensitive member PPD. When the first transfer gate TG is made conductive, charges collected in the photosensitive member PPD flow to the sensor node FDN. Here they generate a bright state of the sensor node FDN. The bright state can be considered as a voltage that results according to the amount of overflowed charges.

As part of the pixel 200 are also the other components in 3 arranged on the same semiconductor substrate SUB.

In the figure, the components N1, N2, N3, N4, N5 and N6 are drawn as N-channel type MOS field-effect transistors. In many cases, a MOS field effect transistor works as a switch. In other cases, a MOS field effect transistor operates as a buffer amplifier. For ease of description, a MOS field effect transistor may be referred to hereinafter as a "switch" or "buffer amplifier".

In the function as a switch corresponds to one of the terminals source and drain of the MOS field effect transistor to the first terminal of the switch. Another of the source and drain terminals corresponds to the second terminal of the switch. The gate of the MOS field-effect transistor corresponds to the input of the switch.

In function as a buffer amplifier, one of the source and drain terminals of the MOS field effect transistor represents the output of the buffer amplifier and another of the source and drain terminals constitutes a supply terminal. The gate of the MOS field effect transistor forms the input of the buffer amplifier.

The input of the buffer amplifier N1 is connected to the sensor node FDN. The supply terminal of the buffer amplifier N1 is connected to a first supply voltage Vds. The output of the buffer amplifier is connected to an intermediate node INN. The buffer amplifier N1 is a source follower, which means that its output signal at the node IMN represents the voltage at the sensor node FDN, but that in addition a systematic signal deviation is added.

The input of an output switch N2 is connected to a second control signal Sel. The output switch N2 is located between the intermediate node IMN and the column line COL. The last sentence is intended to mean that the first terminal of the output switch N2 is connected to the intermediate node IMN and that the second terminal of the output switch N2 is connected to the column line COL.

When the output switch N2 conducts, the output voltage generated by the buffer amplifier N1 becomes the pixel 200 sent to the column line COL.

A sampling switch N4 and a storage capacitor CS form a sampling stage SST whose output is connected to the storage node STN. The input of the sampling switch N4 is connected to a fourth control signal Mem. The sampling switch N4 is arranged between the intermediate node IMN and the storage node STN. The storage capacitor CS is arranged between the storage node STN and a reference potential. When the sampling switch N4 becomes conductive, the output of the buffer amplifier N1 connected to the intermediate node IMN charges the storage node STN. The charge of the storage capacitor CS, which is connected to the storage node STN, then changes accordingly. If the sampling switch N4 is made to isolate, then the voltage at the storage node STN can not change and the voltage from the past is maintained.

The input of a discharge switch N5 is connected to a fifth control signal Rlo. The discharge switch N5 is arranged between the storage node STN and the reference potential. The discharge switch N5 has the function of discharging the storage node STN so that it is prepared for the next voltage to be stored. The buffer amplifier N1 can only supply one electric current, thus it is not able to pull down the voltage at the storage node STN.

The input of a feedback switch N3 is connected to a third control signal Pas. The feedback switch N3 is arranged between the storage node STN and the sensor node FDN. The feedback switch N3 serves to return the signal stored by the sampling stage SST to the sensor node FDN, so that it can also be read out via the column line COL.

The input of a reset switch N6 is connected to a sixth control signal Rhi. The first terminal of the reset switch N6 is connected to a second supply voltage VDH. The second terminal of the reset switch N6 is connected to the sensor node FDN. When the reset switch N6 is made conductive, the sensor node FDN is initialized to a reset state. Any existing photo charges on the sensor node FDN are removed.

Other types of transistors may be used without departing from the spirit of the invention. For example, one skilled in the art will understand that a circuit will continue to operate by replacing MOSFETs of the N-channel type with P-channel type field effect transistors, and vice versa, as well as reversing the polarity of voltages and currents.

In the first embodiment of the pixel 200 In order to control the exposure time, the photosensitive member PPD may be additionally provided with a second transfer gate TA as shown in FIG 5 illustrated, and without departing from the spirit of the invention.

An embodiment of a first method of operation for a pixel field 201 from pixels 200 according to the first embodiment is in 4 shown. A first sequence 401 Pulse is used to get out of the pixel field 201 Read out signals representing real image information. A second sequence 402 Pulse is used to get out of the pixel field 201 Read out signals representing calibration information.

The following is the first sequence 401 described according to the chronological order of the operations. For each of the pixels 200 For example, photo charges in the photosensitive member PPD are continuously generated by incident light. The first important event of the first sequence is a pulse of the seventh control signal Tx for all pixels 200 of the pixel field 201 , This is the actual global shutter process. In each pixel, the photo-charges are transported via the conductive first transfer gate TG to the corresponding sensor node FDN. In this way, each of the sensor nodes FDN is brought into a bright state.

Each "pulse" of a signal causes it to go high for a while and then go low. A high level should cause a switch to conduct, whereas a low level should make it non-conductive. Here these conventions are used. Other embodiments could use other types of devices, however, so that deviations from this the above convention, but without departing from the spirit of the invention.

The next pulses are line sequential to the pixel field 201 created. Therefore, there is a variable pause time as indicated in the drawing.

Below is now a random line and a pixel 200 considered in the randomly chosen line. The following operations are performed on the named pixel when the randomly selected line is addressed.

At the intermediate node IMN, a bright signal S41 is present in accordance with the bright state of the sensor node FDN. With a pulse of the second control signal Sel, the output switch N2 becomes conductive and the bright signal S41 is sent to the column line COL. As a result, the bright signal S41 becomes out of the pixel field 201 output.

Due to previous operations, a first reference voltage should be applied to the storage node STN. A pulse of the third control signal Pas closes the feedback switch N3. This leads to a charge redistribution between the storage capacitor CS and the sensor node FDN. A modified first reference state forms at the sensor node FDN. The buffer amplifier N1 accordingly supplies a modified first reference signal S42 at the intermediate node IMN. A pulse of the second control signal Sel activates the output switch N2. The modified first reference signal S42 is sent to the column line COL.

As indicated in the diagram, the pulse of the third control signal Pas may also overlap with the pulse of the second control signal Sel. Alternatively, the two pulses of the second control signal Sel may merge, resulting in a single, long pulse.

To perform a reset operation, a pulse of the sixth control signal Rhi closes the reset switch N6. As a result, the sensor node FDN is initialized into a second reset state.

Next, a pulse of the fifth control signal Rio closes the discharge switch N5, so that the storage node STN is discharged.

It should be noted that the pulses of the sixth control signal Rhi and the fifth control signal Rio can be reversed in their temporal succession. Also, the relative duration of all pulses can be changed without departing from the spirit of the invention.

The second reset state formed on the sensor node FDN propagates through the buffer amplifier N1, and a second reference signal is formed on the intermediate node INN in accordance with the second reset state of the sensor node FDN. A pulse of the fourth control signal Mem makes the sampling switch N4 conductive. The storage node STN is charged by the buffer amplifier to a second reference voltage, corresponding to the second reset state.

At this time, the first sequence is completed and the pixel is initialized. The described first sequence can be repeated. For the random line, the next repeat will be one frame later.

In a simple embodiment, the modified first reference signal S42 is subtracted from the bright signal S41 to form a raw signal which is compensated for kTC noise.

In principle, however, the modified first reference signal S42 does not represent the first reset state of the sensor node FDN in the same way as the bright signal S41 represents the bright state of the sensor node FDN. The first pass through the buffer amplifier N1 would correctly form the first reference signal, which represents the first reset state of the sensor node FDN. In addition, however, the first reference signal passes through the feedback path. A corresponding voltage is stored on the storage node STN and influenced by the charge redistribution between the storage node STN and the sensor node FDN. Furthermore, the buffer amplifier N1 is passed through a second time, so that finally the modified first reference signal S42 is present, which is sent to the column line COL.

Preferably, the capacitance of the storage capacitor CS should be large compared to the capacitance of the sensor node FDN. In this case, the modified first reference signal S42 will differ from the first reference signal mainly by an offset component. The offset component is typically due to a threshold voltage of the buffer amplifier N1. Second, the above-mentioned feedback path has a loop gain that is typically slightly less than one.

In 4 is also a second sequence 402 displayed. The second sequence 402 is different from the first sequence 401 described in detail above by omitting the pulse of the seventh control signal Tx. The omission of the pulse and thus that the charge transport via the transfer gate is not carried out, causes the sensor node FDN remains in a second reset state.

When the pixel is read out, a second reference signal S43 is sent to the column line COL in accordance with the second reset state of the sensor node FDN. Subsequently, a modified second reference signal S44 corresponding to the second reference signal S43 and the second reset state of the sensor node FDN is sent to the column line COL.

Based on these two values, the offset components can be determined. The modified second reference signal S44 is subtracted from the second reference signal S43 to produce the offset components. The offset components are different for each pixel and slightly variable z. B with the temperature.

5 shows a second embodiment of a pixel 200 according to the present invention. The in connection with the first embodiment according to 3 of a pixel 200 statements made are true - with two exceptions.

The input of the reset switch N6 is still connected to the sixth control signal Rhi. The first terminal of the reset switch N6 is still connected to the second supply voltage VDH. However, here the second terminal of the reset switch N6 is connected to the storage node STN.

Furthermore, another type of photosensitive device is provided here. In addition, the photosensitive member PPD has a second transfer gate TA. The second transfer gate TA is used to control the exposure time, particularly in the sense that the exposure time can be made smaller than the image duration.

A particular advantage of the second embodiment of a pixel is that only one switch is connected to the sensor node FDN. This reduces the parasitic capacitances and leakage currents at the sensor node FDN.

An embodiment of a second method of operation for a pixel field 201 consisting of pixels 200 according to the second embodiment 6 specified.

Compared with the first operating method in 4 Here is the reset operation designed differently. For the reset operation, a short pulse of the third control signal Pas and a long pulse of the sixth control signal Rhi are applied. The long pulse begins before the short pulse begins. And the long pulse ends after the end of the short pulse. This overlap is necessary because the reset switch N6 and the feedback switch N3 are connected in series here. As a result, the reset switch N6 and the feedback switch N3 are simultaneously closed so that the sensor node FDN is initialized.

This modified reset operation can be found twice, in the first sequence 601 and in the second sequence 602 ,

Further embodiments of operating methods for a pixel field 201 and a pixel 200 according to the invention will be described below. The aim is to compensate for the above-mentioned offset components, which are visible in the deviation between the reference signal and the modified reference signal. The methods must be for each of the plurality of pixels 200 applied equally. However, in the following description, only "one pixel" or "the pixel" will be referred to.

• – ein Hellsignal S41,
• – ein modifiziertes erstes Referenzsignal S42,
• – ein zweites Referenzsignal S42, und
• – ein modifiziertes zweites Referenzsignal S44.

A pixel field 201 and pixels 200 according to the first embodiment of the invention - as shown in FIG 3 - And the embodiment of the first operating method are considered for the explanation, but this is not limiting. Likewise, a first sequence 401 of pulses and / or a second sequence 402 used by pulses - as shown in 4 , A combined sequence consists of the first sequence 401 and the second sequence 402 - in this order. From a pixel 200 Four signals are delivered during a combined sequence. As shown in 4 and above these are the signals:

• - a bright signal S41,
• A modified first reference signal S42,
• A second reference signal S42, and
• A modified second reference signal S44.

From the operation of the pixel, it is clear that the pair of the bright signal S41 and the modified first reference signal S42 is correlated with respect to the kTC noise. Likewise, the pair of the second reference signal S43 and the modified second reference signal S44 is correlated with respect to the kTC noise.

• 901: Das Pixel 200 stellt während jedes Bildes ein Hellsignal S41 bereit.
• 902: Das Pixel 200 stellt während jedes Bildes ein modifiziertes erstes Referenzsignal S42 bereit.
• 911: Das Pixel 200 stellt während jedes Bildes ein zweites Referenzsignal S42 bereit.
• 912: Das Pixel 200 stellt während jedes Bildes ein modifiziertes zweites Referenzsignal S43 bereit.
• 913: Für das Pixel 200 wird ein korrigiertes Signal SCC erzeugt.

An embodiment of a third method of operation is in 9 described. It always runs the combined sequence.

• 901 : The pixel 200 provides a bright signal S41 during each picture.
• 902 : The pixel 200 provides a modified first reference signal S42 during each frame.
• 911 : The pixel 200 provides a second reference signal S42 during each frame.
• 912 : The pixel 200 provides a modified second reference signal S43 during each frame.
• 913 : For the pixel 200 a corrected signal SCC is generated.

The four signals provided by the pixel during this combined sequence are applied to one of the plurality of column circuits via a column line COL 220 Posted.

Each of the column circuits 220 is configured to combine these four signals and form a corrected signal SCC. An advantageous correction formula implemented in each column circuit is as follows: SCC = (S41 - G1 * S42) - (S43 - G2 * S44)

Here, G1 is a first gain factor and G2 is a second gain factor. The first gain G1 and the second gain G2 are programmable and are typically selected equal and in accordance with the loop gain.

Preferably, the first gain G1 is the same for all column circuits 220 in the column block 221 , Also, the second gain G2 is preferably the same for all column circuits 220 in the column block 221 ,

The corrected signal SCC is compensated for the kTC noise and corrected for offset components and loop gain.

• 921: Ein Pixel 200 stellt ein zweites Referenzsignal S43 bereit.
• 922: Das Pixel 200 stellt zugehörig ein zweites modifiziertes Referenzsignal S44 bereit.
• 923: Das zweite Referenzsignal S43 und das zweite modifizierte Referenzsignal S44 werden verwendet um einen Satz von Kalibrierwerten zu erzeugen.
• 924: Jeder Satz von Kalibrierwerten wird in einem Kalibrationswertspeicher 232 gespeichert.

An embodiment of a fourth method of operation is in 10 described. Here is the second sequence 402 run only at certain times, but not during each frame duration.

• 921 : One pixel 200 provides a second reference signal S43.
• 922 : The pixel 200 in addition, provides a second modified reference signal S44.
• 923 The second reference signal S43 and the second modified reference signal S44 are used to generate a set of calibration values.
• 924 Each set of calibration values is stored in a calibration value memory 232 saved.

• 901: Das Pixel 200 stellt während jeder Bilddauer ein Hellsignal S41 bereit.
• 902: Das Pixel 200 stellt während jeder Bilddauer ein modifiziertes erstes Referenzsignal S42 bereit.
• 932: Ein zugehöriger der genannten Sätze von Kalibrierwerten wird aus dem Kalibrationswertspeicher 232 während jeder Bilddauer ausgelesen.
• 932: Während jeder Bilddauer wird ein korrigiertes Signal SCC erzeugt, welches auf dem Satz von Kalibrierwerten, dem Hellsignal S41 und dem modifizierten erste Referenzsignal S42 basiert.

During regular operation will be only the first sequence 401 executed.

• 901 : The pixel 200 provides a bright signal S41 during each frame duration.
• 902 : The pixel 200 provides a modified first reference signal S42 during each frame duration.
• 932 : An associated one of said sets of calibration values is taken from the calibration value memory 232 read out during each frame duration.
• 932 During each frame period, a corrected signal SCC is generated which is based on the set of calibration values, the bright signal S41 and the modified first reference signal S42.

The correction calculation is made by the processing block 231 in 2 carried out. Preferably, the correction calculation is made according to the formula given above in connection with the embodiment for the third method of operation.

Without departing from the spirit of the invention, the generation of the set of calibration values may involve additional signals. Thus, it may be advisable to use a longer time series of second reference signals S43 and modified second reference signals S44. The contribution of temporal noise introduced by the set of calibration values is thereby advantageously reduced. Other types of correction formulas are applicable.

7 shows a third embodiment of a pixel 200 according to the present invention. The in connection with the first embodiment according to 3 of a pixel 200 statements made are true. But, there are two differences.

First, the discharge switch N5 is arranged here between the storage node STN and the column line COL. With this configuration, the storage node STN is discharged when the discharge switch N5 is turned on and at the same time the column line COL is pulled to reference potential. A different potential from the reference potential and sufficiently low potential is also usable.

Second, the storage capacitor CS is arranged here between the storage node STN and the first supply voltage Vds.

The third embodiment of a pixel 200 has the advantage that the reference potential is not used within the pixel. Without deviating from the idea of the invention, the two technical features described herein in connection with the third embodiment of a pixel 200 be applied independently.

8th shows a fourth embodiment of a pixel 200 according to the present invention. The in connection with the second embodiment according to 5 of a pixel 200 statements made here are correct. However, there are two differences.

First, the discharge switch N5 has been removed. To perform all required pixel operations, the second supply voltage VDH is implemented as a variable supply voltage.

To discharge the storage node STN, the second supply voltage VDH is set to reference potential and the reset switch N6 is made conductive. During this operation, the second supply voltage VDH may also be different from the reference potential, but it should be sufficiently low to discharge the storage node STN.

For initializing the sensor node FDN, the second supply voltage VDH is set to a predetermined positive voltage, as in the second exemplary embodiment of the pixel 200 has been used. The operation of removing charges on the sensor node FDN is also as described with the second embodiment.

Second, the storage capacitor CS is arranged here between the storage node STN and the first supply voltage Vds.

The fourth embodiment of a pixel 200 has the advantages that the reference potential within the pixel is not used and that the discharge switch N5 is not needed. Without deviating from the idea of the invention, those in connection with the fourth embodiment of a pixel 200 described technical features are also applied independently.

LIST OF REFERENCE NUMBERS

200

pixel

201

pixel field

210

Timing circuit

220

column circuit

221

column block

230

formatted signals

231

processing block

232

Kalibrationswertspeicher

233

digital signals

401

first sequence of a first operating method for a pixel field

402

second sequence of a first operating method for a pixel field

601

first sequence of a second operating method for a pixel field

602

second sequence of a second operating method for a pixel field

901-924

Reference signals in a flowchart relating to embodiments of operating methods for pixels.

COL

column line

CS

storage capacitor

FDN

sensor nodes

G1

first gain factor

G2

second amplification factor

IMN

between nodes

N1

buffer amplifier

N2

output switch

N3

Feedback switch

N4

sampling

N5

discharge switch

N6

reset switch

PPD

Photosensitive element

Pas

third control signal

Rhi

sixth control signal

Rlo

fifth control signal

S41

light signal

S42

modified first reference signal

S43

second reference signal

S44

modified second reference signal

SCC

corrected signal

SST

sampling stage

STN

storage nodes

SUB

substratum

Sel

second control signal

TA

second transfer gate

TG

first transfer gate

Tx

seventh control signal

VDH

second supply voltage

ds

first supply voltage

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• US 7045753 B1 [0015]
• US 7045754 B2 [0017]
• EP 2587794 A2 [0018]

Cited non-patent literature

• Yang, G .; A Snap-Shot CMOS Active Pixel Imager for Low Noise, High-Speed Imaging; IEEE; IEDM; 1998 [0014]

Claims (10)

A pixel field ( 201 ) consisting of a plurality of pixels ( 200 ) arranged in rows and columns, the pixel field ( 201 ) is arranged on a semiconductor substrate (SUB) and wherein a timing control circuit (SUB) also arranged on the semiconductor substrate (SUB) is arranged (FIG. 210 ) the plurality of pixels ( 200 ) are driven so that they have identical integration times and wherein each of the plurality of pixels ( 200 ) comprises: - a photosensitive element (PPD), - a sensor node (FDN), - a first transfer gate (TG) which is arranged between the photosensitive element (PPD) and the sensor node (FDN), - a buffer amplifier (N1), which is connected at its input to the sensor node (FDN) and which is connected at its output to an intermediate node (IMN), - a sampling stage (SST) which contains a sampling switch (N4) and a storage capacitor (CS) and which Input connected to the intermediate node (IMN) and whose output is connected to a storage node (STN), - an output switch (N2), which is arranged between the intermediate node (IMN) and a column line (COL), characterized in that each of Variety of pixels ( 200 ) further comprises: - a feedback switch (N3), which is arranged between the storage node (STN) and the sensor node (FDN), - a reset switch (N6) with a first connection and a second connection, which first connection of the reset switch (N6) is connected to a second supply voltage (VDH). A pixel field ( 201 ) according to claim 1, characterized in that each of said plurality of pixels ( 200 ) further includes: a discharge switch (N5) having a first terminal and a second terminal, which first terminal of the discharge switch (N5) is connected to the storage node (STN). A pixel field ( 201 ) according to claim 1, characterized in that the second terminal of the reset switch (N6) is connected to the sensor node (FDN). A pixel field ( 201 ) according to claim 1, characterized in that the second terminal of the reset switch (N6) is connected to the storage node (STN). A pixel field ( 201 ) according to claims 1 or 2 or 3 or 4, characterized in that the photosensitive element (PPD) is designed as a "pinned" photodiode having a first transfer gate (TG) and optionally a second transfer gate (TA). A pixel field ( 201 ) according to claim 3, characterized in that each of said plurality of pixels ( 200 ) further comprises: a discharge switch (N5) having a first and a second terminal, which first terminal of the discharge switch (N5) is connected to the storage node (STN). A pixel field ( 201 ) according to claim 4, characterized in that each of said plurality of pixels ( 200 ) further comprises: a discharge switch (N5) having a first and a second terminal, which first terminal of the discharge switch (N5) is connected to the storage node (STN). Method for operating a pixel field ( 201 ) according to claim 1, wherein for each of the plurality of pixels ( 200 a reference voltage is stored on the storage node (STN) and a bright state is stored on the sensor node (FDN) and which method is used for each of the plurality of pixels (FIG. 200 ) includes: - providing a bright signal (S41) through the pixel ( 200 during each frame duration, - providing a modified first reference signal (S42) through the pixel ( 200 ) during each frame period, - providing a second reference signal (S43) through the pixel ( 200 ), - providing a modified second reference signal (S44) through the pixel ( 200 ) associated with the second reference signal (S43). The method of claim 8, which is for each of the plurality of pixels ( 200 ) further comprises: generating a corrected signal (SCC) during each frame period based on the bright signal (S41) and the modified first reference signal (S42) and the second reference signal (S43) and the modified second reference signal (S44) and characterized in that the second reference signal (S43) and the modified second reference signal (S44) are provided during each frame period. The method of claim 8, which is for each of the plurality of pixels ( 200 ) further comprises: - generating a set of calibration values based on the second reference signal (S43) and the modified second reference signal (S44), - storing the set of calibration values in a calibration value memory ( 232 ), - generating a corrected signal (SCC) for the pixel ( 200 ) during each frame period based on the bright signal (S41) and the modified first reference signal (S42) and the associated one called set of calibration values, which from the calibration value memory ( 232 ) is read out.

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