DE102015009916A1 - Image sensor arrangement with digital calibration - Google Patents

Abstract

An image sensor array is described which includes a plurality of detector circuits arranged on a semiconductor substrate in rows and columns. A photodiode (PD) is associated with each detector circuit. Each detector circuit includes a sense node (NID) connected to a first terminal of the associated photodiode (PD). Each detector circuit includes a buffer transistor (M2) having a gate connected to the sense node (NID). Each detector circuit includes a hold circuit (HC) including a hold capacitor (Ch) and a hold switch (Sh), the hold circuit (HC) having a control input and a calibration input (NCI). Furthermore, one or more digital-to-analog converters (DAC), which generate a multiplicity of calibration signals, are also located on the semiconductor substrate. Exactly one calibration signal is associated with a detector circuit, and the calibration signal is stored in the detector circuit. Furthermore, a method for operating the image sensor arrangement is also specified.

Description

field of use

The present document relates to an image sensor arrangement according to the preamble of claim 1.

Furthermore, it relates to an image sensor arrangement with a matrix of detector circuits, which is arranged on a semiconductor substrate. More specifically, it relates to the calibration of such detector circuits.

State of the art

Electronic camera functions, which were originally just single devices for video recording or photography, are now ubiquitous and can be found in virtually every portable electronic device, such as cell phones, organizers, tablet computers, etc. Such bulk products include image sensors fabricated in silicon CMOS technologies become.

• • ein lichtempfindliches Element – meist eine Fotodiode,
• • andere Schaltungsteile, die im Folgenden „Detektorschaltung” genannt werden. Die Detektorschaltung ist für das Zurücksetzendes Pixels in den anfänglichen Dunkelzustand und das Auslesen der Helligkeitsinformation aus dem Pixel zuständig.

Such CMOS image sensors typically include a plurality of pixels arranged in rows and columns as a pixel matrix. Each pixel contains

• A photosensitive element, usually a photodiode,
• • other parts of the circuit, referred to below as the "detector circuit". The detector circuitry is responsible for resetting the pixel to the initial dark state and reading out the brightness information from the pixel.

The principle of the "active pixel" as well as the in 1 pictured circuit were first in " Noble, P; Self-Scanned Silicon Image Detector Arrays; IEEE; Tred; 1968 " released.

To understand the operation, it must be remembered that the sense node NID in 1 has a node capacity. This is composed of the junction capacitance of the reverse-biased photodiode PD, the gate capacitance of the buffer transistor M2, and various parasitic capacitances.

During operation, a reset transistor M3 is made conductive for a short time, so that the capacitance of the sense node NID is charged to a high voltage. "Vdd" in the figure should mean that a supply voltage is connected here. A photocurrent is generated by incident light in the photodiode PD, so that the node capacity is discharged. This is done more or less quickly, depending on the light intensity. After a fixed integration time specified by the user, a sense node potential of the sense node NID accordingly results accordingly. The sense node potential thus reflects the intensity of the light incident on the photodiode PD.

Furthermore, a buffer transistor M2 and a selection transistor M4 are provided, the latter acting as a selector switch. By means of these elements, a voltage corresponding to the sense node potential can be applied to the column line Col and in this way becomes accessible outside the pixel matrix. The whole process described is usually repeated line-sequentially. Again, for a given line, it repeats according to the desired frame rate.

There are a number of challenges in designing a good pixel and achieving better and better image quality. Some problems result from semiconductor physics and the imperfect precision of semiconductor fabrication.

Photodiodes have dark currents, other components have leakage currents. These effects are temperature dependent and also different from individual to individual. Furthermore, the production of a number of identical elements on a same chip is not possible. In principle, parameters of two desired identical elements are slightly different. This effect is called "Mismatch". For example, the difference in threshold voltage in buffer transistors M2 from pixel to pixel is important and of practical importance. If you could not correct it, pictures showed a disturbing inhomogeneity. Mismatch is related to the terms tolerance and scatter.

The above effects are usually overcome by compensation schemes, and calibration techniques have been developed.

2 Figure 4 shows a known circuit using certain methods for calibrating each pixel. The goal is to correct the mismatch of the components between pixels. The circuit can be found as 4 in US6355965B1 ,

The dashed lines on the right side with the column amplifier AMPD and the current source JS exist only once for each column. The circuit part on the left represents a pixel of the pixel matrix.

A reverse biased photodiode PD is present. In regular operation, it is connected via a signal switch S12 to the sense node NID. The gate of a buffer transistor M2 is also connected to the sense node. A sense node potential of the sense node NID can thus be sent to the column line Col via the buffer transistor M2 and the readout switch S4.

The current of the photodiode PD also flows through a first transistor M1 and a load transistor M3. These transistors form a load circuit with a logarithmic U / I characteristic. The difficulty with this load circuit is that the transistors are operated at very low currents and have significantly different characteristics. This results in a very large scatter of the sense node potentials from pixel to pixel for the same photocurrent.

For calibration, the signal switch S12, a hold switch Sh and a switch S5 are operated. The result is a control loop which forces a voltage Vout1 to become equal to a reference voltage Vrf. In the process, a reference current Iref flows from the sense node NID. After some time, the gate of the load transistor M3 has settled to a certain potential. A hold capacitor Ch and a hold switch Sh form a hold circuit. When the calibration has ended, the hold switch Sh is nonconductive and the voltage on the hold capacitor Ch is stored. The potential at the gate of the load transistor M3 is thus held.

In a conventional CMOS image sensor, the photodiode PD is realized on the same semiconductor substrate as the detector circuit. Peripheral circuits such as analog-to-digital converters or digital signal processing functions are also arranged on the same semiconductor substrate, which is a silicon substrate.

Silicon based photodiodes are very suitable for detecting visible light. In order to detect light of other wavelengths, for example, NIR ("Near Infra Red"), other semiconductor materials such as the compound semiconductors GaAs, InGaAs or HgCdTe are preferable.

It is known that a matrix of photodiodes can be produced on substrates made of compound semiconductors, and that a matrix of the detector circuits together with further functional blocks can be produced on a silicon substrate. The latter circuit is commonly referred to as "ROIC - Read Out Integrated Circuit". Both substrates can be combined at the end of production with "bumping technologies". As references see US5665959 or US7551059B2 ,

task

There is a need for image sensor assemblies that can achieve accurate dark current correction, device tolerances, and backlighting.

Solution of the task

The solution is given by an image sensor arrangement according to claim 1.

• • einen Sense-Knoten NID, welcher mit einem ersten Anschluss der zugeordneten Fotodiode PD verbunden ist;
• • einen Puffertransistor M2 mit einem Gate-Anschluss, welcher mit dem Sense-Knoten NID verbunden ist;
• • eine Halteschaltung HC, bestehend aus einem Haltekondensator Ch und einem Halteschalter Sh, wobei die Halteschaltung HC einen Steuereingang und einen Kalibriereingang NCI aufweist.

Auch sind einer oder mehrere Digital-Analog-Umsetzer DAC auf dem Halbleitersubstrat angeordnet. Die Digital-Analog-Umsetzer DAC erzeugen eine Vielzahl von Kalibriersignalen. Jedes der Vielzahl von Kalibriersignalen ist genau einer der Vielzahl von Detektorschaltungen zugeordnet und wird in dieser gespeichert.The image sensor array includes a plurality of detector circuits arranged on a semiconductor substrate in rows and columns. Each of the plurality of detector circuits is associated with a photodiode PD. Each of the plurality of detector circuits includes:

• A sense node NID which is connected to a first terminal of the associated photodiode PD;
• A buffer transistor M2 having a gate terminal connected to the sense node NID;
• A holding circuit HC, comprising a holding capacitor Ch and a holding switch Sh, the holding circuit HC having a control input and a calibration input NCI.

Also, one or more digital-to-analog converters DAC are disposed on the semiconductor substrate. The digital-to-analog converters DAC generate a large number of calibration signals. Each of the plurality of calibration signals is associated with and stored in exactly one of the plurality of detector circuits.

Further advantages and improvements can be achieved by measures that are described in the dependent claims.

Furthermore, a method for operating an image sensor arrangement described above is specified.

Applicability and Advantages of the Invention

It is advantageous that a calibration value for a detector circuit is stored in the detector circuit itself, more precisely in a holding circuit. This allows for an individual calibration value for each detector circuit and that it only needs to be refreshed at a low refresh rate, or only when necessary.

The calibration information is prepared by the digital signal processing, converted into an analog value by means of a digital-to-analog converter, then sent to a detector circuit and stored there.

An image sensor arrangement according to the invention generates calibration signals from digital calibration words. Digital calibration words can compute an algorithm with virtually unlimited accuracy.

Advantageously, digital calibration status words can be stored in a digital memory on the same semiconductor substrate. This allows for lossless storage.

The algorithm for calculating the calibration values can be very complex. It is possible to realize digital filters with very large time constants as well as adaptive algorithms.

The three last mentioned properties can not be achieved by means of a purely analogue realization.

The algorithm for calculating the calibration values can also be realized by means of a programmable processor, which results in the flexibility advantages of software solutions.

Preferred embodiments are particularly suitable for the realization of control loops with very large time constants. This allows the compensation of temperature drift effects and the suppression of background light. The elimination of such irrelevant information has a positive effect on the usable dynamic range.

An alternative realization of large time constants with analog means may in particular require very large capacitors and other large components which, because of the mere dimensions, can not be accommodated within a single pixel.

According to a preferred embodiment, digital elements for such slow control loops can be arranged outside the matrix of pixel circuits, so that small pixel circuits are possible.

Producing the calibration state words not on the semiconductor substrate but outside by means of complex devices from the signal data stream of the detector assembly, one gains further flexibility. The calibration status words are then sent back to the sensor array and stored in digital memory on the semiconductor substrate.

According to a preferred embodiment, the calibration status words are generated purely on the basis of the signal words supplied by the analog-to-digital converter. This avoids additional circuit complexity and also DC offset error of the image information.

drawings

The following drawings relate to the prior art and to preferred embodiments of the invention.

1 is a circuit diagram of a pixel according to the prior art.

2 is a schematic diagram for an analog calibration of a pixel according to the prior art.

3 shows a first embodiment illustrating a pixel and various functional blocks in detail.

4 is the circuit diagram of a pixel according to a second embodiment.

5 shows a third embodiment, wherein the main functional blocks of a complete image sensor arrangement are shown.

6 shows as a fourth embodiment, the detail structure of the digital signal processing block and the digital memory.

7 shows as a fifth embodiment, the flowchart of an operating method for a detector arrangement according to the invention.

embodiments

In the figures, transistors M1, M2, ... are shown, which are drawn as MOB field-effect transistors and which are referred to below as "MOSFETs" or "transistors". The drawn MOSFETs are of the n-channel type or of the p-channel type. The latter has a circle in the symbol.

The transistors may also be other types of field effect transistors. Similarly, the channel type of the transistors as well as the polarity of the diodes, photodiodes, voltages and currents could be different without departing from the spirit of the invention.

A MOSFET has a gate terminal, a drain terminal and a source terminal. The gate terminal is also called "gate" or "control input". One of the drain and the source connections is also called "first output" below. The other of the drain and the source connections is also called "second output" below.

Transistors are often used as switches. A switch should have a first output and a second output and a control input exhibit. In this case, the first output is conductively connected to the second output when a suitable signal is applied to the control input.

The phrase "a transistor or switch is located between node A and node B" is intended to mean that in a transistor or switch, its first output is connected to node A and its second output is connected to node B.

3 is a circuit diagram of a first embodiment. For clarity, the circuit diagram shows only one pixel CDP of a plurality of pixels and a set of elements that does not belong to the pixel or pixels. The set of elements is disposed on the semiconductor substrate and includes an analog-to-digital converter ADC, a digital signal processing block DSP, a digital memory MEM, and a digital-to-analog converter DAC.

The pixel CDP includes a photodiode PD and a detector circuit. The detector circuit does not include the photodiode PD but the other components in the pixel CDP. The detector circuit and other similar detector circuits form a plurality of detector circuits arranged on a semiconductor substrate in rows and columns. Preferably, the semiconductor substrate is a silicon substrate.

A first terminal of the photodiode PD is connected to a sense node NID. A second terminal of the photodiode PD is connected to a reference potential. An input of a buffer amplifier BUF is also connected to the sense node NID. A buffer output NOB of the buffer amplifier BUF is connected to an input of a read low pass LPFR and to an input of a comparator circuit CMP. The comparator circuit CMP has a comparator output OTP. An output of the read low pass LPFR is connected to the first output of a select switch S4. A selection signal Tss is applied to the control input of the selector switch S4. The second output of the selection switch S4 is connected to a read column line ColR.

The person skilled in the art is aware of column lines, and thus it is clear that the read column line ColR is connected to second outputs of selectors in other detector circuits located in the same column of detector circuits.

The same applies mutatis mutandis to a write column line ColW. A calibration input NCI of the detector circuit is connected to the write column line ColW. The detector circuit also includes a latch circuit HC. The holding circuit HC includes a holding switch Sh whose first output is connected to the calibration input NCI and whose second output is connected to a holding output NOH of the holding circuit HC. A hold signal Tsh is applied to a control input of the hold switch Sh. A first terminal of a hold capacitor Ch is also connected to the hold output NOH. A second terminal of the holding capacitor Ch is connected to the reference potential. The hold output NOH is connected to an input of a write low pass LPFW. An output of the write low pass LPFW is connected to the gate of a load transistor M3. The first output of the load transistor M3 is connected to a supply voltage Vdd. There is also a first transistor M1 in the detector circuit. The first output and the gate of the first transistor M1 are connected to the second output of the load transistor M3. The second output of the first transistor M1 is connected to the sense node NID.

Furthermore, the read column line ColR is fed to an input of the analog-to-digital converter ADC. The output of the analog-to-digital converter ADC is connected to a signal input WFA of the digital signal processing block DSP. The digital signal processing block DSP is connected to the digital memory MEM. Preferably, the digital memory MEM is realized by means of one or more read-write memories, so-called RAMs. The digital signal processing block DSP also has a signal output OTX and a calibration output WTD. The calibration output WTD is connected to an input of the digital-to-analog converter DAC. An output of the digital-to-analog converter DAC is fed to the write column line ColW.

In practice, between the read column line ColR and the input of the analog-to-digital converter ADC are usually still analog circuit functions, such as amplifiers, multiplexers, etc., which are not shown here for simplicity.

The following is the function of the circuit in 3 explained. The load transistor M3 is an n-channel MOSFET and it works as a source follower. The first transistor M1 is configured as a diode. Together, the first transistor M1 and the load transistor M3 form a load with a non-linear voltage-current characteristic, which depends on the parameters of the two transistors and also on the gate potential of the load transistor M3. This load circuit is connected to the sense node, to which the first terminal of the photodiode PD is connected.

On the photodiode PD incident light can flow a photocurrent. At the sense node NID, a sense node potential is formed, which depends on the light intensity and the characteristics of the load circuit. The buffer amplifier BUF forwards the sense node potential to its buffer output NOB - for simplification we assume here that this potential remains unchanged. Subsequently, the potential is filtered by means of the read low pass LPFR and a sensor signal results. This is sent to the read column line ColR when the selection signal Tss activates the selection switch S4.

The analog-to-digital converter ADC receives the sensor signal at its input and provides a sensor word in digital format at its output. The sensor word is output to the signal input WFA of the digital signal processing block DSP. Within the digital signal processing block DSP, calculations are performed and a calibration word is output at the calibration output WTD. The digital signal processing block DSP also provides image information at the signal output OTX and the image information is output from the image sensor array.

Preferably, the digital signal processing block realizes the algorithm of a temporal low-pass filter. The internal state or states of the filter are stored in the digital memory MEM and accessed as needed.

The calibration word is sent to the digital-to-analog converter DAC. This converts it to an analog calibration signal, which is fed to the calibration input NCI of the detector circuit. When the hold switch Sh is operated by a pulse of the hold signal Tsh, it passes the calibration signal to the hold capacitor Ch where it is stored. The potential at the hold output NOH is then low-pass filtered by the write low pass LPFW, and finally reaches the gate of the load transistor M3. The write low pass LPFW also serves to suppress existing stages and transients at the hold output NOH. The low-pass writer LPFW operates as a reconstruction low-pass filter intended to suppress higher-order sampling spectra.

The characteristic of the load transistor M3 is adjusted by means of its gate voltage. When the potential of the sense node NID decreases, this information propagates through the path described above and then leads to a potential increase at the gate of the load transistor M3. This causes an increased current through the load transistor M3, so that the potential of the sense node NID increases.

Overall, the embodiment described functions as a control loop which suppresses constant signal components and attenuates low-frequency signal components of the sense node NID. In the application, components are suppressed based on mismatch of components, temperature drift and background light.

In this embodiment, a multiplication by a factor "-1" in the feedback loop is needed for a correct function. The factor can be well realized in the DSP digital signal processing block, but signal inversion elsewhere in the loop is also possible.

In this embodiment, there are separate column lines: a read column line ColR and a write column line ColW. As a variant of the embodiment, it is also possible to mentally connect the read column line ColR and the write column line ColW, so that a solution results with only one column line. The digital-to-analog converter DAC then sends its output signal to this one column line. And the analog-to-digital converter ADC then receives its sensor signal from this one column line. Obviously, collisions must be avoided here, the writing and reading operations are therefore time-sequential. This alternative embodiment has the advantage of saving space in the pixel at the cost of a somewhat slower operating speed.

A detailed circuit diagram of a pixel shows 4 as a second embodiment. Again, the pixel CDP includes the detector circuit and the photodiode PD. Compared with the first embodiment in FIG 3 Here are more detailed representations or alternative implementations for some function blocks.

Connected to the sense node NID is the gate of a buffer transistor M2. The first output of the buffer transistor M2 is connected to the reference potential. There is also a fifth transistor M5 available. The first output of the fifth transistor M5 is connected to the supply voltage Vdd. The gate of the fifth transistor M5 is connected to a second bias voltage Vbias2. The second output of the fifth transistor M5 and the first output of the buffer transistor M2 are connected and form the buffer output NOB. In this configuration, both transistors are plotted as p-channel MOSFETs. The buffer transistor M2 operates as a source follower. The fifth transistor M5 operates as a current source serving as a load element for the source follower.

In this embodiment, the read low pass LPFR is no longer present. The size of the detector circuit is reduced if it can be omitted, which in turn is possible when the high frequency component of the potential at the sense node NID is low and does not lead to disturbing aliasing effects.

The buffer output NOB is connected to the first output of a selection transistor M4. The second output of the selection transistor M4 is connected to the read column line ColR. The selection signal Tss is applied to the gate of the selection transistor M4. Thereby, the potential of the buffer output NOB is supplied to the read column line ColR when the selection transistor M4 is rendered conductive. The buffer output NOB is also connected to the input of the comparator CMP.

The holding circuit HC in turn includes the holding capacitor Ch. The holding switch is realized here by means of a holding transistor M6. The hold transistor M6 is arranged between the calibration input NCI and the hold output NOH. The hold signal Tsh is applied to the gate of the hold transistor M6.

Another difference from the first embodiment relates to the write low pass LPFW. It is realized by means of a filter resistor Rw and a filter capacitor Cw. Both components form a first-order RC low-pass filter. A first terminal of the filter resistor Rw is connected to the hold output NOH. A second terminal of the filter resistor Rw is connected to the gate of the load transistor M3. A first terminal of the filter capacitor Cw is also connected to the gate of the load transistor M3. A second terminal of the filter capacitor Cw is connected to the supply voltage Vdd.

Another difference compared to the first embodiment relates to the load circuit of the photodiode PD. The load transistor M3 and the first transistor M1 are here both designed as p-channel MOSFETs. This load circuit has a different behavior. The gate of the load transistor M3 is connected to the first terminal of the filter capacitor Cw. The load transistor M3 operates as a voltage-controlled current source. The first transistor M1 turns the load circuit into a cascode arrangement having a larger output impedance. The gate of the first transistor M1 is connected to a first bias voltage Vbias1. The first output of the load transistor M3 is connected to the supply voltage Vdd. The supply voltage Vdd is positive with respect to the reference potential. The second output of the load transistor M3 is connected to the first output of the first transistor M1. The second output of the first transistor M1 is connected to the sense node NID. The present embodiment aims for a linear characteristic. Without departing from the basic idea of the invention, the first transistor M1 can be omitted, that is, replaced by a conductive connection between its first output and its second output when a high output impedance is not required. Alternative arrangements of high-voltage voltage-controlled current sources are also familiar to the person skilled in the art.

Because of the current source characteristic of the load transistor, the sense node NID has a constant impedance here. In the first embodiment, the impedance and thus the small signal gain with increasing photocurrent are lower. This complicates the dimensioning of the control loop and involves the risk of unstable operating conditions.

5 presents a fourth embodiment. Shown is an image sensor arrangement including a pixel matrix DCA, which includes a plurality of pixels CDP as well as other functional blocks, which will be explained below.

Alone 5 The elements shown are arranged on the semiconductor substrate, wherein optionally the photodiodes PD of the pixels CDP may be external and are not arranged on the semiconductor substrate.

One column of pixels CDP are associated with a write column line ColW and a read column line ColR. The read column line ColR is connected to an input of a column amplifier AMP. There is one column amplifier AMP per column of pixels. The outputs of the column amplifier AMP are connected to a multiplexer MUX. An output of the multiplexer MUX is connected to an input of an analog-to-digital converter ADC. An output of the analog-to-digital converter ADC is connected to a signal input WFA of a signal processing block DSP. The digital signal processing block DSP also has a signal output OTX, a calibration output WTD, and the block is connected to a digital memory MEM.

The calibration output WTD is connected to an input of a shift register, which consists of a chain of register stages REG. At the output of each register stage REG, a digital-to-analog converter DAC is connected, which is connected with its output to one of the write column lines ColW.

In this embodiment, there are an analog-to-digital converter ADC and a digital signal processing block DSP. But it gives a digital-to-analog converter DAC per column of pixels. Therefore, the analog-to-digital converter and the digital signal processing block must be fast enough to operate at the pixel rate of the image sensor array. A digital-to-analog converter DAC operates only with a line frequency of the image sensor arrangement.

Without deviating from the idea of the invention, a larger number of analog-to-digital converters ADC can be provided. Likewise, a completely different number of digital signal processing blocks DSP could be present. Also, within the scope of the invention, it is possible to use a different number of digital-to-analog converters DAC, including the case of using only a single high-speed digital-to-analog converter DAC.

These cases require that one must provide multiplexers or buffers at the inputs and outputs of one or more signal processing blocks DSP, or that the outputs of the DAC must be stored in Sample & Hold stages for the write column lines. Depending on the availability of such functional blocks in a given silicon manufacturing process, an optimal configuration can be chosen.

Alternatively, the digital signal processing block DSP can be realized by means of an embedded processor. It is also possible to access the digital memory MEM from an external system and in this way to write or read out calibration status words.

The operation of the present embodiment is again line by line. At a time, a first row of pixels CDP is selected. Each of the selected pixels CDP provides a sensor signal over the read column line ColR to the column amplifier AMP of its column. The multiplexer MUX transmits a set of sensor signals for the first line - time sequential - to the analog-to-digital converter ADC. The analog-to-digital converter ADC supplies a corresponding set of sensor words to the digital signal processing block DSP. The latter in turn provides a corresponding set of calibration words which are inserted into the shift register. Each of this set of calibration words is input to one of the digital-to-analog converters DAC, each DAC providing a calibration signal. Each of the calibration signals is forwarded via a write column line ColW to one of the pixels in the first row and then stored in the same pixel. The described method is repeated line by line, and when all lines of an image are processed, the image is then repeated.

6 shows as fourth embodiment, the detail structure of the digital signal processing block DSP and the digital memory MEM. The digital memory MEM includes a plurality of cells each storing a calibration status word. Each of the plurality of detector circuits is associated with exactly one calibration status word.

Without deviating from the idea of the invention, the calibration status word can consist of an arbitrary number of bits and also of different values with different technical meaning.

Furthermore, a number of logical functions are shown, among them an adder ADD, a subtracter SUB, a coefficient multiplier COF and an output multiplexer SOL. The signal input WFA, the calibration output WTD and the signal output OTX are also shown.

Whenever a sensor word is received at the signal input WFA, a calibration status word is read from a word cell MWxy of the digital memory MEM. This reading process is illustrated by the "RX" in the figure. Control circuits not shown here ensure that the word cell MWxy is always associated with a specific pixel and that this also corresponds to the sensor word that is currently at the signal input WFA.

With the subtracter SUB, the calibration status word is subtracted from the sensor word and output as a high-pass signal OT2. Further, the coefficient multiplier COF multiplies the calibration status word by a user-specified digital number and passes the result to the adder ADD, which adds the sensor word and provides a calibration word at the calibration output WTD. The predetermined digital number is also called the coefficient value.

The structure with the word cell MWxy of the digital memory MEM, with the coefficient multiplier COF and the adder ADD forms a first-order recursive low-pass filter. For example, choosing a coefficient value of +0.94 results in a 3 dB cutoff frequency of a few kilohertz, assuming that the pixel is read at a rate of 50 kHz. Last value is to be regarded as sampling frequency of the filter.

Therefore, you can also call the calibration word as a data word of a low-pass signal OT3. The calibration word is finally written into the word cell MWxy, thus effectively the replaced previous calibration status word. The writing process is indicated in the figure by the "WX".

The sensor word at the signal input WFA is identical to OT1. So you can take OT1 as a digital sensor signal. By means of the output multiplexer SOL, the user can select the digital sensor signal OT1 or the high-pass signal OT2 or the low-pass signal OT3. An alternative embodiment of an image sensor arrangement could also output two or all signals simultaneously.

The output OTX sequentially supplies a plurality of signal words, each corresponding to one of the plurality of pixels. By repeating with the frame rate, a video signal is output at the OTX output.

7 shows as a fifth embodiment, the flowchart of an operating method for a detector arrangement according to the invention. The described method is performed for each of the plurality of pixel and detector circuits.

The pixel CDP includes a photodiode PD and a detector circuit. Initially, the pixel CDP is selected. This causes a transmission 10 a sensor signal from the detector circuit to the read column line ColR. The sensor signal is input to the analog-to-digital converter ADC 11 , The analog-to-digital converter ADC digitizes the sensor signal and provides a sensor word in digital format. The sensor word is provided for a digital signal processing block DSP 12 , The digital signal processing block DSP generates 13 a calibration word and outputs it at its calibration output WTD. The generation of the calibration word involves digital computations and accessing data of the digital memory MEM. The calibration word is input to the digital-to-analog converter DAC 14 , which generates a calibration signal accordingly 15 , The calibration signal is an analog signal, for example, it may be a voltage or an electric current. The calibration signal is output to the detector circuit 16 , The calibration signal is stored in the detector circuit 17 , The stored calibration signal influences the operation of the detector circuit. As described above, this changes the characteristics of a load circuit in the pixel.

The sequence of the operations described is repeated periodically. Preferably, the repetition rate corresponds to the frame rate. The sampling frequency of the recursive filter and other elements of the control loop are then equal to the frame rate.

Preferably, the process described above is carried out continuously. In that case, the control loop suppresses all electrical offsets and temperature drift effects, and - also advantageous - background light is suppressed. Background light is intended to mean light of constant intensity on the pixels.

Also, slowly changing light intensities should be meant so that the control loop is able to follow and correct such variations. For the comparator circuit CMP, which receives the sensor signal at its input, such components are then no longer visible.

Alternatively, one may perform the process only during a calibration time of limited duration. during the calibration time, the sensor assembly is in a dark condition. At the end of the calibration time, the writing of calibration status words to memory is stopped. As a result, the calibration signal sent to the detector circuit then remains unchanged during the subsequent regular operation. This mode only compensates for static electrical offsets.

For the invention, the existence of the digital memory MEM on the semiconductor substrate is not a necessary element, nor is the use of the digital memory MEM. It is also possible to load the digital memory MEM by means of a device that is not located on the semiconductor substrate and to read out the calibration status words from the digital memory MEM for use on the semiconductor substrate.

The described embodiments include various features that can be combined with each other differently than shown, without departing from the spirit of the invention.

LIST OF REFERENCE NUMBERS

• ADC

  Analog-to-digital converter

  ADD

  adder

  AMP

  column amplifiers

  BUF

  buffer amplifier

  CDP

  pixel

  CMP

  comparator

  COF

  coefficient

  ch

  hold capacitor

  Col

  column line

  COLR

  Read column line

  COLW

  Write-column line

  cw

  filter capacitor

  DAC

  Digital-to-analog converter

  DCA

  pixel matrix

  DSP

  digital signal processing block

  HC

  hold circuit

  JS

  power source

  LPFR

  Reading lowpass

  LPFW

  Write lowpass

  M1

  first transistor

  M2

  buffer transistor

  M3

  load transistor

  M4

  selection transistor

  M5

  fifth transistor

  M6

  holding transistor

  MEM

  digital memory

  MUX

  multiplexer

  MWxy

  a word cell of the digital memory MEM

  N3

  reset transistor

  NCI

  calibration input

  NID

  Sense nodes

  NOB

  buffer output

  NOH

  hold output

  OT1

  digital sensor signal

  OT2

  High-pass signal

  OT 3

  Lowpass signal

  OTP

  comparator output

  OTX

  signal output

  PD

  photodiode

  REG

  register stage

  rw

  filter resistance

  RX

  Reading the digital memory

  S12

  signal switches

  S4

  selector switch

  S5

  fifth switch

  SOL

  output multiplexer

  Sh

  hold switch

  SUB

  subtractor

  Tsh

  stop signal

  tss

  select signal

  Vbias1

  first bias voltage

  Vbias2

  second bias voltage

  Vdd

  supply voltage

  WFA

  signal input

  WTD

  calibration output

  WX

  Write operation of the digital memory MEM

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• US 6355965 B1 [0012]
• US 5665959 [0019]
• US 7551059 B2 [0019]

Cited non-patent literature

• Noble, P; Self-Scanned Silicon Image Detector Arrays; IEEE; Tred; 1968 [0005]

Claims (10)

An image sensor array including a plurality of detector circuits arranged on a semiconductor substrate in rows and columns, wherein a photodiode (PD) is associated with each of the plurality of detector circuits, and wherein each of the plurality of detector circuits includes: - a sense node (NID), a buffer transistor (M2) having a gate terminal, which gate terminal is connected to the sense node (NID), wherein the hold circuit includes a hold capacitor (Ch) and a hold switch (Sh), and wherein the hold circuit (HC) has a control input and a calibration input (NCI), characterized in that one or more digital-to-analog converters (DAC) on the semiconductor substrate are arranged, wherein the one or more digital-to-analog converter (DAC) a plurality of calibration generate and each of the plurality of calibration signals to exactly one of the plurality of detector circuits out and stored by means of the holding circuit of the same detector circuit. An image sensor device according to claim 1, characterized in that each of said plurality of detector circuits further includes a load transistor (M3) having a first output and a second output, said load transistor (M3) being a P-channel type MOS field-effect transistor, and wherein first output of the load transistor (M3) is connected to a positive supply voltage relative to a reference potential, and wherein the second output of the load transistor (M3) is connected to the sense node (NID). An image sensor arrangement according to claim 1, characterized in that each of the plurality of detector circuits further includes a first transistor (M1) and a load transistor (M3) having a first output and a second output, the load transistor (M3) being a MOS field-effect transistor from the P-type. Channel type is carried out and wherein the first output of the load transistor (M3) is connected to a reference potential positive supply voltage and wherein the first transistor (M1) between the sense node (NID) and the second output of the load transistor (M3) is arranged , An image sensor device according to claim 1, characterized in that each of the plurality of detector circuits is disposed on a semiconductor substrate made of silicon and that the photodiodes (PD) are disposed on a semiconductor substrate made of a compound semiconductor. An image sensor arrangement according to claim 2 or 3, characterized in that each of the plurality of detector circuits provides a sensor signal, and that on the semiconductor substrate one or more analog-to-digital converters (ADC) are arranged which receive sensor signals and output sensor words representing these sensor signals , Image sensor arrangement according to claim 5, characterized in that one or more digital signal processing blocks (DSP) are arranged on the semiconductor substrate, wherein the digital signal processing blocks (DSP) receive the sensor words and supply calibration words which are sent to the digital-to-analog converter (DAC) , An image sensor arrangement according to claim 2 or 3, characterized in that a digital memory (MEM) is arranged on the semiconductor substrate, wherein the digital memory (MEM) stores a plurality of calibration state words which are stored in separate memory cells and wherein each of the plurality of Detector circuits is associated with a calibration status word. Image sensor arrangement according to claim 6, characterized in that the image sensor arrangement has a signal output (OTX) and the signal output (OTX) simultaneously or optionally provides: • a digital sensor signal (OT1), • a high-pass signal (OT2), • a low-pass signal (OT3). A method of operating an image sensor array according to claim 1, characterized in that it includes for each of the plurality of detector circuits: - inputting ( 14 ) of a calibration word, which is associated with the detector circuit, in one of the digital-to-analog converter (DAC), - Generate ( 15 ) of a calibration signal by the one of the digital-to-analog converters (DAC), - output ( 16 ) of the calibration signal to the calibration input (NCI) of the detector circuit, - Save ( 17 ) of the calibration signal in the detector circuit. Method according to claim 9, characterized in that it further comprises: - sending ( 10 ) a sensor signal from the detector circuit to a read column line (ColR); - Enter ( 11 ) of the sensor signal into the analog-to-digital converter (ADC); and - providing ( 12 ) of a sensor word for the digital signal processing block (DSP). - To generate ( 13 ) of a calibration word by the digital signal processing block (DSP).

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