DE102009056981A1 - Manufacturing process for semiconductor devices - Google Patents

Abstract

A circuit layer 2 having a terminal conductor part 21 which can be connected to an electrode 31 of a semiconductor element 3 is formed on a metal support substrate 1 in such a manner that the circuit layer can be peeled off from the substrate 1 and that the terminal lead part 21 on the upper surface of the circuit layer is exposed. The circuit layer 2 is laminated on the element 3 while being in the wafer state, and the lead portion 21 and the electrode 31 are connected to each other. Subsequently, the supporting substrate 1 is peeled off from the circuit layer 2, and the wafer is singulated to obtain individual semiconductor devices.

Description

Field of the invention

The The present invention relates to a method of manufacture a semiconductor device comprising a semiconductor element and a arranged thereon circuit layer.

Background of the invention

Semiconductor elements, which are configured with different semiconductor materials (in Hereafter simply referred to as "elements"), like smart cards using silicon semiconductor and organic EL elements are usually made by: repeatedly forming a matrix of multiple elements on a wafer substrate and then the substrate is singulated into individual elements, called chips are known. In the following description, a wafer substrate will be described with a semiconductor element formed thereon (state before the Singulate) also referred to as "semiconductor wafer".

Next The basic element structure becomes different in a semiconductor element Interconnection structures made while in the wafer state is to add sophisticated features, and for other purposes. To these interconnection structures For example, a redistribution layer, a conductor path (Contact hole), which allow the area on the element side and the back surface over a wafer substrate electrically communicate with each other, and the like.

As in JP-A-2000-243754 For example, an aluminum electrode (an electrode contact surface integrated into a member as a semiconductor element structure) is formed, and thereafter, an insulation layer, a copper-plated layer, and the like are sequentially formed thereon to form a redistribution layer.

After this provided it with an interconnection structure and subdivided into chips each element serves as a semiconductor device with a lead, the connection with external conductors (external circuits and the like) and their mounting compared to the original one Element which simply has an exposed electrode facilitates.

By doing For example, a rewiring layer can be provided Aluminum electrodes of the element and conductors on an external circuit for Mount the item easily be joined together, too if they are in terms of size or grid of each other differ.

connections can on the back of a wafer substrate be formed by providing contact holes, which penetrate the wafer substrate in the direction of the substrate thickness.

By Exploration of such interconnection structures that become a semiconductor element to add, the inventors found out that it room for improvement in the two points mentioned below gave and identified these as problems arising from the present To be solved invention.

Of the First point concerns the manufacturing costs with respect to a redistribution layer. The inventors found that the processing for training a redistribution layer directly on a semiconductor wafer tedious is because it is necessary to have a redistribution layer on each one Semiconductor wafer build, so there is still room for a Reduction of manufacturing costs, even if not as Problem was considered. If it turns out that a trained Redistribution layer of insufficient quality, even if the obtained semiconductor wafer as a whole of more acceptable Quality is, the co-disposal of the semiconductor wafer unavoidable, which increases the cost of production, as the Redistribution layer already monolithic on the semiconductor wafer was trained.

Of the second point concerns quality when in a semiconductor wafer a contact hole is formed, to which a separately formed interposer (a kind of interconnect substrate used for chip assembly is interposed) is connected. As a contact hole usually is formed by adding a conductive paste in fills a through-hole, its two can Protrude from the substrate surfaces of the semiconductor wafer, and the heights of the protruding parts are variable. If an interposer between an element with such protruding parts and an external leader is placed while both interconnected causes the different height the protruding parts have a small gap in the interface between the interposer and the semiconductor wafer, which in some cases Elements in turn can cause a contact failure and the Reliability of the semiconductor device reduced.

The problems to be solved by the present invention reside in the improvement of the two points described above which the inventors have found. It is a first object of the present invention to provide a manufacturing method which can reduce the manufacturing cost of redistribution layers on semiconductor elements made possible. A second object of the present invention is to provide a manufacturing method that enables the production of a gapless semiconductor device even in the presence of different heights of protruding parts at the ends of a contact hole.

Brief description of the invention

The Inventors undertook extensive research to address those described above To solve problems, and found that the two described above Problems can be solved simultaneously by one rewiring layer as a wiring layer independently from a semiconductor wafer and the wiring layer so with a carrier layer of metal that provides the carrier layer can be separated. The inventors conducted further investigations on the basis of this result and developed the present invention.

Accordingly The present invention has the following features.

• (1) Method of manufacturing a semiconductor device with a structure in which a semiconductor element and a circuit layer laminated together, the method comprising the following steps includes: Forming a circuit layer with a lead portion, which are connected to an electrode of a semiconductor element can, in such a way that the circuit layer on a Metal support substrate are removed from the substrate can and that the connecting conductor part on the upper surface the circuit layer is exposed; Laminating the circuit layer to the semiconductor element while in the wafer state, wherein the lead portion of the circuit layer and the electrode the semiconductor element are interconnected; and Split off of the metal carrier substrate from the circuit layer the connecting.
• (2) Manufacturing method according to the above point (1), wherein there is a release layer between the metal support substrate and the circuit layer, whereby the circuit layer of can be deducted from the metal support substrate.
• (3) Manufacturing method according to the above point (2) wherein the release layer is a layer that is formed the release layer is easily peeled off the circuit layer and can not be easily separated from the metal support substrate peel off, leaving the release layer together with the metal carrier substrate from the circuit layer can be removed.
• (4) Manufacturing method according to the above point (2) wherein the release layer is polyimide.
• (5) Manufacturing method according to the above point (2), wherein the release layer is made of a material consisting of Metals, metal oxides and inorganic oxides selected is.
• (6) Manufacturing method according to the above point (1), wherein the circuit layer as a redistribution layer for the semiconductor element functions.
• (7) Manufacturing method according to the above point (1), wherein the circuit layer comprises: an insulation layer; a conductive layer located in the insulating layer; one Terminal conductor part for connection to an electrode of a semiconductor element on a surface of the insulating layer; and one External connection conductor part for connection to an external conductor on the other surface of the insulating layer; and in which the connection conductor part and the external connection conductor part via the conductive layer, which is in the insulation layer is connected to each other.
• (8) Manufacturing method according to the above point (7), wherein the insulation layer of the circuit layer is a single Layer which consists of the same polymer or a laminate structure which has a base insulating layer on the metal carrier substrate side and an adhesive layer for adhering to the semiconductor element.
• (9) Manufacturing method according to the above point (1), wherein a wafer substrate which is the substrate of the Wafer-state semiconductor element with a contact hole is provided, which penetrates the substrate in its thickness direction, and the electrode of the semiconductor element via the contact hole be electrically connected to the back of the wafer substrate can; and wherein the circuit layer on one of the two sides of the wafer substrate and one end of the contact hole and the lead portion of the circuit layer are connected together.

Brief description of the drawings

1 Fig. 12 shows schematic diagrams of the manner in which a circuit layer is formed, step by step, to explain the manufacturing method of the present invention. If necessary, hatching was used to distinguish between different areas (the same applies to other drawings).

2 shows various internal structures and terminal structures in a circuit layer formed by the present invention.

3 FIG. 12 shows schematic diagrams of an exemplary internal structure of a circuit layer in more detail. FIG.

4 shows the processing methods in an embodiment of the present invention.

5 Fig. 10 shows the processing methods in another embodiment of the present invention.

6 shows the processing methods in still another embodiment of the present invention.

7 shows an exemplary structure wherein the conductive layer in the circuit layer comprises multiple layers.

The numerals used in these drawings mean the following: 1 = Metal carrier substrate; 2 = Circuit layer; 21 = Connecting conductor part; 22 = External connection conductor part; 5 = Semiconductor elements in the wafer state; 4 = Semiconductor device.

Detailed description the invention

in the Following is the manufacturing process of the present invention with reference to specific examples.

The terms used here that are upwards or downwards downwards, such as "top" and "bottom", serve only to explain the positional relationship between Layers and are not to be understood as limited they are the actual vertical position of a circuit layer or a semiconductor device.

1 Figure 3 shows schematically how a product is formed, over the respective steps in the manufacturing process of the present invention. The illustrated layer structures and connection patterns in the circuit layers are simplified for the purpose of explanation and will be described in detail below.

First, the manufacturing process includes, as in 1 (a) described a step in which a circuit layer 2 on a metal carrier substrate 1 is formed to obtain a laminated structure, so that the circuit layer of the substrate 1 can be deducted. The circuit layer 2 has a connecting conductor part 21 on, attached to an electrode 31 a semiconductor element 3 can be connected, which forms the object of the connection. The connection conductor part 21 is on the surface of the surface on the side of the metal support substrate 1 opposite, exposed in such a way that the lead portion to the electrode 31 of the semiconductor element 3 can be connected. In the actual manufacturing steps, the area on which the connecting conductor part 21 is exposed, further covered with a release layer, wherein the release layer can be removed before connecting the lead portion to the semiconductor element.

By doing you get circuit layers through these independent steps It is possible, with low costs and in large quantities only those of acceptable quality to connect to elements in the wafer state.

In 1 (a) are the connecting conductor part 21 , the electrode 31 and the like are shown as protruding more than in actual cases to clearly indicate their positions. In 1 only a single element is shown in enlarged view. In actual settings, however, several elements are arranged in matrix form on a wafer-scale substrate.

One Gold Stud Bump, Underbump Metallization (UBM) and the like are formed in the electrodes of the element. examples for the UBM are Ni / Au layers, which are formed by electroless plating Ni is on the primer side; the same applies in the following, d. H. the primer side of the lamination becomes first Ti / Cu layers, Ti / W / Cu layers and Ti / Ni / Cu layers, which are formed by sputtering, and the like.

Next, the manufacturing method includes a step of using the above-described circuit layer 2 during lamination to the wafer-state semiconductor element 3 is laminated and the connecting conductor part 21 the circuit layer 2 and the electrode 31 of the element 3 be connected with each other, as in 1 (b) is shown.

In 1 (b) are the protruding parts of the lead wire part 21 and the electrode 31 each omitted. In the actual step become the semiconductor element 3 and the circuit layer 2 brought by pressing in a solid gapless bonding.

Furthermore, the manufacturing method includes a step of peeling off the metal support substrate by peeling off the circuit layer, as in FIG 1 (C) is shown. This step provides a semiconductor device 4 in which the semiconductor element 3 and the circuit layer 2 on each other la be miniert.

In at this stage, the semiconductor device is in wafer form; Semiconductor devices in the form of individual chips are going through Get separated. The circuit layer with the separated Metal support substrate may prior to separation of a processing be subjected, such as attaching a solder ball.

According to the Manufacturing method of the present invention will be the first described above Problem solved as it is described below.

The Manufacturing method of the present invention can be used as a method be described in which a redistribution layer, the previously as a circuit layer separately from a semiconductor element has been applied to an element in a wafer state, such as a semiconductor wafer, is laminated to obtain a semiconductor device.

A large number of semiconductor devices with large Areas comprising a large number of wafers can, can easily through roll-to-roll production produced by making circuit layers separately, and therefore the manufacturing cost is even lower than if one Redistribution layer formed directly on each semiconductor wafer becomes.

Furthermore gives a metal support substrate that for a Circuit layer is provided in such a way that the circuit layer can be removed, the circuit layer sufficient rigidity, so that the handling increases until the circuit layer is laminated on a semiconductor wafer becomes, which thus contributes to the reduction of manufacturing costs.

The Manufacturing method of the present invention allows it to select only proper circuit layers to to connect them to the element in the wafer state, making an unnecessary Disposal of flawless elements is avoided.

According to the Moreover, the production method of the present invention becomes also solved the second problem described above, like it is described below.

If For example, the lead portion of a circuit layer with a surface having a protruding connection, like one end of a contact hole, from the two surfaces of a semiconductor wafer, presses a metal carrier substrate from behind with sufficient rigidity against the whole Surface of the circuit layer. By this pressing creates sufficient pressure just below the lead portion the circuit layer, and the insulating layer around the lead portion around (in particular, the adhesive layer (described below)) fills the differences in the heights of the protruding parts in the Connecting part and comes into close contact with the wafer surface, with no gap in the interface between the circuit layer and the semiconductor wafer is formed.

As As mentioned herein, a semiconductor device may be any one Be a device that laminating and connecting a Circuit layer allows; Examples of this are conventionally known elements, such as those with simple structure, such as a single light-emitting element, Fields that comprise a collection of such elements organic semiconductor element, a chip card, a processor with various integrated working circuits, a memory, a Photosensor and an image sensor and a multi-chip module, MEMS (microelectromechanical systems; Devices in which machine components, sensors, Actuators, electronic circuits and the like on one Substrate are integrated) and the like.

The Wafer substrate on which a semiconductor element is to be formed, may be any substrate for semiconductor elements; Examples thereof are a semiconductor crystal substrate such as silicon, and an insulating crystal substrate, glass substrate, organic compound substrate and the like. Of these substrates, silicon crystal substrates (silicon wafers) are the most versatile.

Of the As used herein, "semiconductor element in a wafer state" not just multiple semiconductor elements in the form of a matrix on one Wafer substrate (before singulation), but also those produced by passing multiple elements on a wafer substrate Quality control checks, the substrate once in individual chips and then only those non-defects Chips on a plate with the same shape as the wafer substrate rearranges. In the following description, a "semiconductor element in a wafer state "also referred to as" wafer state element ".

If laminated on a semiconductor element and connected thereto becomes, a circuit layer acts as a redistribution layer and provides the connection to an external conductor.

Publicly known methods may be used to interconnect the electrode of the element and the lead portion of the circuit layer; Examples are Au Au Bon Au Stud Bump solder bonding, solder bump bonding, Ag paste bonding, and ACF (anisotropic conductive film) or NCF (non-conductive film) bonding. To meet a requirement for fine pitches, Au Stud Bump solder bonding is suitably used. When a gap arises between the device and the terminal layer due to a bump height and the like, an underfill material or the like may be filled.

in the Case of a structure in which a contact hole forming a wafer substrate penetrates in its thickness direction, present in the substrate and an electrode of a semiconductor element via the Contact hole connected to the back of the wafer substrate Can be a circuit layer on the back of the wafer substrate, and the lead portion the circuit layer can be connected to the terminal of the contact hole become. In this case too, the circuit layers can can not be used to the electrode of the element and the contact hole on the back side of the wafer substrate but on the element side connect to each other, and the circuit layer can both laminated on the back as well as on the element side become.

The Arrangement pattern of individual circuit layers, before the Singulation in the circuit layers are included be any of the element field patterns in the wafer-like element correspond, and allow the connection of individual Elements and circuit layers.

at the outer peripheral shape of the circuit layer as a whole before singling it can be the same as at the wafer substrate or a corresponding mold, a mold with still larger area containing a variety of Wafer substrates (plain plates, tapes unrolled from a roll and the like) may have the same shape as the element assembling area in each wafer substrate or a corresponding shape and the like act.

Supplementary Elements for placing the circuit layer before singulation and the wafer-like member and means for improving the handleability can be added if necessary.

Although the inner structure and the conductor connection structure of a circuit layer are not particularly limited, a suitable basic structure is one in which, as in 1 (a) shown, a connecting conductor part 21 for connection to an electrode of an element on one side of an insulating layer, an external lead part for connection to an external conductor (a contact surface of an external circuit on which the semiconductor device is to be mounted and the like) on the other side, and these conductor parts via the conductive layer, which is located in the insulating layer, are interconnected.

Other examples besides this typical example structure are a structure in which special leads parts 21a and 21b interconnected ( 2 (a) ), a structure in which a single lead portion is connected to a plurality of lead portions for the external terminal (not shown), a structure in which special lead portions 21a and 21b in the layer are interconnected and not connected to an external lead portion on the bottom of the circuit layer ( 2 B) ), and the same; The pattern of the connection structure can be freely varied and combined depending on the purpose.

The circuit in the circuit layer (a conductive layer extending laterally in the circuit layer) may be a single layer as shown in FIGS 1 and 2 is shown, or a multiple layer, as in 7 is shown, act.

3 Fig. 10 is a schematic diagram showing further details of the internal structure of a circuit layer.

In the in 3 (a) The embodiment shown is a conductive layer 23 with a defined connection pattern in an insulating layer 20 , wherein the tip of a conductor track (metal column) 24 that differs from the conductive layer 23 extends to the element side, a connecting conductor part 21 forms while the top of a trace (metal column) 25 , in turn, from the track 23 extending to the metal carrier substrate side, an external lead portion 22 forms. In this embodiment, a metal layer for a particularly preferred electrical connection and an increased corrosion resistance is formed on the tip of each conductive layer.

In the in 3 (b) In the embodiment shown, there is a conductive layer 26 on the element side and a conductive layer 27 on the metal carrier substrate side in an insulating layer 20 and are divided vertically into two levels. The conductive layer 26 on the element side is embedded in the insulating layer (in the case shown with the adhesive layer 20b covered). In the embodiment shown, the conductive layer abuts 27 on the metal carrier substrate side to a release layer 5 , Thus, the conductive layers 26 and 27 through a conductor track 28 which is in a defined position therebetween, connected to each other. On the upper surface of the adhesive layer 20b there is an opening in a defined position into which the conductive layer 26 exposed; the exposed part in the opening forms a connecting conductor part 21 for connection to the element. Meanwhile, in the illustrated embodiment, the lower surface of the conductive layer 27 on the metal carrier substrate side completely exposed to the lower surface of the insulating layer; an opening (through hole h) is at a defined position in the lower surface of a metal support substrate 1 formed, the separation layer 5 was removed, leaving the bottom surface of the conductive layer 27 is exposed, and the exposed part in the opening forms an external connection conductor part 22 , The exposed part in each opening may be a part in which the conductive layer is simply exposed; however, in the illustrated embodiment, a metal layer for a particularly preferred electrical connection and increased corrosion resistance is on the surface of each exposed part.

The The metal layer described above is preferably by plating educated; suitable materials for the metal layer are individual metals, such as copper, gold, silver, platinum, lead, tin, Nickel, cobalt, indium, rhodium, chromium, tungsten and ruthenium, as well Alloys consisting of two or more thereof and the like. The preferred materials include gold, tin, nickel and the like; to the preferred embodiments of the metal layer belong to a double layer structure with a lower layer of Ni and a surface layer of Au and the like.

As in the 3 (a) and (b), there is an opening (through hole h) for the metal support substrate at a position corresponding to the external lead portion 22 corresponds, wherein the tip of the external lead part 22 from the lower surface of the insulating layer 20a can stand out.

At the insulation layer 20 the circuit layer may be a single layer made of the same polymer, and it may also be a lamination structure comprising a base insulation layer 20a on the metal carrier substrate side and an adhesive layer 20b for gluing on an element, as in the 3 (a) and (b) is shown. When the electrode of the element and the lead portion of the circuit substrate are combined with each other in their connection with sufficient mechanical strength, the adhesive layer may be omitted, and the insulating layer 20 may be a publicly known isolation layer without adhesive property.

Examples of suitable materials for base insulating layers include publicly known synthetic resins such as polyimide resin, acrylic resin, polyether nitrile resin, polyethersulfone resin, epoxy resin, polyethylene terephthalate resin, polyethylene naphthalate resin and polyvinyl chloride resin, composites of these synthetic fiber mats, glass mats, glass nonwoven fabrics, microparticles such as TiO ₂ , SiO ₂ , ZrO ₂ , minerals and clay, and the like. In particular, polyimide resin, epoxy resin and glass mat epoxy resin are preferred because a thinner flexible insulation layer having higher mechanical strength and electrical properties (insulation property and the like) is obtained after the metal support layer is peeled off and separated.

The Thickness of the base insulating layer is preferably 3 up to 50 μm.

preferred Materials for the adhesive layer include thermoplastic Resins, such as polysulfone, polyethersulfone, polyhydantoin, polyetherimide, Polyester, polyimidesiloxane and siloxane-modified polyamide-imide, Epoxy resins, acrylic resins, silicone resins, polyimide resins and the like; These can also be used in misery.

To the suitable epoxy resins include epoxy resins, those with a thermoplastic resin, rubber, elastomer and the like mixed, silica hybrids, epoxy resins dispersed therein Nanoparticles and the like.

Examples suitable acrylics include epoxy acrylate, Urethane acrylate, silicone acrylate and the like.

The Thickness of the adhesive layer is preferably 1 to 100 μm.

When A method of forming a circuit layer on a metal carrier substrate may conventionally known methods for Production of circuit substrates or interposers, such as the semi-additive Method and the subtractive method can be used.

By doing a circuit layer on a metal carrier substrate forms, the dimensional stability during manufacture increases, and the handling of thin circuit layers will be improved.

When a conductive layer and a wiring are formed by the semi-additive method in a circuit layer, it is preferable, as in FIG 4 shown a vaccine layer 23a (Metal thin film) formed by sputtering in advance, so that a metal material on the well conductive layer 23 and the wall surface of the part, which is the conductor track 25 should form, can separate. Examples of suitable materials for such a seed layer are single metals such as copper, gold, silver, platinum, lead, tin, nickel, cobalt, indium, rhodium, chromium, tungsten and ruthenium, alloys consisting of two or more species thereof, and the same.

Examples of materials for in 3 The conductive layer and trace shown are single metals selected from copper, gold, silver, platinum, lead, tin, nickel, cobalt, indium, rhodium, chromium, tungsten, ruthenium, and the like, and alloys comprising one or more thereof (e.g., solders, nickel-tin, gold-cobalt and the like). In particular, it is preferred to use metals which enable galvanization or electroless plating. Copper is preferred because of its excellent suitability for easily forming a circuit pattern of the conductive layer and its electrical properties.

The thickness of the conductive layer 23 may suitably be selected, inter alia, in the range of 1 to 50 microns. The tracks 24 and 25 preferably have a cylindrical shape with a diameter of 5 to 500 .mu.m, preferably 5 to 300 .mu.m.

To the preferred materials for the metal support substrate belong among other things copper, copper alloys, which in based primarily on copper, nickel, nickel alloys, the based primarily on nickel, alloys primarily based on Nickel and iron are based, stainless steel and the like.

Around the difference in linear expansion coefficient over to minimize the semiconductor wafer, an alloy is preferably used, which is based primarily on nickel and iron (eg Alloy 42).

The Thickness of the metal carrier substrate is variable and depends from the stiffness of the material and is preferably about 10 microns to 200 microns, more preferably about 20 μm to 80 μm.

If the thickness of the metal carrier substrate is less than 10 μm is likely to occur wrinkles and wrinkles in the metal support substrate on, which in turn reduces the handling in the rolling process. If the thickness of the metal carrier substrate larger than 200 μm, the winding diameter decreases due to its Stiffness, which in turn hinders handling in the rolling process and the processing by etching disturbs.

Around the smoother detachment of the metal carrier substrate and to facilitate the circuit layer, a structure is preferable where there is a separation layer between them. Preferably the separating layer is formed so that the separating layer is easy detach from the circuit layer and yourself very difficult to detach from the metal support substrate leaves and that the release layer together with the metal support substrate can be removed from the circuit layer.

Suitable materials for the release layer include organic substances (silicone resin, polyimide and the like) and inorganic substances (metals, metal oxides, inorganic oxides and the like). Examples of the inorganic substances are Ag, Ti, W, Ni, SiO ₂ and the like.

In Considering the steps for making a circuit layer and the high temperature conditions during bonding the circuit layer with a semiconductor wafer are polyimide and the more preferred above inorganic substances, because silicone resin can deteriorate.

If the separation layer is formed as a polyimide layer is its thickness is preferably 0.1 to 10 μm, with 0.1 to 5 μm are further preferred in order to prevent the entire circuit layer bends.

If the release layer as a layer consisting of the above inorganic Substances consists, is formed, is their thickness preferably 1 to 100 nm, with 1 to 50 nm being more preferred, to prevent the entire circuit layer from bending.

If the release layer is a polyimide layer are suitable methods to form the layer, a method in which a solution is applied, a method in which the layer by electrochemical Deposition or chemical vapor deposition (CVD) is deposited, a method in which a separately formed polyimide film is laminated will, and the like. If the release layer is a layer that of an inorganic substance such as a metal, metal oxide or inorganic oxide, are suitable methods of formation the layer electroplating, vacuum evaporation, cathode sputtering and the same.

Examples

The manufacturing method of the present invention will be described below more specifically and in detail with reference to actual production examples. For all circuit layers in the 4 to 7 , in the following explanation Reference is made, only a single lead portion and a single this corresponding external lead portion on the back of the latter are increased.

example 1

A Separating layer, which consists of polyimide, was on one of Alloy 42 existing metal carrier substrate formed, a circuit layer was formed on it, and then everything was done with a semiconductor wafer connected. A metallization with a precious metal for a contact point on an end face of an external lead portion was carried out; an opening was made by the Bottom forth made in the metal support substrate, such that an end face of the external lead portion is exposed, and the end surface was metallized.

Formation of a separation layer

As in 4 (a) was shown, a film of Alloy 42 with a thickness of 50 microns as a metal support substrate 1 A polyamic acid solution (prepared by a reaction of pyromellitic dianhydride and 2,2'-dimethyl-4,4'-diaminobiphenyl) was applied thereto and dried and imitated by heating with a polyimide release layer over the entire surface 5 was formed with a thickness of 2 microns.

Formation of a basic insulation layer

As in 4 (b) a polyimide layer (base insulation layer) has been shown 20a formed using a photosensitive polyamic acid (prepared by a reaction of 3,3 ', 4,4'-biphenyltetracarboxylic dianhydride, 4,4'-diaminodiphenyl ether and paraphenylenediamine containing a photosensitizer). At the position where an external lead part should be formed, an opening h1 was made. The release layer was exposed on the bottom of the opening. The base insulation layer had a thickness of 5 μm, and the opening was circular and had a diameter of 100 μm.

Formation of a seed layer, a lower trace and a conductive layer As in 4 (c) A sputtering was performed with chromium and then copper with a seed layer 23a was formed (thickness of the chromium layer 20 nm, thickness of the copper layer 100 nm), and by electrolytic coppering became a conductive layer 23 with a defined circuit pattern and a trace 25 educated. Subsequently, the part of the seed layer where the conductive layer 23 was missing, removed. Since the copper layer of the seed layer was combined with the copper of the wiring and the conductive layer, the seed layer is 23a in 4 (c) represented as a single layer, which consists of chrome. The same goes for the 5 to 7 ,

Formation of an opening in the metal carrier substrate

As in 4 (d) 1, an opening h2 having a diameter of 300 μm was formed from the lower surface of the metal support substrate 1 on a position that the trace 25 formed, wherein an aqueous solution of ferrous chloride is used to form the opening h2, thereby forming a release layer (polyimide layer) 5 to expose in the opening. Furthermore, the separation layer 5 by etching with an alkaline treatment liquid exposing the seed layer (chromium layer) 23a and the chrome layer was etched using a mixed aqueous solution of potassium hexacyanoferrate (III) and sodium hydroxide to expose the copper layer.

Formation of the upper trace

As in 4 (e) shown was the top of the conductive layer 23 covered with a metallization resist r1 (except for the part where a trace should be formed), the underside of the metal carrier substrate 1 and the opening h2 were completely covered with a resist r2, and a wiring 24 with a diameter of 80 microns and a height of 15 microns was formed by electrolytic copper plating.

Formation of an adhesive layer

As in 4 (f) As shown, the metallization resisters r1 and r2 were removed, and an adhesive layer 20b , which mainly comprises epoxide and polyimide, was formed in such a manner that the exposed conductive layer 23 and the track 24 were embedded, and the adhesive layer was etched by means of an alkaline solution in such a manner that the upper end surface of the conductor track 24 was exposed as a connector on the top of the adhesive layer.

Formation of a metal layer in the connection part

As in 4 (g) 2, a nickel layer (with a thickness of 2 μm) and a gold layer (with a thickness of 0.5 μm) were successively formed by placing the top side of the conductor track 24 and the bottom in the opening of the metal carrier substrate (lower end surface of the wiring 25 ) galvanized.

Connection to semiconductor wafers

The thus-obtained circuit layer (the metal support substrate detachably attached) became after connected to a semiconductor wafer according to the following method.

Of the Semiconductor wafer contained 240 elements, each element had 240 circular ones Electrode contact surfaces with a diameter of 80 microns on, with on each contact surface a gold stud bump with a diameter of 60 microns was formed.

The thus-obtained circuit layers were aligned and bonded in a vacuum of 3 Pa at a temperature of 300 ° C under a pressure of 1.5 g / bump using an alignment and bonding apparatus (manufactured by EV Group) and thereafter became the glue layer 2 Hardened at 180 ° C for hours. Subsequently, the metal support substrate became at the interface between the release layer 5 and the base insulation layer 20a subtracted, and the release layer 5 and the metal support substrate were removed to obtain a semiconductor device.

Example 2

In This example was a metallization with a precious metal for a contact point on an end face of an external lead portion carried out. In the metal carrier substrate was no opening made; an opening became manufactured at a defined position on a release layer, and a noble metal layer for the contact point was formed, and then a trace was formed thereon.

Formation of a separation layer

As in 5 (a) has been shown, a metal carrier substrate 1 , which was a film of the same Alloy 42 used, and on it was a release layer 5 of polyimide having a thickness of 2 μm as formed in Example 1, using the same photosensitive polyamic acid solution as used in Example 1. An opening h3 was in a defined position where an external lead portion of the separation layer should be formed. The opening was circular and had a diameter of 100 μm.

Formation of a basic insulation layer and forming a metal layer for the contact point

As in 5 (b) was shown, a polyimide layer having an opening h4, which corresponded to the opening h3 (basic insulation layer 20a ), using the same photosensitive polyamic acid as used in Example 1. The basic insulation layer 20a had a thickness of 5 μm, and the opening was circular and had a diameter of 100 μm.

Subsequently, a gold layer 212 and a nickel layer 211 formed successively by galvanizing the top of the metal support substrate exposed in the openings h4 and h3.

Formation of a seed layer, a lower trace and a conductive layer As in 5 (c) A sputtering was performed with chromium and then copper with a seed layer 23a was formed (thickness of the chromium layer 20 nm, thickness of the copper layer 100 nm), and by electrolytic coppering became a conductive layer 23 with a defined circuit pattern and a trace 25 educated. Subsequently, the part of the seed layer where the conductive layer 23 was missing, removed.

Formation of the upper trace

As in 5 (d) shown was the top of the conductive layer 23 covered with a metallization resist r1 (except for the part where a trace should be formed) and the bottom of the metal carrier substrate 1 was completely covered with a r2 resist. A trace 24 with a diameter of 80 microns and a height of 15 microns was formed by electrolytic copper plating.

Formation of an adhesive layer

As in 5 (e) As shown in Figure 1, the metallization resisters r1 and r2 were removed using the same materials and methods as in Example 1 above, an adhesive layer 20b was formed in such a manner that the exposed conductive layer 23 and the track 24 were embedded, and the adhesive layer was etched in such a way that the upper end surface of the trace 24 was exposed as a connector on the top of the adhesive layer.

Formation of a metal layer on the end face of the lead wire part

As in 5 (f) 2, a nickel layer (having a thickness of 2 μm) and a gold layer (having a thickness of 0.5 μm) were successively plated by plating on the upper end surface of the wiring 24 educated.

Here in Example 2, as in 5 (a) is shown, first formed an opening in a release layer; therefore, as compared to Example 1, it was not necessary to form an opening in the metal substrate for nickel plating and gilding of the terminal as shown in FIG 4 (d) is shown.

Connection to semiconductor wafers

The circuit layer thus obtained (Me support substrate) was attached to the semiconductor wafer by the same methods as in Example 1, and the release layer and the metal support substrate were removed to obtain a semiconductor device.

Example 3

In This example was a metal as a material for a Separating layer used.

Formation of a separation layer

As in 6 (a) was shown was a release layer 5 (with a thickness of 25 nm), which consisted of Ag, by vacuum evaporation on a metal support substrate 1 , which was a film of the same Alloy 42 as in Example 1 formed.

Formation of a basic insulation layer and forming a metal layer for the contact point

As in 6 (b) has been shown, a polyimide layer having an opening h5 (basic insulation layer 20a ) using the same photosensitive polyamic acid as used in Example 1. The basic insulation layer 20a had a thickness of 5 μm, and the opening was circular and had a diameter of 100 μm.

A gold layer 212 and a nickel layer 211 were successively formed by plating on the Ag surface exposed in the opening.

Formation of a seed layer, a lower trace and a conductive layer As in 6 (c) A sputtering was performed with chromium and then copper with a seed layer 23a was formed (thickness of the chromium layer 20 nm, thickness of the copper layer 100 nm); electrolytic copper plating became a conductive layer 23 with a defined circuit pattern and a trace 25 educated. Subsequently, the part of the seed layer where the conductive layer 23 was missing, removed.

As in 6 (d) shown was the top of the conductive layer 23 covered with a metallization resist r1 (except for the part where a trace should be formed) and the bottom of the metal carrier substrate 1 was completely covered with a r2 resist. A trace 24 with a diameter of 80 microns and a height of 15 microns was formed by electrolytic copper plating.

Formation of an adhesive layer

As in 6 (e) As shown in Figure 1, the metallization resisters r1 and r2 were removed using the same materials and methods as in Example 1 above, an adhesive layer 20b was formed in such a manner that the exposed conductive layer 23 and the track 24 were embedded, and the adhesive layer was etched in such a way that the upper end surface of the trace 24 was exposed as a connector on the top of the adhesive layer.

Formation of a metal layer on the end face of the lead wire part

As in 6 (f) Shown was a nickel layer 211 (with a thickness of 2 microns) and a gold layer 212 (with a thickness of 0.5 microns) successively by electroplating on the upper end surface of the conductor 24 educated.

Here in Example 3, as in 6 (b) shown, a gilding and nickeling enabled by electric current through the separation layer (Ag layer) was supplied; therefore, as compared to Example 1, it was not necessary to form an opening in the metal substrate for nickel plating and gilding of the terminal as shown in FIG 4 (d) is shown.

Connection to semiconductor wafers

The thus obtained circuit layer (the metal support substrate peelable) was prepared by the same method as in Example 1 connected to the semiconductor wafer, and the separation layer and the metal support substrate were removed using a semiconductor device was obtained.

Example 4

In this example, an inorganic oxide (SiO ₂ ) was used as a material for a release layer.

Formation of a separation layer

As in 4 (a) was shown was a release layer 5 made of SiO ₂ (with a thickness of 7 nm) by sputtering on a metal support substrate 1 , which was a film of the same Alloy 42 as in Example 1 formed.

The methods, materials and the like described in the subsequent steps of "forming a base insulating layer and forming a metal layer for the contact point", "forming a seed layer, a lower wiring and a conductive layer", "forming an adhesive layer", "forming a metal layer the terminal area of the lead portion "and" terminal to semiconductor wafer "were used were exactly the same as in Bei game 1.

In this example, in the 4 (d) ₂ , the SiO ₂ layer which was the separation layer, simultaneously with the etching of the metal support substrate 1 removed to make an opening from the bottom of the metal support substrate, since the layer was very thin.

Example 5

In this example, as in 7 As shown, a plurality of conductive layers are formed as a conductive layer in a circuit layer.

In the 7 The embodiment shown represents the same structure as obtained in Example 1 above, except that base insulating layers and conductive layers are laminated repeatedly.

In this example, the processing in relation to the methods of "forming the release layer on the metal support substrate" in FIG 4 (a) to "forming an opening in the metal carrier substrate" in FIG 4 (d) in the same manner as in Example 1. Through this processing, as in 7 shown a metal carrier substrate 1 , a release layer 5 , a first basic insulation layer 201 , a first track 251 and a first conductive layer 231 educated. A seed layer was also prepared in the same manner as in Example 1.

Next, in this example, the same processing as in 4 (b) shown again instead of going to step in 4 (e) progressing to a first conductive layer 231 in a second base insulation layer 202 to embed and produce in a defined position in the same an opening. As in 4 (c) shown was a second trace 252 and a second conductive layer 232 educated. The same processing as described above was again carried out to form a third basic insulation layer 203 , a third track 253 and a third conductive layer 233 to build.

Subsequently, the steps of the 4 (e) to (f) performed to an upper trace 24 and an adhesive layer 20b to form and around a metal layer on a connection part 21 to build.

Due to the processing steps described above, the in 7 obtained circuit layer.

Example 6

In In this example, it was confirmed that a circuit layer seamlessly to a semiconductor wafer with a contact hole, where the terminal protrudes from the wafer surface, can be bonded.

Semiconductor wafer

One Silicon semiconductor wafers having a thickness of 400 μm and a diameter of 15.2 cm was made, and through holes with a diameter of 100 microns were formed therein. The through holes were printed by printing Way filled with a copper paste, that the connecting parts increased by about 5 microns, and the wafer was burned, with a protruding connector was created.

circuit layer

A Circuit layer with a peelable metal carrier substrate was obtained in the same manner as in Example 1.

connection

The Circuit layer and the semiconductor wafer were by pressing under the same conditions as in Example 1 bonded together, which is a Semiconductor device resulted.

Between the semiconductor wafer and the circuit layer thus obtained absolutely no gap exists, and the connection between the electrodes of all elements and the lead portion of the circuit layer was good.

Industrial Applicability

According to the Manufacturing method of the present invention may be a redistribution layer for a lower cost semiconductor device and the disposal of semiconductor elements of more acceptable Quality because of an unacceptable quality of Redistribution layer is avoidable. The manufacturing process The present invention also enables the manufacture a seamless semiconductor device when one end protrudes a contact hole.

This application is based on a in Japanese Patent Application No. 2008-316076 , which is hereby expressly and fully incorporated by reference.

QUOTES INCLUDE IN THE DESCRIPTION

This list The documents listed by the applicant have been automated generated and is solely for better information recorded by the reader. The list is not part of the German Patent or utility model application. The DPMA takes over no liability for any errors or omissions.

Cited patent literature

• JP 2000-243754 A [0004]
• - JP 2008-316076 [0127]

Claims (9)

Method for producing a semiconductor device with a structure in which a semiconductor element and a circuit layer laminated together, the method comprising the steps of: Form a circuit layer having a lead portion connected to a Electrode of a semiconductor element can be connected in one such that the circuit layer on a metal carrier substrate can be deducted from the substrate and that the connecting conductor part exposed on the upper surface of the circuit layer; Laminate the circuit layer on the semiconductor element while it is in the wafer state, wherein the lead portion of the circuit layer and the electrode of the semiconductor element are connected together; and Separating the metal carrier substrate from the circuit layer after connecting. Manufacturing method according to claim 1, wherein a separating layer between the metal carrier substrate and the circuit layer, whereby the circuit layer can be deducted from the metal support substrate. Manufacturing method according to claim 2, wherein the release layer is a layer that is formed the release layer is easily peeled off the circuit layer and can not be easily separated from the metal support substrate peel off, leaving the release layer together with the metal carrier substrate removed from the circuit layer can be. Manufacturing method according to claim 2, wherein the separating layer consists of polyimide. Manufacturing method according to claim 2, wherein the separating layer is made of a material consisting of metals, Metal oxides and inorganic oxides is selected. Manufacturing method according to claim 1, wherein the circuit layer as a redistribution layer for the semiconductor element functions. Manufacturing method according to claim 1, wherein the circuit layer comprises an insulation layer; a conductive layer located in the insulating layer; one Terminal conductor part for connection to an electrode of a semiconductor element on a surface of the insulating layer; and one External connection conductor part for connection to an external conductor on the other surface of the insulating layer; and in which the connection conductor part and the external connection conductor part via the conductive layer, which is in the insulation layer is connected to each other. Manufacturing method according to claim 7, wherein the insulating layer of the circuit layer is a single Layer which consists of the same polymer or a laminate structure has a base insulation layer on the metal support substrate side and an adhesive layer for bonding to the semiconductor element. Manufacturing method according to claim 1, wherein a wafer substrate, which is the substrate of the Wafer-state semiconductor element with a contact hole is provided, which penetrates the substrate in its thickness direction, and the electrode of the semiconductor element via the con tact hole electrically connected to the backside of the wafer substrate can be; and wherein the circuit layer is on one of the two Side of the wafer substrate is laminated and one end of the contact hole and the lead portion of the circuit layer interconnected become.