DE102008046188A1 - Chip-printed circuit board-arrangement, has passivation layer arranged next to electrical connecting contact, and wire bonding connection with wire connected with contact surface of board by electrically conductive material - Google Patents

Abstract

The arrangement has a passivation layer (13) arranged next to an electrical connecting contact (12). A wire bonding connection (15) with a bonding wire (16) is provided on the contact of a semiconductor chip (11), where the wire ends at the passivation layer. The bonding wire is connected with a contact surface (18) of a printed circuit board (19) by an electrically conductive material (17) e.g. soldered strut. The passivation layer includes an adherent surface for wire bonding. An intermediate layer (14) is arranged on the passivation layer, and includes an elastic material. An independent claim is also included for a method for manufacturing a chip printed circuit board arrangement.

Description

The The invention relates to a chip circuit board assembly and a method for manufacturing a chip circuit board assembly.

The Development of electronic components and their connection with a parent System like a printed circuit board is shaped by the requirements constantly growing, higher efficiency the electronic components with simultaneous requirement of further miniaturization and cost savings.

A possibility it is this, chips without their own housing directly on a circuit board to arrange and connect directly to each other.

The Problem here is the compensation of the structure widths between the Terminal contacts of the chip and the contact surfaces of the circuit board.

Typical structure widths The terminal contacts of chips are between 60 and 120 microns with falling Tendency with further development of production technology. On the other hand The smallest structure widths are on printed circuit boards, which with reasonable effort can be made in volume at 150-200 microns.

Around to balance the difference between the structure widths becomes added a redistribution layer on the chip in the prior art.

These elevated the cost of assembly and may also have other disadvantages, such as a bending of the chip with temperature change, the result.

The The invention provides a chip circuit board assembly and method ready for making a chip circuit board assembly that meets these requirements satisfy.

The inventive solution particularly advantageous because the connection between the semiconductor chip and PCB no further level (rewiring, leadframe, Substrate), but directly. The bonding wires are flexible and same displacements made by different thermal expansion coefficients of semiconductor chip and circuit board occur, what the reliability of this Chip circuit board assembly elevated.

following Be exemplary embodiments according to the invention with reference to the attached Drawing closer explained.

1 shows in cross section the schematic representation of an embodiment of the chip circuit board assembly according to the invention;

2 shows in plan view a schematic representation of an embodiment of the chip-printed circuit board arrangement for chips with simple terminal contact row;

3 shows in plan view a schematic representation of an embodiment of the chip-printed circuit board arrangement for chips with a double terminal contact row.

1 shows the structure of a chip-printed circuit board assembly with a semiconductor chip 11 , on one side electrical connection contacts 12 having. The connection contacts 12 are of a passivation layer 13 surrounded, which protects the semiconductor chip from mechanical and environmental influences.

On the connection contact 12 is a wire bond connection 15 attached, of which a bonding wire 16 leads away.

On the passivation layer 13 is an intermediate layer 14 arranged. This layer has the task to dampen the placement of the bonding tool and the free end of the bonding wire 16 by means of adhesive force on the intermediate layer 14 to keep. If the passivation layer 13 is designed so that they can take on both tasks, the intermediate layer 14 omitted.

The intermediate layer 14 can be like the passivation layer 13 consist of a photolithographically structured layer on the semiconductor chips 11 is applied. Alternatively, it can consist of a single-sided or double-sided adhesive tape, which in sections in the region of the bonding wire 16 on the passivation layer 13 is applied.

It is also possible to distribute the properties damping and adhesion to two materials: the damping takes over the passivation layer 13 and the adhesion takes over the intermediate layer 14 , or the damping takes over the passivation layer 13 and the adhesion takes over in the area of the bonding wire 16 dripped or printed adhesive material. A third variant is the damping with the intermediate layer 14 to ensure and the liability takes over in the field of bonding wire 16 dripped or printed adhesive material.

With the free end of the bonding wire 16 is any part of the bonding wire 16 outside the connection contact 12 meant.

Opposite the free end of the bond wire tes 16 is the contact surface 18 the circuit board 19 , The distance between bonding wire 16 and contact area 18 is variable in the range of a few microns up to 100 microns and more.

On the contact surface 18 is an electrically conductive material 17 attached, which after approach the bonding wire 16 encloses and after a stabilization step, a firm connection with the bonding wire 16 received. The electrically conductive material 17 may be a fusible link or an electrically conductive adhesive.

As 1 shows are on a connection contact 12 a semiconductor chip 11 a wire bond connection 15 fitted with a wire bonding method, the free end of the bonding wire 16 on the semiconductor chip 11 next to the connection contact 12 ends. When forming this end, the bonding wire must be 16 stick to the ground to pull another piece of bonding wire from the capillary of Drahtbondmaschine, from which the ball for the following Drahtbondanschluss 15 is melted. Furthermore, the bonding wire must 16 be torn off by clamping in the capillary, without the free end of the bonding wire 16 stands out from the ground, which has a passivation layer 13 or an intermediate layer applied thereto 14 can be.

To the structures of the semiconductor chip 11 To guard against mechanical overload during wire bonding and to support the wire bonding process may be prior to applying the wire bonds 15 on the passivation layer 13 an intermediate layer 14 be applied, which absorbs the mechanical stresses and adhesion of the free end of the bonding wire 16 causes. The intermediate layer 14 may be the surface of the semiconductor chip 11 with the exception of the connection contacts 12 completely cover or only in the areas around the terminals 12 be arranged. The intermediate layer 14 is preferably made of an elastic dielectric material having a thickness in the range of 5 to 50 microns. The material may be a suitable polymer or a synthetic resin. This material can be screen printed on the individual semiconductor chip 11 or the wafers containing the semiconductor chips are applied. Alternatively, the intermediate layer 14 consist of an adhesive tape, which on the surface of the semiconductor chip 11 is applied. The tape may be single-sided or double-sided adhesive.

The surface of the passivation layer 13 or the intermediate layer 14 can before wire bonding by a plasma treatment, for. B. with water vapor, activated. Thus, this surface is temporarily liable. By absorbing moisture, this adhesion decreases over time. The activation of the surface for temporarily improved adhesion can alternatively be achieved by contact with a solvent.

Another possibility is to apply to the non-adhesive surface of the passivation layer 13 , the intermediate layer 14 or of the adhesive tape in the region of the bonding wire 16 to apply an additional adhesive. This adhesive is preferably made of a viscous material, which is a part of the bonding wire 16 picks up and fixes. However, the adhesive should preferably not be arranged in the contact area of the bonding capillary.

The intermediate layer 14 and the subsequent Drahtbond connection can be applied to the already isolated semiconductor chip or on the semiconductor chip, if this is still in the wafer composite.

On the circuit board 19 are contact surfaces 18 provided with an electrically conductive material 17 , For example, can be printed with solder paste, for example by screen printing.

After placing the semiconductor chip 11 with a free end of the bonding wire 16 opposite a contact surface 18 the circuit board 19 the solder paste is melted in a reflow process and thus a positive electrical connection 17 between the semiconductor chip 11 with the free end of the bonding wire 16 and circuit board 19 produced. Before the solder paste melts, flux can be added to better contact the solder joints.

Alternatively to the solder paste may be on the contact surfaces 18 the circuit board, a conductive adhesive are applied, for example by screen printing. The conductive adhesive is when applied to the circuit board 19 and when mating with the semiconductor chip 11 pasty and only then hardens in a stabilization step.

This Stabilization step can, depending on the material of the conductive adhesive automatically with Time progress or by a heat treatment done.

For mechanical support, after the stabilization of the positive electrical connection, a creeping material can enter the gap between the semiconductor chip 11 and circuit board 19 are introduced, which after curing the semiconductor chip 11 mechanically on the circuit board 19 fixed (so-called underfill). Additionally or alternatively, the semiconductor chip 11 on the circuit board 19 or the complete circuit board 19 with semiconductor chip 11 be provided with a synthetic resin, which after curing a mechanical protection against the environment represents influences.

In the 2 and 3 For example, it shows how the connection of the terminals 12 in a tight grid on the semiconductor chip 11 are arranged by means of bonding wire connection 15 and bonding wire 16 on the contact surfaces 18 the circuit board takes place when these contact surfaces 18 in a larger grid than the connection contacts 12 are arranged.

2 is an example of semiconductor chips 11 with a number of connection contacts 12 . 3 is an example of semiconductor chips 11 with two rows of connection contacts 12 ,

11

chip

12

connection contact on the chip

13

passivation

14

interlayer

15

Wire bond

16

bonding wire

17

electrical conductive material

18

Contact surface on the circuit board

19

circuit board

Claims (20)

Chip circuit board assembly comprising: - a printed circuit board ( 19 ) with a contact surface ( 18 ); A semiconductor chip ( 11 ) with an electrical connection contact ( 12 ) and a passivation layer ( 13 ) next to the terminal 12 ) is arranged; A wire bond ( 15 ) with bonding wire ( 16 ) on the connection contact ( 12 ) of the semiconductor chip, wherein - the bonding wire ( 16 ) on the passivation layer ( 13 ) of the semiconductor chip ( 11 ) and where - the contact area ( 18 ) of the printed circuit board ( 19 ) opposite the end of the bonding wire ( 16 ) is arranged and - the bonding wire ( 16 ) with the contact surface ( 18 ) of the printed circuit board ( 19 ) via an electrically conductive material ( 17 ) connected is. A chip circuit board assembly according to claim 1, wherein said passivation layer ( 13 ) has an adhesive surface at the time of wire bonding. A chip circuit board assembly according to claim 1, wherein on the passivation layer ( 13 ) an intermediate layer ( 14 ) is arranged. A chip circuit board assembly according to claim 3, wherein the intermediate layer ( 14 ) comprises a dielectric material. A chip circuit board arrangement according to one of claims 3 to 4, wherein the intermediate layer ( 14 ) comprises an elastic material. Chip circuit board arrangement according to one of claims 3 to 5, wherein the intermediate layer ( 14 ) has an adhesive surface at the time of wire bonding. A chip printed circuit board assembly according to any one of claims 3 to 6, wherein the intermediate layer ( 14 ) consists of a one-sided adhesive tape. A chip printed circuit board assembly according to any one of claims 3 to 6, wherein the intermediate layer ( 14 ) consists of a double-sided adhesive tape. Chip circuit board arrangement according to one of claims 3 to 5, wherein the intermediate layer ( 14 ) has a non-adhesive surface and in the region of the bonding wire ( 16 ) an additional adhesive on the intermediate layer ( 14 ) is arranged. A chip printed circuit board assembly according to any one of claims 1 to 9, wherein the electrically conductive material ( 17 ) is a fusible link. A chip printed circuit board assembly according to any one of claims 1 to 9, wherein the electrically conductive material ( 17 ) is a conductive adhesive. A method of manufacturing a chip circuit board assembly, comprising the steps of: - providing a semiconductor chip ( 11 ) with an electrical connection contact ( 12 ) and a passivation layer ( 13 ) on the semiconductor chip ( 11 ) next to the terminal 12 ) is arranged; - making a wire bond connection ( 15 ) on the connection contact ( 12 ) of the semiconductor chip, wherein the open end of the bonding wire ( 16 ) on the passivation layer ( 13 ) of the semiconductor chip ends; Providing a printed circuit board ( 19 ) with a contact surface ( 18 ) and a conductive material applied thereto ( 17 ); - arranging the printed circuit board ( 19 ) opposite the chip ( 11 ) so that the contact surface ( 18 ) of the printed circuit board with the electrically conductive material ( 17 ) over the open end of the bonding wire ( 16 ) and performing a stabilization step, wherein the electrically conductive material ( 17 ) with a part of the bonding wire ( 16 ) enters a firm connection. Method according to claim 12, wherein on the passivation layer ( 13 ) of the semiconductor chip ( 11 ) before making the wire bond Interlayer ( 14 ) is deposited. Method according to claim 12, wherein on the passivation layer ( 13 ) of the semiconductor chip ( 11 ) prior to making the wire bond as an intermediate layer ( 14 ) An adhesive tape is arranged. Method according to one of claims 12 to 14, wherein the surface of the passivation layer ( 13 ) or the intermediate layer ( 14 ) is activated and made adhesive by plasma treatment prior to making the wire bond. Method according to one of claims 12 to 14, wherein the surface of the passivation layer ( 13 ) or the intermediate layer ( 14 ) is rendered adhesive by the action of a solvent prior to making the wire bond. Method according to one of claims 12 to 14, wherein the non-adhesive surface of the passivation layer ( 13 ) or the intermediate layer ( 14 ) prior to making the wire bond in the region of the bonding wire ( 16 ) an additional adhesive is applied. A method according to any one of claims 12 to 17, wherein the stabilizing step comprises heating the electrically conductive material ( 17 ). A method according to claim 18, wherein the stabilizing step comprises melting the electrically conductive material ( 17 ). The method of claim 18, wherein the stabilizing step comprises curing the electrically conductive material ( 17 ).