DE102008045027A1 - Signal processing circuit for use in display device, has logic gate including input connected with modulator output, another input connected with signal input and output connected with signal output - Google Patents

Abstract

The circuit has a signal input (IN1) for supplying a pulse modulated input signal (PM1). A controlled pulse modulator (MOD) has a control input (CIN) and a modulator output (MOT), and produces an intermediate signal at the modulator output as a function of a data word by pulse modulation, where the data word is supplied by a data input (DIN). The pulse modulation is controlled by the input signal. A logic gate (LG1) has an input (21) connected with the modulator output, another input (22) connected with the signal input and an output (23) connected with a signal output (OT). Independent claims are also included for the following: (1) a display device comprising a display processor and a signal processing circuit (2) a method for signal processing.

Description

The The invention relates to a signal processing circuit and a Display device with the signal processing circuit. The invention further relates to a method for signal processing.

In Many applications require certain control signals with relative signal levels, especially for control tasks efficient to code. Such control tasks can z. B. a brightness control in lighting circuits. In this case, such control signals for example, as a binary data words or encoded as pulse modulated signals. In the latter case can continue to be modulated between pulse width modulated signals and pulse density modulated Signals are distinguished.

If a control signal composed of a plurality of control signal components is to be, especially with pulse-modulated signals this first in signal level or binary data words reconverted to be combined in this form. Subsequently, from the combined signal again generates a pulse modulated signal. When converting back can However, inaccuracies occur that are distorted lead combined output signal.

It Object of the invention, a signal processing circuit and to provide a method of signal processing, with which a pulse modulated signal with another signal with improved accuracy and low Effort can be combined. It is also an object of the invention to show a display device with the signal processing circuit.

These Tasks become with the objects the independent one claims solved. Embodiments and developments of the invention are the subject the dependent claims.

In an embodiment For example, a signal processing circuit includes a signal input to feed a pulse modulated input signal, a signal output first link and a controlled pulse modulator. The pulse modulator comprises a control input coupled to the signal input, and a modulator output. The pulse modulator is set up by Pulse modulation an intermediate signal at the modulator output as a function one over a data input can be fed Data words to generate, with the pulse modulation by the input signal (PM1) is controlled. The first gate has a first one Input coupled to the modulator output, a second Input coupled to the signal input and an output which is coupled to the signal output.

Of the Pulse modulator generated as a function of supplied to him on the input side Data word a pulse modulated intermediate signal, wherein the generation the pulse modulated signal also from the pulse modulated input signal depends. In other words a pulse modulation occurs only when the pulse modulated input signal having a respective predetermined level. The pulse modulated intermediate signal will over the second link linked to the pulse modulated input signal so as to be the pulse modulated To produce output signal.

With the described signal processing circuit, it is possible a Combining the pulse modulated input signal with the data word without the pulse modulated input signal into a signal level corresponding To convert signal or data word. This leads to a increased Accuracy in the combination of these signals. Furthermore, it is in conventional circuits, with which such signals are combined, required that the pulse modulated input signal for the reconversion with a clock signal is synchronized while in the described signal processing circuit to such Synchronization can be dispensed with. Furthermore, in conventional Circuits need to be a digital multiplier that the both data signals used as input signals. This is the result Effort for the described signal processing circuit less.

In an embodiment is the pulse modulator is set up to pulse modulation dependent on from a logic state of the input signal. For example the pulse modulator has a delay element or a memory element whose function depends on the logic state of the input signal can be stopped.

In another embodiment the signal processing circuit further comprises a second gate with a first entrance to the feeder a reference clock signal, a second input connected to the signal input is coupled, and an output, wherein the control input of the pulse modulator executed as a clock input is and the pulse modulator for a clocked operation is set up.

The gates are at least partially logical in various embodiments Running gates, so that each link from input signals to a logical link.

By the preferably logical link of the reference clock signal with the pulse modulated input signal generates a clocked control signal which is sent to the clock input the clock-controlled pulse modulator is performed.

In a further embodiment are the second inputs of the first and second gate via a common or a respective delay element, which passes through the Reference clock signal is clock controlled, coupled to the signal input. It can thereby be achieved that the clock edges of the pulse-modulated Input signal with those of the reference clock signal match or synchronized. Regarding the pulse modulated output signal this has the consequence that short pulses in the output signal avoided can be which under certain circumstances not evaluated by a processing unit of the output signal can be.

In an alternative embodiment the signal processing circuit comprises a phase locked loop, English Phase-Locked Loop, PLL, which is established, the reference clock signal in dependence of the pulse modulated input signal. For example a period of the pulse modulated signal is evaluated, wherein the phase locked loop the reference clock signal with a predetermined Frequency multiplier factor from a fundamental frequency of the pulse modulated Derived signal. In other words the reference clock signal becomes dependent on a period duration of the input signal. Also in this case is a synchronization given between pulse-modulated input signal and reference clock signal, which in turn prevents too short pulses in the output signal.

In an embodiment In the signal processing circuit, the pulse modulator comprises a sigma-delta modulator with at least one accumulator, the input side coupled to the data input is, as well as a clock-controlled delay element or memory element. The sigma-delta modulator, which is a sigma-delta modulation of the data word in a known manner, performs its arithmetic operations in clocked operation.

in this connection is in one embodiment the corresponding clock signal by the clocked control signal on Output of the first gate shown. So if, due to the logic state of the pulse modulated input signal no clock edges of the reference clock signal at the clock input of the sigma-delta modulator applied, so for example, a modulation process can be interrupted, so that at the output of the sigma-delta modulator a currently applied logical state is maintained. This changes accordingly Pulse-pause ratio in the pulse-modulated intermediate signal.

alternative For example, a memory function in the sigma-delta modulator dependent on of the input signal. For this purpose, the delay element or memory element can be so interconnected that its output fed back its entrance is when the input signal is a certain level, preferably has a low level. At the other level status of the Input signal, preferably a high level, is the output of the accumulator led to the input of the delay element or memory element. Also in this embodiment becomes a currently applied one at the output of the sigma-delta modulator maintain logical state.

In a further embodiment For example, the pulse modulator has a clock-driven binary counter Generation of a counter word on. Furthermore, a comparison element is provided, the input side with the counter and the data input and output side with the modulator output is coupled. So for example, a logical high signal generated when the binary Data word bigger than that binary counter word of the meter is while a logical low signal is emitted when the binary coded counter signal greater than the corresponding value of the data word is. In other words, the Output of the comparison element a pulse width modulated intermediate signal at. Preferably, this corresponds to a word width of the counter word and a word width of the data word.

In an embodiment is the counter coupled on the input side with the control input designed as a clock input, so that a counting process dependent on the clocked control signal takes place.

In an alternative embodiment points the counter a memory element such as a flip-flop which, like previously for the embodiment of the sigma-delta modulator described, stopped by the input signal in its function can be. For this purpose, the memory element can in turn be connected in this way be that its output is fed back to its input when the input signal has a certain level, preferably a low level. At the each other level state of the input signal, vorzugswei se so a high level, the interconnection is such that a counting function executed in a known manner becomes.

In a further embodiment, the pulse modulator comprises a further modulator output and a further comparison element, the input side with the counter or another Datenein gear and output side is coupled to the other modulator output. In this case, the signal processing circuit has a further logic element with a first input which is coupled to the further modulator output, a second input which is coupled to the signal input and an output which is coupled to a further signal output. At the further data input, a further data word can be supplied, which is to be combined with the pulse-modulated input signal. Thus, respective pulse width modulated output signals based on a combination of the pulse modulated input signal with a respective data word can be generated at the various data outputs.

In the described embodiments the signal processing circuit is at least one of the gates executed as a logic gate, in particular as an AND gate. Preferably can however, all logic gates of the signal processing circuit as And gates are running.

In a further embodiment the signal processing circuit further comprises a first and a second data port for supplying a first and a second control word and a multiplier on the input side with the first and the second data port and the output side is coupled to the data input. Thus, at the data ports respective Tax components are supplied in the form of the first and second control words, which is preferably binary Multiplication result in the data word, which is processed by the pulse modulator becomes. Accordingly, a pulse-shaped input signal with multiple binary Control words are combined.

The Signal processing circuit according to one of the described embodiments For example, to control a backlight in a screen or display, preferably a liquid crystal display be used.

For example has an embodiment a display device having a screen processor set up is, an image signal to control a screen and a to generate pulse modulated luminance signal, a signal processing circuit according to one of the described embodiments. The signal input the signal processing circuit is in this case for supplying the Brightness signal set up. The display device is set up, a lighting of the screen, in particular a backlight, in dependence an output signal at the signal output of the signal processing circuit perform.

For example also lie next to the pulse modulated brightness signal of the display processor further brightness-controlling control words that with the pulse-modulated Brightness signal to be combined. In the signal processing circuit Thus, the brightness signal with a or, according to the respective embodiment, with several binary ones Control words for brightness control combined. The pulse modulated Output signal of the signal processing circuit can for driving a driver circuit for lighting elements be used, such as. B. light emitting diodes or organic light emitting diodes, which light the background of the screen. The real one Image information, on the other hand, is provided by the image signal from the display processor generated.

In an embodiment A method of signal processing becomes a pulse modulated input signal fed. By pulse modulation is a pulse modulated intermediate signal as Function of a data word in clocked operation depending on the clocked control signal generated, wherein the pulse modulation by the input signal is controlled. By linking the input signal with the Intermediate signal becomes a pulse-shaped Output signal generated.

The shortcut The signals are in various embodiments as a logical link, in particular performed as an AND operation.

Consequently the generation of the pulse-modulated intermediate signal takes place both dependent on a clock signal for the clocked operation as well as the pulse modulated input signal, which usually the period in which one modulation takes place over one pure dependence is reduced to the clock signal. However, this reduction corresponds a ratio represented by the pulse modulated input signal. Accordingly can without reverse conversion of the pulse modulated input signal is a combination with a binary data word take place, which reduces the complexity of the method compared to conventional methods.

In an embodiment The method is a clocked control signal by linking the Input signal generated with a reference clock signal. The generating the intermediate signal takes place in dependence on the clocked control signal.

In a further embodiment of the method becomes a counter word when generating the intermediate signal by counting generated by clock edges of the clocked control signal and with the Data word compared. This results in the intermediate signal from the Comparison result.

In an embodiment the method is the generation of the intermediate signal by means of clocked sigma-delta modulation as a function of the input signal.

In further embodiments of the method the previously for the signal processing circuit listed modifications and combinations accomplished become.

The Invention will be described below in several embodiments with reference to the Figures closer explained. Functionally or functionally identical elements carry the same Reference numerals. Insofar as elements or blocks correspond in their function, the description thereof is not repeated in each of the following figures.

It demonstrate:

1 A first embodiment of a signal processing circuit,

2 A second embodiment of a signal processing circuit,

3 A third embodiment of a signal processing circuit,

4 a signal-time diagram of signals within a signal processing circuit,

5 A first embodiment of a pulse modulator with a sigma-delta modulator,

6 A second embodiment of a pulse modulator with a sigma-delta modulator,

7 A fourth embodiment of a signal processing circuit,

8th A fifth embodiment of a signal processing circuit,

9 A sixth embodiment of a signal processing circuit,

10 a seventh embodiment of a signal processing circuit, and

11 an embodiment of a display device.

1 shows an embodiment of a signal processing circuit having a first logic gate LG1 and a controlled pulse modulator MOD. The pulse modulator MOD has a control input CIN, which is connected to a signal input IN1, and a data input DIN, which is connected to a further signal input IN2. A modulator output MOT is with a first input 21 of the first logical gate LG1 coupled, which in turn is designed as an AND gate. A second entrance 22 of the first logic gate LG1 is connected to the signal input IN1. An exit 23 of the first logic gate LG1 is coupled to a signal output OT of the signal processing circuit.

in the Operation of the arrangement is over the signal input IN1, a pulse modulated input signal PM1 supplied. Of the Pulse modulator is set up, pulse modulated by pulse modulation Intermediate signal at the modulator output MOT as a function of the over Data input DIN supplied To generate data words DW in timed operation. The data word DW has in this embodiment a word width of n bits. A modulation of the data word DW takes place controlled by the input signal PM1 and preferably in response to a Clock signal. For example, the modulation process takes place in the pulse modulator MOD only in the periods when the pulse modulated input signal PM1 has a high level. When the pulse modulated signal PM1 has a low level, accordingly finds no modulating processing of the data word in the pulse modulator MOD instead.

For example correspond to the pulse modulated input signal PM1 in pulse modulated Form and the data word DW in binary Each form a relative control value between 0 and 1 respectively 0% and 100%. For the pulse modulated input signal PM1 results in the relative value in a known manner from a temporal relationship between high and low levels, while the relative value in the data word DW corresponding to a binary value of the data word based on a theoretically possible maximum value can. The pulse-modulated output signal also corresponds to a relative one Value calculated purely mathematically, for example from a multiplication the relative values of the pulse modulated input signal PM1 and of the data word DW. Accordingly corresponds to a pulse-pause ratio of pulse modulated output signal with the computationally resulting Value. It should be noted that the pulse modulated output signal in principle can be generated by any type of on / off modulation. For example the output signal can be both a pulse width modulated and a be a pulse density modulated signal.

Since the pulse-modulated input signal PM1 does not first have to be converted into a corresponding analog or digital signal in the described signal processing circuit, but can be further processed directly, the combination of the pulse-modulated input signal PM1 with the data word DW takes place in a simplified manner and with increased accuracy.

2 shows a further embodiment of a signal processing circuit based on the embodiment of 1 based and in addition to the first logic gate LG1 and the clock-controlled pulse modulator MOD has a second logic gate LGX. The second logic gate LGX, which is designed as an AND gate, has a first input 11 which is coupled to a reference clock input RIN and a second input 12 which is coupled to a signal input IN1. An exit 13 of the second logic gate LGX is coupled to the control input CIN of the pulse modulator MOD, which is designed as a clock input.

In the operation of the arrangement of 2 is again fed via the signal input IN1 a pulse modulated input signal PM1, which accordingly at the second inputs 12 . 22 the logic gate LGX, LG1 acts. At the reference clock input RIN a reference clock signal FREF is supplied, which is linked via the first logic gate LGX with the input signal PM1. Thus arises at the exit 13 of the second logic gate LGX a clocked control signal, which is supplied as a clock signal to the pulse modulator MOD. The pulse modulator is set up to generate a pulse-modulated intermediate signal at the modulator output MOT as a function of a data word DW supplied via the data input DIN in clocked operation. The data word DW in this embodiment has a word width of n bits. A modulation of the data word DW takes place as a function of the clocked control signal, which is usually not a continuous clock signal. For example, the modulation process in the pulse modulator MOD takes place only in the time segments with the clock edges of the reference clock signal, in which the pulse-modulated input signal PM1 has a high level. If the pulse-modulated signal PM1 has a low level, accordingly again no modulating processing of the data word takes place in the pulse modulator MOD.

In dependence the clocked control signal thus arises at the modulator output MOT the pulse modulated intermediate signal, which in turn with the pulse modulated Input signal PM1 is logically linked by the first logic gate LG1, so as to generate the pulse modulated output signal at the OT signal output.

3 shows a further embodiment of a signal processing circuit, which substantially the in 2 corresponds to the circuit shown. The pulse modulator MOD in this embodiment comprises a clock-controlled binary counter CTR whose clock input CIN to the output 13 of the second logic gate LGX is coupled. The pulse modulator MOD further comprises a comparison element CMP with a non-inverting input + coupled to the data input DIN and an inverting input - coupled to an output of the counter CTR. On the output side, the comparison element CMP forms the modulator output OT.

During operation of the arrangement, the counter CTR counts in binary form clock edges of the clocked control signal at the output 13 of the second logic gate LGX. Accordingly, in principle every clock edge of the reference clock signal FREF is counted and leads to an increase of the binary counter value. Upon reaching the maximum possible value, which is specified by the word width n, an overflow occurs, so that the counter is reset to zero. The logical combination of the reference clock signal FREF with the input signal PM1 results in a low level of the input signal PM1 interrupting the counting process in the counter CTR. Accordingly, with a stopped counter, that is to say a constant counter word at the inverting input, the comparison element also remains constant the comparison result given a constant data word DW. The pulse-modulated output signal at the signal output OT thus results from the logical combination in the first logic gate LG1 of the constant comparison result and the pulse-modulated input signal PM1. The pulse-pause ratio of the pulse-width-modulated output signal thus again corresponds to the product of the corresponding level value of the pulse-modulated input signal PM1 with the value of the data word DW.

4 shows an exemplary signal-time diagram of signals, for example, in a signal processing circuit according to 3 may occur. The lowest signal shown is a pulse-width-modulated input signal PM1, which represents a pulse-pause ratio or a clock ratio of 0.5. Above the input signal PM1, a constant binary data word DW and a counter word CW are shown at the output of the counter CTR. As can be seen, the counter word CW is increased only during the high levels of the input signal PM1, while it remains constant during the low levels. Above the data word DW and the counterword CW is shown a comparison result CR at the modulator output MOT which has a high level when the data word is greater than the counter word and a low level when the counterword CW is greater than or equal to the data word. Finally, as the uppermost signal, the pulse width modulated output signal PMO is shown, which results from the logical combination of the comparison result CR with the pulse width modulated input signal PM1.

In the illustrated signal-time diagram corresponds to the data word DW a relative value of 0.4. Purely arithmetically results from Multiplication of the data word with the level of the input signal PM1 an output level of 0.5 × 0.4 = 0.2. Accordingly, the output signal PMO based on a period of N clock periods TREF of the reference clock signal FREF while twelve clock periods to a high level, where N = 60. For this pulse-to-pause ratio of 12/60, the calculated value of the output level is obtained again from 0.2.

5 shows an alternative embodiment of a pulse modulator MOD, which is based on the sigma-delta modulation principle. The pulse modulator MOD comprises an accumulator ACC with a first input, which is coupled to supply the data word DW with the data input DIN. At a second input of the accumulator ACC, a feedback signal having a word width n is supplied which corresponds to the word width n of the data word DW. An output of the accumulator ACC is coupled to a delay element VZ1, which comprises a control input coupled to the clock input CIN. On the output side, the delay element VZ1 is coupled to the modulator output MOT and to the second input of the accumulator ACC.

During operation, the accumulator ACC accumulates the data word DW and the feedback signal with the respective word width n, resulting in a summation result having a word width of n + 1. The summation result is delayed by the delay VZ1 clock-dependent, wherein, as previously in 2 described, when used in the signal processing circuit at the clock input the clocked control signal is applied. The summation result is therefore passed on the occurrence of a clock edge at the clock input CIN, and remains constant until the occurrence of the next clock edge. From the delayed summation result with the word width n + 1, the feedback signal is formed with the word width n, wherein a single carry bit is output as a pulse density modulated intermediate signal at the modulator output MOT.

Since the output signal of the delay element VZ1 changes only with the occurrence of clock edges, no forwarding of the summation result of the accumulator ACC can occur during a low level of the input signal PM1, so that a modulation process can be regarded as essentially stopped. Thus, when used in the signal processing circuit according to 1 or 2 as an output signal again a pulse density modulated output signal whose level corresponds mathematically to a multiplication of the data word DW with the input signal PM1.

6 shows an alternative embodiment of a designed as a sigma-delta modulator pulse modulator MOD, which in principle on the in 5 illustrated embodiment. In this case, a switch or multiplexer MUX is additionally provided, which is switchable in response to the input signal PM1 at the control input CIN. The output of the delay element VZ1 is coupled via the multiplexer MUX in a first switch position 0 with its input. In a second switch position 1, the multiplexer MUX couples the output of the accumulator ACC to the input of the delay element VZ1.

Preferably, the multiplexer MUX is controlled at a low level of the input signal PM1 in the first switch position 0, while the second switch position 1 is controlled by a high level of the input signal PM1. In the switch position 0, the output signal remains unchanged in each case. In other words, modulation is stopped in this case. In the switch position 1, the modulation is carried out in a conventional manner. Thus, when used in the signal processing circuit according to 1 as an output signal again a pulse density modulated output signal whose level corresponds mathematically to a multiplication of the data word DW with the input signal PM1.

The sigma-delta modulators off 5 and 6 are presented for reasons of clarity only as single-stage modulators. However, it is also possible to use multistage sigma-delta modulators for the pulse modulator MOD, which are operated as a function of the clocked control signal or of the input signal PM1.

7 shows a further embodiment of a signal processing circuit which substantially on the in 3 illustrated embodiment. In addition, however, a clock-controlled delay VZ2 is provided, whose data input D is coupled to the signal input IN1, while the clock input of the delay element is connected to the reference clock input RIN. The second inputs 12 . 22 the logic gates LGX, LG1 are coupled to a data output Q of the delay element VZ2.

The clock edges or the signal levels of the pulse-modulated input signal PM1 are forwarded by the delay element VZ2 in each case at the occurrence of a clock edge of the reference clock signal FREF, so that the data output Q is a pulse-modulated signal which coincides with the timing edges of the reference clock signal FREF syn is chron. Accordingly, the logic operation in the logic gates LGX, LG1 does not take place directly as a function of the pulse-modulated input signal PM1, but as a function of the time-synchronized pulse-modulated signal. Incidentally, however, the function of the signal processing circuit according to the function of in 3 represented signal processing circuit. Due to the synchronization, for example, so-called race conditions in the circuit can be avoided.

In modification of the in 7 In principle, instead of the pulse modulator MOD with counter CTR and comparison element CMP, a sigma-delta modulator as in FIG 5 shown used.

8th shows a further alternative embodiment of a signal processing circuit, in which in addition to the in 3 a phase-locked loop PLL is provided, which is supplied as input the pulse-modulated input signal PM1. The phase-locked loop PLL accordingly generates at its output the reference clock signal FREF as a function of the pulse-modulated input signal PM1. For example, the phase-locked loop PLL evaluates a period of a pulse-width-modulated signal PM1 in order to generate the reference clock signal FREF at a correspondingly higher frequency. In such an embodiment, it may be necessary for the pulse-modulated input signal PM1 to correspond neither to a level 0, ie a permanent low level, nor to a level 1, ie a permanent high level, since in this case a determination of a clock frequency of the pulse-modulated input signal PM1 is almost impossible. Accordingly, a substitute frequency generator can be provided in the phase locked loop PLL, which is activated in the event that the clock frequency can not be determined from the input signal PM1. Alternatively, in a circuit which generates the pulse-modulated input signal PM1, it is possible to prevent the two critical levels 0% or 100% from being output.

9 shows a further embodiment of a signal processing circuit in which the pulse modulator MOD comprises a further comparison element CMP2. As with the predicate CMP, an inverting input is coupled to an output of the counter CTR. A non-inverting input of the further comparison element CMP2 forms a further data input of the pulse modulator MOD and is coupled to a terminal IN3 for supplying a further data word. An output of the further comparison element CMP2 forms a further modulator output which is connected to a first input 31 a third logic gate LG2 is connected.

A second entrance 32 of the third logic gate LG2 is electrically connected to the signal input IN1. Another signal output OT2 of the signal processing circuit is connected to an output 33 of the third logic gate LG2.

Also in this embodiment the logical gates LGX, LG1, LG2 are shown as AND gates. However, as with the other embodiments, it is readily apparent possible, other logical functions for provide the logic gates LGX, LG1, LG2, in which case further changes in the signal processing circuit with respect to occurring logical Level can be made. The link of the respective signals in the logic gates LGX, LG1, LG2 also by other links, the occur in place of the logic gates LGX, LG1, LG2.

In the illustrated embodiment can in Operation next to the one data word which is supplied at the terminal IN2, also one or more additional data words at port IN3 or at here for reasons of clarity not shown further inputs supplied with comparators with the counter CTR generated counter word be compared. The output signals of the comparators CMP, CMP2 etc. form respective pulse-width-modulated intermediate signals, which via the logical Gate LG1, LG2 and for clarity again not shown further logic gates with the pulse modulated Input signal PM1 logically linked become. Thus, at the outputs the logical gates LG1, LG2, etc., several pulse width modulated Output signals generated.

Different expressed is another pulse-modulated intermediate signal by comparison of the counter word generated with another data word and another pulse-shaped output signal is through linkage of the input signal is generated with the further intermediate signal.

For example can in each case the same pulse-modulated one in an application of a controller Input signal PM1 and several different, individual data words based be placed. So z. B. in a brightness control a Basic brightness over the pulse modulated input signal PM1 be set while for individual Pixels or image areas are supplied with respective data words that the effective Specify brightness at the pixel or in the image area.

10 shows a further embodiment of a signal processing circuit, which substantially on the in 1 or 2 illustrated embodiment is based. In addition, in the signal processing circuit, a multiplier MP and a first and a second data port C1, C2 for supplying a first and a second control word provided. The multiplier MP is coupled on the input side to the data terminals C1, C2 and configured to calculate the data word by binary multiplication of the control words, which in this embodiment have a word width of n and m, respectively. With a full multiplication, the data word DW thus results with a word width of n + m, which is supplied to the pulse modulator MOD at the data input DIN.

With the in 10 It is thus possible to determine the pulse-modulated output signal from a pulse-modulated input signal PM1 and the two control words at the data connections C1, C2. In a further, not shown modification of the signal processing circuit and other data ports for supplying additional control words can be provided, which can be combined with each other by further multipliers.

11 shows an embodiment of a display device with a screen processor DPR, a computing unit CPU, a screen DIS and a lighting control unit LMU, which includes a signal processing circuit according to one of the embodiments described above. A user interface UIN and a light sensor LS are connected to the illumination control unit LMU. The lighting control unit LMU further includes driver outputs DR, are connected to the light-emitting elements LE, which may be embodied for example as light-emitting diodes or organic light-emitting diodes.

in the Operation of the display device are performed by the arithmetic unit CPU Image data is sent to the screen processor DPR. These are from the Screen processor DPR converted into an image signal, which for Activation of the DIS screen is used. Preferably, the screen is DIS as a digitally controllable screen, for example as a liquid crystal screen or as a screen with thin film transistors executed. The image signal thus includes, for example, color information for individual Screen points of the screen DIS, that of a viewer can be perceived which is shown schematically in the figure as a human eye HE is.

In addition will from the screen processor DPR from the image information supplied by the CPU a pulse modulated brightness signal PM1 is generated. It can be a Method with dynamic brightness adjustment, English dynamic luminance scaling, DLS, can be used where the color information of the image signal for the DIS screen be adapted such that one through the Light elements LE formed backlight reduced in intensity can be. this leads to to a lower power consumption of the backlight. Preferably Thus, the image signal is generated with a higher brightness, the pulse modulated brightness signal PM1 a correspondingly reduced Brightness value represents.

About the User interface UIN can be a user of the display device further adjustment of the brightness of the screen DIS respectively adjust the backlight, preferably by the User interface UIN The user-requested brightness as a binary data word DW coded and to the input IN2 of the lighting control unit Supplied to LMU becomes. Furthermore, over the light sensor LS, an ambient brightness are detected and as a corresponding coded signal to the input IN3 of the lighting control unit Supplied to LMU become. For example, the backlight should be brighter appear, the brighter the ambient brightness detected by the light sensor LS is. The signal of the light sensor LS finally becomes a binary data word implemented, which corresponds to a correspondingly required brightness. In the signal processing circuit used by the lighting control unit LMU is included is from the pulse modulated brightness signal PM1 and the user interface UIN and the light sensor LS supplied data words generates a pulse-modulated output signal, which is used for driving a driver unit is used, which corresponding currents or Voltages at driver output DR. The driver unit, which may also be included in the lighting control unit LMU can, is for clarity, however not shown.

The Brightness of the backlight is thus due to low-effort Combination of the pulse modulated brightness signal PM1 with the additional ones Brightness information of the user interface UIN and the light sensor LS. By the possibility the intensity Reducing the backlight can reduce power consumption the display device can be reduced.

This is especially in battery powered devices like Mobile phones or personal digital Wizards for extension a possible Operating time advantageous.

In the present description, several different embodiments of the signal processing circuit have been discussed. This combination options for different embodiments have been shown. However, it is obvious that other possible combinations, which are not explicitly shown, can be carried out, in particular with regard to their use tion in a display device. For example, an individual backlight with a signal processing circuit according to 9 be executed. Further, it is possible to interleave a plurality of signal processing circuits according to the described embodiments to combine a larger number of input signals with each other.

MOD

pulse modulator

LGX, LG1, LG2

combiner

IN1, IN2, IN3

entrance

RIN

Reference clock input

DIN

data input

CIN

control input

MOT

modulator output

OT, OT2

signal output

FREF

Reference clock signal

PM1

pulse-modulated input

DW

data word

CTR

counter

CMP, CMP2

predicate

VZ 1, VZ 2

delay

ACC

accumulator

CPU

computer unit

DPR

display processor

DIS

screen

LE

light element

HE

human eye

LMU

Lighting control unit

U.N.

User interface

LS

light sensor

PLL

Phase-locked loop

CW

counter word

CR

comparison result

PMO

pulse-modulated output

MUX

multiplexer

Claims (15)

Signal processing circuit, comprising - a signal input (IN1) for supplying a pulse modulated input signal (PM1); - a signal output (OT); - A controlled pulse modulator (MOD) with a control input (CIN), which is coupled to the signal input (IN1), and a modulator output (MOT), wherein the pulse modulator (MOD) is established by pulse modulation an intermediate signal at the modulator output (MOT) as Function of a data input (DIN) feedable data word (DW) to generate and wherein the pulse modulation is controlled by the input signal (PM1); and - a first gate (LG1) having a first input ( 21 ) coupled to the modulator output (MOT), a second input ( 22 ), which is coupled to the signal input (IN1), and an output ( 23 ), which is coupled to the signal output (OT). Signal processing circuit according to claim 1, wherein the pulse modulator (MOD) is set up, the pulse modulation dependent on from a logic state of the input signal (PM1). Signal processing circuit according to claim 2, wherein the pulse modulator (MOD) is a delay element or a memory element whose function depends on the logic state of the input signal (PM1) can be stopped. Signal processing circuit according to claim 1, further comprising a second gate (LGX) with a first input (LGX). 11 ) for supplying a reference clock signal (FREF), a second input ( 12 ), which is coupled to the signal input (IN1), and an output ( 13 ), wherein the control input (CIN) of the pulse modulator (MOD) is designed as a clock input and the pulse modulator (MOD) is set up for a clocked operation. Signal processing circuit according to claim 4, wherein the second inputs ( 12 . 22 ) of the first and second logic elements (LGX, LG1) are coupled to the signal input (IN1) via a common or a respective delay element (VZ2) which is clock-controllable via the reference clock signal (FREF). A signal processing circuit according to claim 4, further comprising a phase locked loop (PLL) that is adapted to Reference clock signal (FREF) depending of the pulse modulated input signal (PM1). Signal processing circuit according to one of claims 1 to 6, in which the pulse modulator (MOD) a sigma-delta modulator with at least an accumulator (ACC), the input side with the data input (DIN), and a clock-controlled delay element or memory element (VZ1). Signal processing circuit according to one of claims 1 to 6, in which the pulse modulator (MOD) has a clock-controlled binary counter (CTR) for generating a counter word (CW), and a predicate (CMP), the input side with the counter (CTR) and the data input (DIN) and the output side with the modulator output (MOT) is coupled. Signal processing circuit according to claim 8, wherein the pulse modulator (MOD) comprises a further modulator output and a further comparison element (CMP2), the input side with the Counter (CTR) and another data input (IN3) and the output coupled to the other modulator output, wherein the signal processing circuit, a further gate (LG2) with a first input ( 31 ) coupled to the further modulator output, a second input ( 32 ), which is coupled to the signal input (IN1), and an output ( 33 ) coupled to another signal output (OT2). Signal processing circuit according to one of claims 1 to 9, further comprising first and second data ports (C1, C2) for feeding a first and a second control word and a multiplier (MP), the input side with the first and second data port (C1, C2) and the output coupled to the data input (DIN) is. Display device with a screen processor (DPR), which is set up, a picture signal for controlling a Screen (DIS) and a pulse modulated brightness signal (PM1) and having a signal processing circuit after one the claims 1 to 10, whose signal input (IN1) for supplying the brightness signal (PM1) is set up, wherein the display device is set up is a screen (DIS) illumination, in particular a backlight, dependent on an output signal at the signal output of the signal processing circuit perform. Method for signal processing, comprising - Feeding one pulse modulated input signal (PM1); - generating an intermediate signal by pulse modulation as a function of a data word (DW) in the clocked Operation, whereby the pulse modulation by the input signal (PM1) is controlled; and - Produce a pulse-shaped Output signal by linking of the input signal (PM1) with the intermediate signal. The method of claim 12, wherein a clocked Control signal by linking of the input signal (PM1) is generated with a reference clock signal (FREF) and generating the intermediate signal in response to the clocked control signal he follows. The method of claim 12, wherein performing the Pulse modulation from a logic state of the input signal (PM1) is dependent. Method according to one of claims 12 to 14, wherein the Data word (DW) by multiplying a first and a second Control word is generated.