DE102008020812A1 - Device for detecting an error present in a processor - Google Patents

Abstract

The invention relates to a device for detecting a fault present in a processor (1) by a monitoring processor (2) which is connected to the processor (1). It is provided that the monitoring processor (2) contains a questioning unit (6), which via an interface (8) in a module (4) of the processor (1) which is considered to be unsafe, with a response unit (7) in a module which is considered safe (5) of the processor (1).

Description

The The invention relates to a device for detecting one in one Processor existing error through a monitoring processor that with connected to the processor.

It has already been proposed, a processor through a separate monitoring processor to monitor for errors. The monitoring is based on this on a cyclical communication. In such a processor are often Contain modules that have already proven themselves in use. These Modules are finished products and are considered error-free because they are have long been in use with many users error-free. A cyclic communication is not provided. Nevertheless, can it by accident occurring hardware error to a fault in the as error-free applicable modules.

One such hardware failure will not by the separate monitoring processor discovered so that the modules are uncertain. This is due to the fact that the monitoring processor the tried and tested in the field Modules of the processor with cyclic communication not reached.

Of the Invention is based on the object, a device for detecting indicate a bug in a processor that is more reliable than all previously existing devices works and also as unsafe modules checked. Especially are also supposed modules of the processor, which does not have a direct connection have to the monitoring processor, to be checked.

The Task is according to the invention solved by that the monitoring processor contains a question unit, the above an interface in an insecure module of the processor with a response unit in a valid module of the processor communicates.

In order to the advantage is achieved that if the correct answer to the question asked arrives with high reliability, that there is no error in all modules of the processor.

For example is in the processor considered to be unsafe in the processor as safe upstream test module. Already in the test module can then the response coming from the responder will be analyzed and it can appropriate action is taken in the event of a detected error.

For example Both the question unit and the answer unit are by a sure one Telegram connected. Ensuring such a secure telegram that the question to the answer unit and accordingly to this Question belonging Answer back again to the question unit arrives. Every secure telegram has a specific one Number to make it reliable can be recognized.

For example is by the question unit a simple algorithm in the interface can be generated and transmitted to the response unit for calculation and for return the result to the monitoring processor and / or to the test module considered safe. Based on the returned answer, which was already known, it is reliably determined whether the processor and, in particular, the module considered insecure, are functional.

Of the Algorithm can be a simple math problem, such as 2x + 1 where x is an arbitrary number. The algorithm is in the Question unit and known in the response unit.

For example are the monitoring processor and / or the safe test module for detecting a wrong one and / or delayed back sent result suitable.

With the device according to the invention is particularly the advantage Achieves that simple means reliable error in a processor It can also be seen in an insecure module of the processor and in particular is a random hardware error.

The device according to the invention is explained in more detail with reference to the drawing:
To detect an error in a processor 1 is a monitoring processor 2 present with the processor 1 communicates. In the processor 1 There are several modules 3 to 5 one of which is an insecure module 4 is because, although it is a proven module, it may be disturbed by a random hardware failure.

To all modules 3 to 5 in the processor 1 In the same way to be able to monitor errors, there is a question unit 6 in the monitoring processor 2 and a response unit 7 in a secure module 5 of the processor 1 , The question unit 6 and the response unit 7 are connected by a secure telegram so that a question is always associated with the answer belonging to it. In the uncertain module 4 is an interface 8th present the questions of the question unit 6 and the responses of the responder 7 forwards. When a correct answer to a question is received, it is determined with high reliability that the module is considered unsafe 4 there is no error.

From the question unit 6 will be in a tele an algorithm for the response unit 7 Posted. From there it will be in the processor 1 calculated result to the question unit 6 or to a test module considered safe 3 returned. If the result agrees with the expected result, it is assumed that the module considered unsafe 4 and thus the entire processor 1 are in a safe condition.

With the device according to the invention is a reliable verification of the processor 1 possible, even if in the unsafe module 4 The monitoring process should have interfering hardware errors.

Claims (5)

Device for detecting a in a processor ( 1 ) existing error by a monitoring processor ( 2 ) connected to the processor ( 1 ), characterized in that the monitoring processor ( 2 ) a question unit ( 6 ), which has an interface ( 8th ) in a module considered unsafe ( 4 ) of the processor ( 1 ) with a response unit ( 7 ) in a module that is considered safe ( 5 ) of the processor ( 1 ). Device according to claim 1, characterized in that the module which is considered to be insecure ( 4 ) in the processor ( 1 ) a test module considered as safe ( 3 ) is connected upstream. Device according to one of claims 1 or 2, characterized in that the questioning unit ( 6 ) and the response unit ( 7 ) are interconnected by a secure telegram. Device according to one of claims 1 to 3, characterized in that by the question unit ( 6 ) a simple algorithm in the interface ( 8th ) and to the response unit ( 7 ) for calculating and returning the result to the monitoring processor ( 2 ) and / or to the test module considered safe ( 3 ). Device according to Claim 4, characterized in that the monitoring processor ( 2 ) and / or the test module considered safe ( 3 ) are suitable for detecting a false and / or delayed return result.