DE102008026432A1 - Integrated circuit for use in e.g. magnetoresistive RAM module, has set of resistance change memory elements, and set of memory element selection devices that are floating-body-selection devices such as FETs or thyristors - Google Patents

Abstract

According to an embodiment of the invention, there is provided an integrated circuit comprising a plurality of resistance change memory elements and a plurality of memory element selectors, the selectors being floating body selectors.

Description

integrated Circuits containing resistive memory cells ("resistance change memory cells") are known.

The The object underlying the invention is the electrical properties of such integrated circuits.

to solution This object is achieved by the invention an integrated circuit according to claim 1 ready. Furthermore, the invention provides a memory module according to claim 11 ready. After all the invention provides methods for operating an integrated Circuit according to patent claims 13 and 24 ready. Advantageous embodiments or developments of the inventive concept can be found in the subclaims.

According to one embodiment The invention provides an integrated circuit which comprising: a plurality of resistance change memory elements, and a plurality of memory element selection means, wherein the selectors are floating body selectors.

According to one embodiment In accordance with the invention, the selectors are field effect transistor devices or thyristor devices.

According to one embodiment According to the invention, the integrated circuit has a plurality of Bit lines and a plurality of word lines, each one Selector means a first terminal connected to one of the bit lines via a memory element connected to a second terminal connected to one of the word lines and the body of the selector, and a third one Terminal connected to an area of the integrated circuit is set to a fixed potential has.

According to one embodiment The invention can be any selection device from a non-conductive state be switched into a conduction state by a switching voltage created between the first port and the third port is, and by the voltage of the second terminal on a switching potential is set.

According to one embodiment of the invention, the conduction state is a punch-through state, a bipolar state or a conductive state after occurrence of a Snap-back process.

According to one embodiment invention, the integrated circuit has a circuit, before memory element writes or memory element read processes be executed the potential of the floating bodysuits of all selection devices, which are connected to the same bit line sets by the first connections the selectors connected to the same bit line are set to an adjustment potential.

According to one embodiment According to the invention, the integrated circuit has an SOI architecture on.

According to one embodiment According to the invention, the resistance change memory elements are phase change memory elements.

According to one embodiment In accordance with the invention, the resistance change memory elements are magneto-resistive Memory elements.

According to one embodiment In accordance with the invention, the resistance change memory elements are programmable Metallisierungsspeicherelemente.

According to one embodiment The invention relates to a memory module with at least one integrated A circuit is provided, comprising: a plurality of resistance change memory elements, and a plurality of memory element selection means, wherein the selectors are floating body selectors.

According to one embodiment According to the invention, the memory module is stackable.

According to one embodiment The invention relates to a method for operating an integrated A circuit is provided which includes a plurality of resistance change memory elements and a plurality of memory element selection devices, wherein the selecting means comprise floating bodies, and wherein the method comprises: generating a voltage drop across one Selection device, such that the selection device of a Non-conducting state switches to a conduction state; and reading memory state, or writing the memory state of a Memory element assigned to the selector after the selector has been switched to the line state.

According to an embodiment of the invention, the integrated circuit has a plurality of bit lines and a plurality of word lines, each selection device having a first terminal connected to one of the bit lines via a memory element, a second terminal connected to one of the word lines and the body the selector is connected, and ei NEN third terminal, which is connected to a region of the integrated circuit, which is set to a fixed potential has.

According to one embodiment The invention will be a selection device of the non-conductive state switched to the conduction state by a switching voltage between is applied to the first terminal and the third terminal, and by changing the voltage of the second terminal to a switching potential is set.

According to one embodiment The invention is, before a memory cell writing process or a memory cell reading process is executed, the potential of the changed floating bodies of a plurality of selection means.

According to one embodiment The invention is, before a memory cell writing process or a memory cell reading process is executed, the potential of the floating Bodys of all selectors changed using the same bitline are connected.

According to one embodiment of the invention, after the selector of a non-conductive state was switched into a conduction state, the voltage of the second Connection reduces to a holding potential, without the selection device back to switch to the non-conducting state.

According to one embodiment In the invention, the potential of the floating body is changed by the potential of the first connections changed the selection become.

According to one embodiment In the invention, the potential of the floating body is changed by a voltage pulse to the first terminals of the selectors supplied becomes.

According to one embodiment According to the invention, the voltage pulse has a duration of 100 ps and 100 ns and one strength from 0.2V to 2V.

According to one embodiment The invention relates to a method for operating an integrated A circuit is provided which includes a plurality of resistance change memory elements and a plurality of memory element selection devices, wherein the selecting means selecting means with floating Bodys, and wherein the method comprises: generating a voltage drop across one conductive path through a memory element and a selection device, which is assigned to the memory element passes through; and Determining the storage state of the storage element based on the switching behavior of the selector of a resistance state in a conduction state resulting from the voltage drop.

According to one embodiment of the invention the voltage drop over drops the conductive path, approximately 0.2V to 5V.

The Invention will be described below with reference to the figures for example embodiment explained in more detail. It demonstrate:

1 a schematic cross-sectional view of a magnetoresistive memory cell;

2 an integrated circuit associated with the in 1 shown circuit is usable;

3A a schematic cross-sectional view of a programmable Metallisierungsspeicherelements, which is in a first switching state;

3B a schematic cross-sectional view of a programmable Metallisierungsspeicherelements, which is in a second switching state;

4 a schematic cross-sectional view of a phase change storage element;

5 a schematic representation of an integrated circuit having phase change memory elements;

6 a schematic cross-sectional view of a carbon storage element, which is in a first switching state;

7 a schematic cross-sectional view of a carbon storage element, which is in a second switching state;

8th a flowchart of a method for operating an integrated circuit according to an embodiment of the invention;

9 a flowchart of a method for operating an integrated circuit according to an embodiment of the invention;

10 a schematic representation of an integrated circuit according to an embodiment of the invention;

11 a schematic representation of an integrated circuit according to an embodiment of the invention;

12 Voltages used to operate an integrated circuit according to an embodiment of the invention;

13 Voltages used to operate an integrated circuit according to an embodiment of the invention;

14A a schematic perspective view of a memory module according to an embodiment of the invention; and

14B a schematic perspective view of a memory module according to an embodiment of the invention.

In the characters can identical or corresponding areas, components or groups of components be marked with the same reference numerals. Furthermore, it is too mention, that the drawings are schematic in nature, d. H. not to scale need to be.

There embodiments of the invention on magnetoresistive memory devices, the resistance change memory cells (magneto-resistive memory cells), are applicable Below is a brief outline of magnetoresistive memory devices are given.

In magneto-resistive memory cells instead of the charge of a Elektrons the magnetization of a material, d. H. the being of Electrons used to represent information.

1 shows an embodiment of a magneto-resistive resistor element 100 , which may for example be part of an MRAM device, and that a soft magnetic layer 102 , a tunnel layer 104 and a hard magnetic layer 106 having. The soft magnetic layer 102 and the hard magnetic layer 106 usually have a plurality of magnetic metal layers, for example, eight to twelve layers of materials such as PtMn, CoFe, Ru or NiFe. A logical state becomes through the directions of the magnetizations of the soft magnetic layer 102 and the hard magnetic layer 106 represents.

To that in the magnetoresistive resistive element 100 stored state can read, as in 2 shown circuit with a sense amplifier (SA) 230 be used. A reference voltage UR is applied to one end of the resistor element 100 created. The other end of the resistance element 100 is connected to a measuring resistor Rm1. The other end of the measuring resistor Rm1 is earthed. The current passing through the resistor element 100 running, is equal to the current Izelle. A reference circuit 232 provides a reference current Iref supplied to one end of the sensing resistor Rm2. The other end of the measuring resistor Rm2 is earthed.

Since the embodiments of the present invention are applicable to devices containing programmable metallization cells (PMCs) such as conductive bridging random access memory (CBRAM) devices, in the following description, reference is made to FIGS 3A and 3B explaining an important principle underlying CBRAM devices.

A CBRAM element 300 has a first electrode 301 , a second electrode 302 and a solid electrolyte block (also known as an ion conductor block) 303 that is between the first electrode 301 and the second electrode 302 is arranged on. The solid electrolyte block may also be shared by multiple memory cells (not shown here). The first electrode 301 contacts a first surface 304 of the solid electrolyte block 303 , the second electrode 302 contacts a second surface 305 of the solid electrolyte block 303 , The solid-state electrolyte block 303 is opposite its environment by an isolation structure 306 isolated. The first surface 304 is usually the top, the second surface 305 the bottom of the solid electrolyte block 303 , The first electrode 301 is usually the upper electrode, the second electrode 302 the lower electrode of the CBRAM element 300 , One of the first and second electrodes 301 . 302 One is a reactive electrode, the other is an inert electrode. For example, the first electrode 301 the reactive electrode, and the second electrode 302 the inert electrode. In this case, the first electrode 301 for example, from silver (Ag), the solid electrolyte block 303 from chalcogenide material, and the isolation structure 306 consist of SiO ₂ or Si ₃ N ₄ . The second electrode 302 may alternatively or additionally nickel (Ni), platinum (Pt), iridium (Ir), rhenium (Re), tantalum (Ta), titanium (Ti), ruthenium (Ru), molybdenum (Mo), vanadium (V), may include conductive oxides, silicides, and nitrides of the aforementioned materials, and may further include alloys of the aforementioned materials. The thickness of the ion conductor block 303 may for example be 5 nm to 500 nm. The thickness of the first electrode 301 may for example be 10 nm to 100 nm. The thickness of the second electrode 302 For example, it may be 5 nm to 500 nm, 15 nm to 150 nm, or 25 nm to 100 nm. The embodiments of the invention are not limited to the above-mentioned materials and thicknesses.

According to one embodiment of the invention, chalkogenide material (more generally: the material of the ion conductor block 303 ) to understand a compound having oxygen, sulfur, selenium, germanium and / or tellurium. According to one embodiment of the invention, chalcogenide material is a compound of a chalcogenide and at least one metal of group I or group II of the periodic table, for example arsenic trisulfide silver. Alternatively, the chalcogenide material contains germanium sulfide (GeS _x ), germanium selenide (GeSe _x ), tungsten oxide (WO _x ), copper sulfide (CuS _x ) or the like. Furthermore, the chalcogenide material may include metal ions, wherein the metal ions may be a metal selected from a group consisting of silver, copper, and zinc, or a combination or alloy of these metals. The ion conductor block 303 may consist of solid electrolyte material.

When a voltage across the solid electrolyte block 303 falls off, as in 3A is indicated, a redox reaction is set in motion, the Ag ⁺ ions from the first electrode 301 comes out and into the solid-state electrolyte block 303 into where they are reduced to silver. In this way, silver-containing clusters 308 in the solid electrolyte block 303 educated. When the voltage across the solid electrolyte block 303 decreases long enough, increases the size and number of silver-rich clusters within the solid electrolyte block 303 so strong that a conductive bridge (conductive path) 307 between the first electrode 301 and the second electrode 302 is trained. When the in 3B shown voltage across the solid electrolyte block 303 drops (inverse voltage compared to the in 3A shown voltage), a redox reaction is set in motion, the Ag ⁺ ions from the solid electrolyte block 303 out to the first electrode 301 drives, where they are reduced to silver. This will change the size and number of silver-rich clusters 308 within the solid electrolyte block 303 reduced. If this happens long enough, the conductive bridge becomes 307 deleted.

The current memory state of the CBRAM element 300 determine is a measuring current through the CBRAM element 300 directed. The measuring current experiences a high resistance when in the CBRAM element 300 no conductive bridge 307 is formed, and experiences a low resistance when in the CBRAM element 300 a conductive bridge 307 is trained. For example, a high resistance represents logic "0", whereas a low resistance logically represents "1" or vice versa. Instead of a measuring current, a measuring voltage can also be used.

There embodiments the invention to phase change memory devices, the resistance change memory cells (Phase change memory cells) The following is a brief outline of a Phase-change memory device are given.

Phase change memory devices include Phase change elements, which in turn is phase change material exhibit. The phase change material can be switched between at least two crystallization states (i.e., the phase change material may assume at least two degrees of crystallization), each one Crystallization state represents a memory state. If the number of possible crystallization states is two, the crystallization state, which has a high degree of crystallization, also as "crystalline Condition "indicates where against the crystallization state, which has a low degree of crystallization also known as "amorphous State " becomes. Different crystallization states can be differentiated by corresponding different electrical properties are distinguished from each other, in particular by different resistances, which are implied by this. For example, a crystallization state, a high degree of crystallization (ordered atomic structure) generally has a lower resistance than a crystallization state, which has a low degree of crystallization (disordered atomic structure). For the sake of simplicity, it shall be assumed below that that the phase change material two crystallization states can accept (an "amorphous State "and a "crystalline Status"). However, it should be mentioned that also uses additional intermediate states can be.

Phase change memory elements can from the amorphous state to the crystalline state (and vice versa), when temperature fluctuations occur within the phase change material. Such temperature changes can be evoked in different ways. For example may be a current through the phase change material (or a voltage can be applied to the phase change material be created). Alternatively, a resistance heating element, that next to the phase change material is provided, a current or voltage are supplied. To set the memory state of a phase change memory element, a measuring current can be passed through the phase change material (or a measurement voltage can be applied to the phase change material), wherewith the resistance of the phase change memory element, representing the memory state of the phase change memory element, is measured.

4 shows a cross-sectional view of an exemplary Phasenänderungsspeicherele ments 400 (Active-in-via type). The phase change memory element 400 has a first electrode 402 , Phase change material 404 , a second electrode 406 as well as insulating material 408 on. The phase change material 404 becomes lateral through the insulating material 408 locked in. A selection device (not shown) such as a transistor, a diode or other active device may be connected to the first electrode 402 or the second electrode 406 be coupled to the application of the phase change material 404 with current or voltage using the first electrode 402 and / or the second electrode 406 to control. To the phase change material 404 into the crystalline state, the phase change material 404 be subjected to a current pulse and / or a voltage pulse, wherein the pulse parameters are selected so that the temperature of the phase change material 404 above the phase change material crystallization temperature, but kept below the phase change material melting temperature. If the phase change material 404 is to be converted into the amorphous state, the phase change material 404 be subjected to a current pulse and / or a voltage pulse, wherein the pulse parameters are selected so that the temperature of the phase change material 404 rises rapidly above the phase change material melting temperature, with the phase change material 404 subsequently cooled rapidly below its crystallization temperature.

The phase change material 404 can contain a variety of materials. According to one embodiment, the phase change material 404 comprise (or consist of) a chalcogenide alloy containing one or more elements of group VI of the periodic table. According to a further embodiment, the phase change material 404 Comprise or consist of chalcogenide composite material such as GeSBTe, SbTe, GeTe or AbInSbTe. According to a further embodiment, the phase change material 404 comprise or consist of a chalcogen-free material, such as GeSb, GaSb, InSb, or GeGaInSb. According to a further embodiment, the phase change material 404 comprise or consist of any suitable material having one or more of the elements Ge, Sb, Te, Ga, Bi, Pb, Sr, Si, P, O, As, In, Se, and S.

According to one embodiment of the invention, at least one of the first electrode 402 and the second electrode 406 Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W or mixtures or alloys thereof (or consist thereof). According to a further embodiment, at least one of the first electrode 402 and the second electrode 406 Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W and two or more elements of the group: B, C, N, O, Al, Si, P, S and / or mixtures and alloys thereof (or consist of this). Examples of such materials are TiCN, TiAlN, TiSiN, W-Al ₂ O ₃ , and Cr-Al ₂ O ₃ .

5 shows a block diagram of a memory device 500 containing a write pulse generator 502 , a distribution circuit 504 , Phase change memory elements 506a . 506b . 506c . 506D (For example, phase change memory elements 400 as in 4 shown) and a sense amplifier 508 having. According to one embodiment, the write pulse generator generates 502 Current pulses or voltage pulses corresponding to the phase change memory elements 506a . 506b . 506c . 506D by means of the distribution circuit 504 whereby the storage states of the phase change storage elements 506a . 506b . 506c . 506D be programmed. According to one embodiment, the distribution circuit 504 a plurality of transistors, the the phase change memory elements 506a . 506b . 506c . 506D or heating elements, in addition to the phase change storage elements 506a . 506b . 506c . 506D are provided to supply DC pulses or DC pulses.

As already indicated, the phase change material of the phase change memory elements 506a . 506b . 506c . 506D from the amorphous state to the crystalline state (or vice versa) by changing the temperature. More generally, the phase change material can be converted from a first degree of crystallization to a second degree of crystallinity due to a temperature change. For example, the bit value "zero" may be assigned to the first (low) degree of crystallization, and the bit value "1" to the second (high) degree of crystallization. Since different degrees of crystallization imply different electrical resistances, the sense amplifier is 508 capable of storing one of the phase change memory elements 506a . 506b . 506c or 506D depending on the resistance of the phase change material to determine.

To achieve high storage densities, the phase change memory elements 506a . 506b . 506c and 506D be designed to store several bits of data (ie the phase change material can be programmed to different resistance values). For example, if a phase change memory element 506a . 506b . 506c and 506D is programmed to one of three possible resistance levels, 1.5 data bits per memory cell are stored. If the phase change memory elements to one of four possible resistance levels are programmed, two bits of data per memory cell can be stored, and so on.

In the 5 The illustrated embodiment may similarly be applied to other resistance change memory elements such as magnetoresistive memory elements (eg, MRAMs), organic memory elements (eg, ORAMs), or transition metal oxide memory elements (TMOs).

Another type of resistance change memory element that can be used is to use carbon as a resistance change material. In general, amorphous carbon rich in sp ³ -hybridized carbon (ie, tetrahedral bonded carbon) has high resistance, whereas amorphous carbon rich in sp ² -hybridized carbon (i.e., trigonal-bonded carbon) has low resistance , This difference in resistance can be utilized in resistance change memory elements.

According to one embodiment of the invention, a carbon storage element is formed in a similar manner as described above in connection with the phase change storage elements. A temperature-induced change between an sp ³ -rich state and an sp ² -rich state can be used to change the resistance of amorphous carbon material. These varying resistances can be used to represent different memory conditions. For example, an sp ³ rich state (high resistance state) may represent "zero", and an sp ² rich state (low resistance state) may represent "one". Intermediate resistance states can be used to represent multiple bits as described above.

In this type of carbon storage element, the use of a first temperature generally causes a transition that converts sp ³ -rich amorphous carbon into sp ² -rich amorphous carbon. This transition can be reversed by the application of a second temperature, which is typically higher than the first temperature. As mentioned above, these temperatures may be generated by, for example, charging the carbon material with a current pulse and / or a voltage pulse. Alternatively, the temperatures may be generated using a resistance heating element provided adjacent to the carbon material.

Another way to utilize resistance changes in amorphous carbon to store information is the electro-field induced formation of a conductive path in an insulating amorphous carbon film. For example, applying a voltage pulse or current pulse may cause the formation of a conductive sp ² filament in insulating, sp ³ -rich amorphous carbon. The operation of this resistance carbon storage type is described in FIGS 6 and 7 shown.

6 shows a carbon storage element 600 that a top contact 602 a carbon storage layer 604 with insulating amorphous carbon material rich in sp ³ -hybridized carbon atoms and a bottom contact 606 having. As in 7 can be shown by means of a current (or voltage) passing through the carbon storage layer 604 is passed, an SP ² filament 650 in the sp ³ -rich carbon storage layer 604 be formed, whereby the resistance of the memory element is changed. Applying a high energy (or reverse polarity) current pulse (or voltage pulse) may be the sp ² filament 650 destroy what the resistance of the carbon storage layer 604 is increased. As discussed above, the changes in the resistance of the carbon storage layer 604 be used to store information, for example, representing a high resistance state "zero", and a low resistance state "one". In addition, in some embodiments, intermediate levels of filament formation or formation of multiple filaments in sp ³ -rich carbon films may be used to provide multiple varying resistance levels, thereby storing a plurality of information bits within a carbon storage element. In some embodiments, alternating sp ³ -rich carbon layers and sp can ² -rich carbon layers are used, the sp ² -rich layers stimulate the formation of conductive filaments, so that the amperage and / or voltage levels that for writing a value to this type of carbon memory be used, can be reduced.

8th shows a method 800 for operating an integrated circuit according to an embodiment of the invention. at 802 a voltage drop is applied via a selector such that the selector switches from a non-conductive state to a conductive state. at 804 the memory state of a memory element assigned to the selector is read or written after the selector has been switched to the conduction state.

According to an embodiment of the invention The selection devices are field-effect transistor devices or thyristor devices.

According to one embodiment of the invention, the conduction state is a punch-through state, a conduction mode after the occurrence of a snap-back effect, or on Bipolar.

According to one embodiment According to the invention, the integrated circuit has a multiplicity of bit lines and a variety of word lines. Each selection device has a first terminal that connects to one of the bitlines Memory element is connected to a second port, the one connecting the word lines to the body of the selection device, and a third connection, with an area of integrated Circuit connected to a fixed potential, ground potential, for example.

According to one embodiment The invention is a selection device of the non-conductive state in the non-line state Switched by a switching voltage between the first and the third terminal is applied, and by the voltage of the second Connection is set to a switching potential.

According to one embodiment According to the invention, after a selecting direction of the non-conducting state has been switched to the line state, that at the second terminal reduced potential, without the selection device back in the To switch non-conducting state. For example, that can be done on the second terminal potential applied to a holding potential (the Potential applied to wordlines that are not selected memory elements connected) are reduced.

According to one embodiment of the invention, after the selector of the non-conductive state has been switched to the line state, memory cell write processes executed by respective memory cell write currents through the selection device be directed, d. H. by the storage element, that of the selection device is assigned. Furthermore, memory cell read processes accomplished be by reading currents be passed through the selector, d. H. through the storage element, assigned to the selector.

According to one embodiment the invention is during the reading and writing processes the voltage between the first terminal and the third port is reduced without the selector back to switch to the non-conductive state.

According to one embodiment The invention is, before a memory cell writing process or a memory cell reading process relating to a particular memory element accomplished the potential of the floating bodys of a plurality of selection devices changed. According to one embodiment the invention, this potential change is carried out before the selector assigned to the particular memory element is switched from the non-conductive state to the conductive state.

According to one embodiment The invention is, before a memory cell writing process or a memory cell reading process relating to a particular memory element accomplished becomes the potential of the floating bodysuits of all the selection devices changed, those with the same bitlines as the particular memory element are connected. According to one embodiment the invention, this potential change is carried out before the selector assigned to the particular memory element is switched from the non-conducting state to the conducting state becomes.

According to one embodiment In the invention, the potential of the floating body is changed by the potential of the first connections changed the selection become. By doing so, the charge (charge amount) becomes within changed the floating bodysuits, which changed their potential become.

According to one embodiment According to the invention, the potentials of the floating bodies are changed so that parasitic Effects that occur within the selectors that contribute to are located adjacent to the particular selector (for example, all the selectors associated with the same Bit line connected as the particular (selected) selection device are). For example, parasitic effects can be prevented cause neighboring selectors to go from a non-conductive state switch to a conduction state, which is not desirable.

According to one embodiment In the invention, the potential of the floating body is changed by the first connections the selection means a voltage pulse is supplied.

Of the Voltage pulse may be, for example, 0.2 V to 1 V. Farther For example, the voltage pulse may last for 0.5 ns Have 10 ns.

According to one embodiment of the invention, the voltage pulse is a negative voltage pulse. This means that the voltage pulse has an opposite amplitude direction compared to the voltage pulse directions used to switch a selector from a non-conducting state to the conducting state. For example, the voltage pulse used to change the potential of the floating body may have a negative amplitude, and the voltage pulse used to switch a selector from a non-conductive state to the conductive state may have a positive amplitude, or vice versa.

9 shows a method 900 for operating an integrated circuit according to an embodiment of the invention. at 902 For example, a voltage drop is generated across a conduction path passing through a memory element and a selector assigned to the memory element (here, the term "voltage drop" means a voltage drop across the entire electrical component of memory element and selector). at 904 The memory state of the memory element is determined based on the switching behavior of the selector from a resistance state to a conduction state, resulting from the voltage drop. In other words, the memory state of the memory element is not determined by passing an additional measurement current through the memory element after the corresponding selection device has been switched from a non-conducting state to a conducting state. Rather, the circuit behavior of the selector itself gives an indication of the memory state of the memory element: If the total resistance of the memory element resistance and the selector resistor is above a certain resistance threshold, the voltage drop that drops across the conduction path may not be sufficient to switch the selector to the conduction state , In contrast, when the storage element is in a low resistance state, the voltage drop across the conduction path may be sufficient to switch the selection device from the non-conduction state to the conduction state. In this way, the memory cell reading process can be speeded up.

According to one embodiment of the invention the voltage drop over falls off the line path, approximately 0.2 V to 5 V. According to a embodiment of the invention the voltage drop over the line path drops, about 0.2V or about 5 V.

According to one embodiment of the invention the voltage drop over falls off the line path, approximately 0.7 V to 3 V. According to a embodiment of the invention the voltage drop over drops off the line path, about 0.7V or 3 V.

All embodiments related to 8th Also, insofar as applicable, may be applied to the embodiments discussed in connection with 9 were discussed.

10 shows an integrated circuit 1000 according to an embodiment of the invention. The integrated circuit 1000 has a plurality of resistance change memory elements 1002 and a plurality of memory element selection devices 1004 on. The selection devices 1004 are selection devices with floating body.

According to one embodiment of the invention, the selection means 1004 MOSFET devices or thyristor devices.

11 shows an integrated circuit 1100 according to an embodiment of the invention. The integrated circuit 1100 has a plurality of memory elements 1002 and a plurality of selectors 1004 on. The integrated circuit 1100 also has a plurality of bitlines 1102 and a plurality of word lines 1104 on. Each selection device 1004 has a first connection 1106 that with one of the bitlines 1102 over the storage element 1002 connected, a second port 1108 who collaborated with one of the wordlines 1104 and the body 1110 the selection device 1004 connected, as well as a third connection 1112 that with an area 1114 the integrated circuit 1100 set to a fixed potential. The area 1114 For example, when set to a fixed potential, it may be an area of a grounded semiconductor substrate that is different from all memory cells 1120 the integrated circuit 1100 shared (shared) becomes.

It should be noted that the second connections 1108 directly with the bodysuits 1110 the selection devices 1004 can be connected. However, the phrase "connected to the body" may also mean that the second port 1108 connected to an electrode that is on the body 1110 is provided, but against the body 1110 is isolated by an insulating layer (which may for example be the case when the selection means 1004 MOSFET devices are).

According to one embodiment of the invention, each selection device 1004 be switched from a non-conductive state to a conductive state by a switching voltage between the first terminal 1106 and the third port 1112 is applied, and by the voltage of the second terminal 1108 on a switch potential is set. By the selection device 1004 is switched to the conduction state, the memory element 1002 , that of the selection device 1004 assigned is selected.

One effect of using floating body selectors is that there is no low impedance connection between the body 1110 the selection device 1004 and any other terminal set to a fixed potential must be provided when the selector 1004 is in the non-conducting state. Such a low-resistance connection, for example to the third port 1112 or to any other / additional connector, such as the substrate, is normally required on non-floppy body selectors. However, such low-resistance interconnects complicate the integrated circuit fabrication process and may also increase the integrated circuit space requirement (a larger chip area area is needed).

According to one embodiment According to the invention, the conduction state may be a punch-through state be. However, other types of conductive states are possible, for example a firing state ( "Kindle Fashion"), or a conduction state after the occurrence of a snap-back process ("snap back").

According to one embodiment of the invention, the integrated circuit 1100 a circuit which, before a memory element write process is performed on a particular memory element (ie, before the memory element is selected), the potentials of the floating bodies 1110 the selection devices 1004 sets that with the same bit line 1102 how the particular memory element is connected by setting potential to the first terminals 1108 the selection devices 1004 which is supplied with the same bit line 1102 connected, such as later in connection with 13 will be explained. An effect of this embodiment is that it can avoid parasitic effects that occur in selectors connected to the same bitline 1102 are connected as the particular memory element.

According to one embodiment of the invention, the integrated circuit 1100 an SOI architecture ("Silicon and Insulator").

According to one embodiment According to the invention, the resistance change memory elements are phase change memory elements.

According to one embodiment The invention relates to the resistance change elements programmable metallization memory elements.

12 shows an example of a method of operating the integrated circuit 1100 , To enter a memory state in the memory element 1002 ₂ to write, the voltage of the bit line 1102 from a first voltage value 1200 to a second voltage value 1202 set at a time t ₁ . It is assumed here that the area 1114 is set to a fixed potential. In this way, the same voltage drop across each selection device 1004 generated with the same bit line 1102 connected is. Then, at a time t _2, the voltage of the word line becomes 1104 ₂ from a first voltage value 1204 to a second voltage value 1206 set. This switches the selection device 1004 ₂ from the non-conductive state to the conductive state, and a programming current flows through the memory element 1002 ₂ , whereby the memory element 1002 ₂ is programmed. At a time t ₃ , the voltage of the word line drops 1104 ₂ back to the first voltage value 1204 from. Furthermore, at a time t _4, the voltage value of the bit line drops 1102 from the second voltage value 1202 back to the first voltage value 1200 from.

The time duration between the first time t ₁ and the fourth time t ₄ may, for example, be in a range between 1 ns and 1000 ns. The voltage difference between the first voltage value 1200 and the second voltage value 1202 may be between 0.2V and 5V during a memory state write process, for example. For example, good results have been achieved using a voltage range between 1V and 5V during a memory state writing process. During a memory state read process, the voltage difference between the first voltage value 1200 and the second voltage value 1202 for example, in a range between 0.2 V and 5 V. For example, good results have been achieved using a voltage range between 0.2V and 0.5V during a memory state read process. The voltage difference between the first voltage value 1204 and the second voltage value 1206 may be between 0.5V and 2V during the memory state read process or the memory state write process, for example.

13 shows voltages used to operate an integrated circuit according to another embodiment of the invention. The voltages that are used are similar to those in 12 shown voltages.

However, in addition falls before the time t _1, at time t ₀ , the voltage on the bit line 1102 from the first voltage value 1200 to a third voltage value 1208 , Then the voltage changes from the third voltage value 1208 to the second voltage value 1202 at time t ₁ . For example, the voltage pulse applied between times t ₀ and t ₁ may have a duration between 100 ps and 100 ns and a magnitude between 0.2 V and 5 V. According to one embodiment of the invention, the voltage difference between the first voltage value 1200 and the third voltage value 1208 between 0.2V and 2V (good results). In particular, good results have been obtained using a voltage difference between the first voltage value 1200 and the third voltage value 1208 which is between 0.2V and 1V. The time interval between the times t ₀ and t ₁ may be, for example, between 0.5 ns and 10 ns. Here, the voltage pulse applied between times t ₀ and t ₁ is a negative voltage pulse. This means that the voltage pulse has the opposite amplitude direction compared to the voltage pulse directions (positive) used to switch the selector 1004 from a non-conductive state to a conductive state.

Using the third voltage value 1208 which is lower than the first voltage value 1200 That causes the potential of floating bodysuits 1110 all selection devices 1004 that with the same bit line 1112 like the selection device 1004 ₂ are changed (to be reduced, for example) such that during the memory state writing process of the memory element 1002 ₂ no parasitic effects within selectors 1004 that do not occur the selector 1004 ₂ themselves are. For example, it is possible to prevent the selection device from being prevented 1004 ₁ switches from the non-conductive state to the conductive state.

As in 14A and 14B 1, embodiments of the memory devices / integrated circuits according to the invention can be used in modules. In 14A is a memory module 1400 shown that one or more integrated circuits 1404 which is on a substrate 1402 are arranged. Every integrated circuit 1404 may include multiple memory cells (memory elements). The memory module 1400 can also use one or more electronic devices 1406 comprising memory, processing circuits, control circuits, address circuits, bus connection circuits, or other circuits or electronic devices that may be combined with memory device (s) of a module, such as the integrated circuits 1404 , Furthermore, the memory module 1400 a plurality of electrical connections 1408 which can be used to the memory module 1400 to connect with other electronic components, such as other modules.

As in 14B As shown, these modules may be stackable to form a stack 1450 train. For example, a stackable memory module 1452 one or more integrated circuits 1456 included on a stackable substrate 1454 are arranged. Every integrated circuit 1456 can contain several memory cells. The stackable memory module 1452 can also use one or more electronic devices 1458 comprising memory, processing circuits, control circuits, address circuits, bus connection circuits, or other circuitry, and which may be combined with memory devices of a module, such as the integrated circuits 1456 , Electrical connections 1460 are used to make the stackable memory module 1452 with other modules within the stack 1450 connect to. Other modules of the stack 1450 may be additional stackable memory modules that are the stackable memory module described above 1452 or other types of stackable modules, such as stackable processing modules, communication modules, or modules containing electronic components.

In The following description is intended to provide further aspects of example embodiments of the invention explained become.

Around cost competitive capable are PCRAM devices or other resistance change cell devices necessary with small dimensions. In a planar array transistor or in a transistor where the source / drain contacts are in the same horizontal plane (for example, a FinFET) is the cell size for a 1T1R cell on 6F2 for geometric reasons limited, where F is the smallest feature size.

Around Making a 1T1R cell smaller than 6F2 can be a vertical current flow can be used as this is the use of a buried ground plate allowed.

Various array architectures can for memory cells smaller than 6F2 with a vertically surrounded gate or a double gate transistor be used, wherein a buried, diffused grounding plate is used in the silicon substrate.

When a body contact comes to each cell is provided, the buried ground plate should have a net-like arrangement, which complicates the manufacture and increases the resistance of the ground plate.

at A floating body cell should be made sure that no parasitic leakage currents as well as punch-through of the selectors due to the floating Tension of the body of the selection device occur.

MOSFETs can as selection devices for Resistive memory cells are used, but at a limited current carrying capacity suffer, especially when the selection means are reduced (eg when adapting to small "ground rules").

Also Diodes can be used as selection devices. The disadvantage here is the high voltage drop over the selector itself with forward bias. Another possibility is the use of bipolar transistors with a low Emitter collector voltage drop all in forward bias and a high current carrying capacity. The problem with using bipolar devices is integration in small cell, for example 4F2 cells.

According to one embodiment The invention addresses the problem of limited current carrying capacity solved by using pickers with floating bodies in punch-through fashion. For example, you can the selection devices MOSFETs with floating body or thyristor structures with floating p and / or n regions. The selection device For example, between a ground plate and the resistive element be switched. Ie. the resistive element (memory element) can in turn be connected between the selector and the bit line.

According to one embodiment the invention, the device is turned on by a sufficient high voltage between the ground plate and the bit line (BL) is created. Select only one selector per bit line can be executed by applying an appropriate signal to the word line (WL), d. H. a voltage pulse representing the selector (e.g. a thyristor) ignites (For example, punch-through state of the floating body device).

by virtue of of the floating body is an accumulation of the charge in the body while the holding time and thus a parasitic punch-through of the selector probably. Therefore, the drain region of the floating body device for a short Time period are negatively biased to the floating body potential through a forward preloaded transition to pull down. This process can be done with a read / write cycle the cell can be combined because in this case the body potential critical to a punch-through of the device (at high voltages) to avoid.

effects of embodiments of the invention are as follows: Both conventional substrates and SOI substrates, and both planar (SOI) and vertical MOSFET selectors can be used. Both selection devices with floating body as well as selection devices with a weakly connected body can be used. According to one embodiment In the invention, the term "weakly connected" means a compound via a impoverished silicon area.

The embodiments need the invention no periodic refresh. "Refreshs" (changes the body potential) can for example, only for Bit lines used before writing processes or reading processes to eliminate the cell past. In this way the problem can be more parasitic leakage currents or punch-through states solved by applying low-level (BL) pulses before each read / write process, to eliminate the cell history.

in the Within the scope of the invention the terms "connected" and "coupled" both mean direct and indirect connection and coupling.

Claims (25)

Integrated circuit, with: - one Plurality of resistance change memory elements, and - one A plurality of memory element selection devices, wherein the selection devices Floating body select devices are. An integrated circuit according to claim 1, wherein the Selectors Field effect transistor devices or thyristor devices are. Integrated circuit according to one of claims 1 to 2, - wherein the integrated circuit comprises a plurality of bit lines and a plurality of word lines, - wherein each selection means a first terminal which is connected to one of the bit lines via a memory element, a second terminal, the is connected to one of the word lines and the body of the selector, and a third terminal connected to an area of the integrated one Circuit is connected, which is set to a fixed potential has. An integrated circuit according to claim 3, wherein each Selection device from a non-conducting state to a conducting state can be switched by a switching voltage between the first Connection and the third connection is created, and by the Voltage of the second connection set to a switching potential becomes. An integrated circuit according to claim 4, wherein the Line state a punch-through state, a line state after Occurrence of a snapback effect or a bipolar condition. Integrated circuit according to one of Claims 3 to 5, the integrated circuit having a circuit which, before memory element writes or memory element reads are performed, the potential of the floating bodysuits of all selection devices, which are connected to the same bit line sets by the first connections the selectors connected to the same bit line are set to an adjustment potential. Integrated circuit according to one of claims 1 to 6, wherein the integrated circuit has an SOI architecture. Integrated circuit according to one of claims 1 to 6, wherein the resistance change memory elements Phase change memory elements are. Integrated circuit according to one of claims 1 to 6, wherein the resistance change memory elements magnetoresistive memory elements are. Integrated circuit according to one of claims 1 to 6, wherein the resistance change memory elements programmable metallization memory elements are. Memory module with at least one integrated Circuit comprising: - one Plurality of resistance change memory elements, and - one A plurality of memory element selection devices, wherein the selection devices Floating body selectors are. The memory module of claim 11, wherein the memory module is stackable. Method for operating an integrated circuit, the plurality of resistance change memory elements and comprises a plurality of memory element selection devices, wherein the selecting means selecting means with floating Body are, the method comprising: - Produce a voltage drop over a selector such that the selector of switches a non-conducting state into a conducting state, - Read memory state, or writing the memory state of a Memory element assigned to the selector after the selector has been switched to the line state. The method of claim 13, wherein the selection means Field effect transistor devices or Thyristor devices are. The method of claim 13 or 14, wherein the conduction state a punch-through state, a conduction state after occurrence of a Snap-back effect or a bipolar condition. Method according to one of claims 13 to 15, - in which the integrated circuit has a plurality of bit lines and a Having a plurality of word lines, - wherein each selection device a first port connected to one of the bit lines via Memory element is connected to a second port, which with one of the word lines and the body of the selection device connected is, and a third terminal connected to an area of the integrated circuit, which is set to a fixed potential, is connected. The method of claim 16, wherein a selection device is switched from the non-conducting state to the conducting state, by applying a switching voltage between the first terminal and the second terminal is applied, and by the voltage of the second Connection is set to a switching potential. The method of claim 17, wherein after said selecting means was switched from the non-conductive state in the conduction state, the Voltage of the second terminal reset to a holding potential is returned to the non-conductive state without the selector to switch. Method according to one of claims 13 to 18, wherein, before a memory cell write process or a memory cell read process accomplished the potential of the floating bodys of a plurality of selection devices changed becomes. Method according to one of claims 16 to 18, wherein before a memory cell write process or memory cell read process is executed, the potential of the floating bodies of all selectors connected to the same bit line is changed. The method of claim 20, wherein the potential changed the floating bodysuits is determined by the potentials of the first terminals of the selection devices changed become. The method of claim 21, wherein the potential changed the floating bodysuits by applying a voltage pulse to the first terminals of the selectors supplied becomes. The method of claim 22, wherein the voltage pulse has a duration of 100 ps and 100 ns and a magnitude of 0.2V to 2V. Method for operating an integrated circuit, the plurality of resistance change memory elements and comprises a plurality of memory element selection devices, wherein the selecting means selecting means with floating Bodys are, the method comprising: - Produce a voltage drop over a conductive path through a memory element and a selector, which is assigned to the memory element passes through, - Determine the storage state of the memory element based on the switching behavior the selector from a resistance state to a conduction state, that results from the voltage drop. The method of claim 24, wherein the voltage drop, the over drops the conductive path, approximately 0.2V to 5V.