DE102008008144A1 - Integrated circuit for use in e.g. flash memory of electronic apparatus, has resistive storage element coupled with buried-gate-selector transistor, where information is accumulated on base of specific resistance of storage element - Google Patents

Abstract

The circuit has a storage cell including a buried-gate-selector transistor and a resistive storage element (100) that is coupled with the buried-gate-selector transistor. Resistive storage element information is accumulated on base of specific resistance of the resistive storage element. A recess is formed in an active region of the substrate, where the active region includes a source region and a drain region. The recess is arranged between the source region and the drain region, and covers a gate-oxide-layer. The resistive storage element includes a transient metal-oxide material. An independent claim is also included for a method for producing an integrated circuit.

Description

The The invention relates to an integrated circuit, a method for manufacturing an integrated circuit, a memory cell and a memory module.

storage devices are used in essentially all computer applications and many electronic Used devices. In some applications, a non-volatile Memory can be used, which stores its stored data itself then stores when there is no power. A non-volatile Memory becomes common, for example in digital cameras, portable audio players, wireless communication devices, personal digital assistants and peripherals, as well as for saving used by firmware in computers and other devices.

A size Number of different storage technologies has already been developed. Non-volatile storage technologies include flash memory, magnetoresistive random access memory (MRAM, Magnetoresistive Random Access Memory), Phase Change Multiple Access Memory (Phase Change Random Access Memory), Conductive Bridge Random Access Memory (CBRAM, Conductive Bridging Random Access Memory) and carbon storage. Because of the big one Demand for storage devices researchers are working continuously to improve storage technologies and develop new ones Types of stores, including new types of non-volatile To save.

According to one embodiment The invention provides an integrated circuit, comprising: a memory cell including a buried gate select transistor (Buried Gate Select Transistor) and one with the buried gate select transistor coupled resistive memory element, wherein the resistive Memory element based on a specific resistance of the resistive memory element stores information.

According to one embodiment has the buried gate select transistor on: a recess formed in an active area of a substrate, wherein the active region comprises a source region and a drain region wherein the recess between the source region and the Drain area arranged is a gate oxide layer that coats the recess and a gate that a conductive one Material which at least partially fills the recess.

According to one Development of the invention has the resistive memory element a transition metal oxide material on.

It can be provided that the transition metal oxide material is selected from a group consisting of NiO, TiO ₂ , HfO ₂ , ZrO ₂ , Nb ₂ O ₅ and Ta ₂ O ₅ .

Further can be provided that the resistive memory element is a switching layer which is formed by reversibly forming a conductive filament in the switching layer between a high resistance state and a low resistance state on.

According to one another embodiment The invention is a method for producing an integrated Circuitry, the method comprising: forming a Buried-gate selection transistor, and forming a resistive memory element coupled to the buried gate transistor is, wherein the resistive memory element based on a resistivity of the resistive memory element information stores.

According to one embodiment comprises forming the buried gate select transistor; Trenching in a substrate of the integrated circuit; secrete a gate oxide layer overlying the trench and depositing a trench Gates in the ditch.

The The method may include forming a source region and a drain region in the substrate.

According to one Development of the invention can be provided that the forming a source region and a drain region forming at least one from the source area and the drain region as a region coincident with a adjacent select transistor divided, in other words, shared.

The Depositing gate can be the deposition of a conductive material exhibit.

It it can be provided that the forming of the resistive memory element forming a bottom contact, forming a switching layer, and Make an upper contact.

According to one embodiment may be forming the switching layer depositing a transition metal oxide material exhibit.

According to a development of the invention it can be provided that the deposition of a transition metal oxide material has the deposition of a material that best from a group selected from NiO, TiO ₂ , HfO ₂ , ZrO ₂ , Nb ₂ O ₅ and Ta ₂ O ₅ .

According to one Another embodiment of the invention can be provided that the The method further comprises forming a bit line electrically is coupled to the resistive memory element.

According to one embodiment The invention may provide an integrated circuit, comprising: an over a buried gate select transistor formed resistive memory element, wherein the buried gate select transistor a trench formed in a substrate, a trench-covering gate oxide layer and having a trench at least partially filling gate.

According to one Further development of the invention can be provided that the resistive Memory element comprises a transition metal oxide material.

It can be provided that the resistive memory element is a switching layer which is formed by reversibly forming a conductive filament in the switching layer between a high resistance state and a Low-resistance state on.

According to one embodiment The invention may further provide a memory cell, comprising: a buried gate select transistor and one with the buried gate select transistor coupled resistive memory element, wherein the resistive memory element based on a resistivity of the resistive Memory element stores information.

According to one embodiment For example, the buried gate select transistor comprise: one formed in an active region of a substrate Well, wherein the active region has a source region and a Drain region, wherein the recess between the source region and the drain region, a gate oxide layer which deepening the depression, and a gate that is a conductive Material which at least partially fills the recess.

According to one Further development of the invention can be provided that the resistive Memory element comprises a transition metal oxide material.

The Resistive memory element may include a switching layer, the by reversibly forming a conductive filament in the switching layer a high resistance state and a low resistance state on.

According to one another embodiment According to the invention, a memory module can be provided, comprising: a plurality of integrated circuits, the integrated ones Circuits comprise a memory cell having a buried gate select transistor and a resistive coupled to the buried gate select transistor Memory element, wherein the resistive memory element the basis of a resistivity of the resistive memory element information stores.

It it may be provided that the buried gate select transistor comprising: one formed in an active region of a substrate Well, wherein the active region has a source region and a Drain region, wherein the recess between the source region and the drain region, a gate oxide layer which deepening the depression, and a gate that is a conductive Material which at least partially fills the recess.

According to one Further development of the invention can also be provided that the resistive memory element comprises a transition metal oxide material.

According to one Further development of the invention, the resistive memory element have a switching layer formed by reversibly forming a conductive Filaments in the switching layer between a high resistance state and a low resistance state switches.

In In the drawings, like reference characters generally refer to on the same parts through the different views. The painting are not necessarily scale, instead, the emphasis is generally on the principles to illustrate the invention. In the following description are different embodiments of the invention with reference to the following figures.

It demonstrate

1A and 1B a resistive memory element in which a conductive filament is formed by a transition metal oxide layer;

2A and 2 B alternative block diagram arrangements of a memory cell using a resistive memory element;

3 a resistive memory cell having a buried gate transistor according to an embodiment of the invention;

4 a schematic representation of two resistive memory cells according to an embodiment of the invention;

5 a block diagram of a method for manufacturing an integrated circuit memory device according to an embodiment of the invention;

6A to 6L Views of an integrated circuit memory device according to an embodiment of the invention in various stages of the manufacturing process, and

7A and 7B a memory module or a stackable memory module that can use memory cells according to an embodiment of the invention.

The Size of electronic devices is constantly being reduced. In memory device, conventional Technologies such as flash memory and DRAM (Dynamic Random Access Memory, dynamic multiple access memory), the information store on the basis of storing electrical charges, in the near future in terms of their size to reach their limits. additional Properties of these technologies, such as the high switching voltages and the limited number of write cycles and read cycles of Flash save, or the limited storage time of the charge state at DRAM provide additional Challenges. To explore some of these questions, explore Researchers use storage technologies to store information do not resort to storing an electrical charge.

According to some embodiments In the invention, such a technology is a resistive memory based on the bistable resistance change in transition metal oxide layers. How to later Job still explained will, can in response to the application of a corresponding voltage in certain transition metal oxide materials a trace or a conductive Filament due to thermal electronic exchange effects formed in or removed from the material. The training and remove this conductive Filaments is coupled with a thermistor effect, which is the bistable switching process due to the inhomogeneous temperature distribution in the transition metal oxide material in Response to the application of a voltage induced.

Among the transition metal chalcogenides, NiO is of particular interest for this application because of its large band gap of about 4.5 eV. At room temperature, NiO in its stoichiometric state is a good insulating semiconductor that forms its relatively large band gap by hybridization of relatively highly localized 3d electrons to O 2p electron bands. Furthermore, NiO has a region of negative differential resistance and monostable switching in the current-voltage characteristic (IU) due to the steepness of its resistance-temperature characteristic in response to the application of a suitable voltage due to the thermistor effect (σ ~ e ^{-ΔE / kT} ).

1A shows a resistive memory element 100 of the type discussed above, suitable for use in some embodiments of the invention. The resistive memory element 100 indicates: an upper contact 102 , a lower contact 104 and a transition metal oxide switching layer 106 that is between the upper contact 102 and the lower contact 104 is arranged. The transition metal oxide switching layer 106 may comprise any of a number of transition metal compounds, such as NiO, TiO ₂ , HfO ₂ , ZrO ₂ , Nb ₂ O ₅ , Ta ₂ O _5, or other suitable materials.

When via the transition metal oxide switching layer 106 a voltage above a "SET" voltage is applied, then becomes a conductive filament 114 formed in the layer, eliminating the resistive memory element 100 by drastically reducing the resistance of the transition metal oxide switching layer 106 is put into an "on" state. For example, a SET voltage of about 2 V applied across a NiO film having a thickness of between about 20 nm and about 100 nm may cause the resistance of the film to be from about 1 KΩ to 10 KΩ (depending on the thickness of the layer) falls to less than about 100 Ω.

As in 1B shown, becomes the conductive filament 114 when a "RESET" voltage across the transition metal oxide switching layer 106 is applied in the "on" state, removing the resistive memory element 100 returns to an "off" state, and the resistance of the transition metal oxide switching layer 106 is increased. The "RESET" voltage for use with a transition metal oxide layer having a NiO film may be about 1V.

To the current memory state of the resistive memory element 100 can determine a read current through the resistive memory element 100 be directed. The read current encounters high resistance when in the resistive memory element 100 no filament 114 gives, and on a low resistance, if there is a filament 114 gives. For example, a high resistance may represent a logical "0" while a lower resistance Resistor represents a logical "1", or vice versa.

2A shows an illustrative memory cell using a resistive memory element suitable for use according to some embodiments of the invention. The memory cell 200. has a select transistor 202 and a resistive memory element 204 on. The selection transistor 202 indicates: a source 206 that with a bit line 208 coupled, a drain 210 that with the memory element 204 coupled, and a gate 212 that with a word pipe 214 is coupled. The resistive memory element 204 is also with a common line 216 coupled, which may be grounded or may be coupled to other circuits, such as, for example, with circuits (not shown) for determining the resistance of the memory cell 200. for use in reading. Alternatively, in some configurations, circuitry (not shown) may be used to determine the state of the memory cell 200. while reading with the bit line 208 be coupled. It is noted that the terms "connected" and "coupled" as used herein refer to both direct and indirect connection or coupling.

To write to the memory cell becomes the word line 214 to select the cell 200. used, and a voltage is through the resistive memory element 204 on the bit line 208 applied, so that a trace or a filament in the resistive memory element 204 is formed or removed, whereby the resistance of the resistive memory element 204 will be changed. Similarly, when reading the cell 200. the word line 214 to select the cell 200. used, and the bit line 208 is used to apply a read voltage across the resistive memory element 204 for measuring the resistance of the resistive memory element 204 used.

The memory cell 200. may be referred to as a 1T1J cell because it has a transistor and a memory transition (the resistive memory element 204 ) used. Typically, a storage device comprises an array of many such cells. It should be noted that in a resistive memory element, other configurations for a 1T1J memory cell or other configurations than a 1T1J configuration may be used. For example, in 2 B an alternative arrangement for a 1T1J memory cell 250 in which a selection transistor 252 and a resistive memory element 254 in terms of in 2A have been repositioned.

In the in 2 B illustrated alternative configuration is the resistive memory element 254 with a bit line 258 and a source port 256 the selection transistor 252 coupled. A drain connection 260 the selection transistor 252 is with a common line 266 coupled, which may be grounded, or may be coupled to other (not shown) circuits, as described above. A gate 262 the selection transistor 252 is from a word line 267 controlled.

A The challenge with storage technologies is the limited packing density of memory cells. An increase the packing density increased the number of memory cells on a single device can be placed and increased thus the amount of data that the device can store. In general For example, the packing density can be reduced by decreasing the size of the memory cells elevated become. To cope with the increasing demand for storage devices high capacity Satisfy the use of memory cells with scaling dimensions below 50 nm desirable be.

For TMO memory cells, As described above, the storage element itself can be made to a diameter be scaled down in the range of 15 nm to 20 nm. In the event of an integration into a memory cell with a selection transistor (as shown above) or a diode, however, this advantage becomes due to the dimensions of the transistor or diode and the Restricted integration schemes.

According to some embodiments The invention may be the size of a Memory cell using a TMO memory element by combining of the TMO memory element with a select transistor having a three-dimensional Channel and a buried gate, can be reduced. This combination can significantly reduce the dimensions of the memory cells, wherein the possibility of a increased Density is provided. Furthermore, the use of a such buried gate select transistor in some embodiments of the invention the process scheme for the deposition of the TMO switching layer and simplify the subsequent integration.

3 shows a memory cell according to some embodiments of the invention. A memory cell 300 has a buried gate select transistor 302 on, with a source 304 a drain 306 , a gate oxide layer 308 and a gate 310 (which also serves as a word conduit). The drain area 306 is with a lower contact 312 coupled with a switching layer 314 is coupled. An upper contact 316 is above the switching layer 314 arranged, and is with a bit line 318 coupled. The source area 304 is with a common line 320 coupled.

The buried gate select transistor 302 is in a depression 322 in a surface of an active area of a substrate 324 trained, the source area 304 and the drain area 306 having. The gate oxide layer 308 is designed to be the recess 322 covers, and the gate 310 fills the depression 322 at least partially. The gate oxide layer 308 has an insulating material such as SiO ₂ and the gate 310 is formed of a conductive material, such as tungsten (W), although other conductive materials may be used.

The switching layer 314 may be a TMO layer as described above. Alternatively, the switching layer 314 other materials for forming a memory element that stores information by changing the resistance or the conductivity of the memory element. Examples of such resistive memory technologies include Conductive Bridging Random Access Memory (CBRAM), Phase Change Random Access Memory (PCRAM), Magneto-Resistive Random Access Memory (MRAM), and Memory based on changes in resistance in carbon layers.

The use of the buried gate select transistor 302 allows the size of the memory cell to be reduced, thereby increasing the density of memory cells on an integrated circuit memory device made in accordance with an embodiment of the invention.

The average size of a cell can be further reduced by arranging the cells so that the selection transistors of at least two adjacent cells share a source region or a drain region. 4 shows a schematic representation of the switching scheme for such an arrangement in which the selection transistors in two adjacent cells share a source region.

As can be seen, has a memory cell 402 a transistor 404 with a source connection 406 , a drain connection 412 and a gate 410 on. The memory cell 402 further includes: a resistive memory element 412 , such as a TMO-based resistive memory element as described above, or another type of resistive element. The gate 410 of the transistor 404 is with a word line 414 coupled. The drain connection 408 of the transistor 404 is with the resistive memory element 412 coupled with a bit line 416 is coupled. The source connection 406 of the transistor 404 is with a common line 418 coupled.

In an adjacent memory cell 422 there is a similar resistive memory element 432 , as well as a transistor 424 that has a source connection 426 , a drain connection 428 and a gate terminal 430 having. The gate connection 430 of the transistor 424 is with a word line 434 coupled. The drain connection 428 of the transistor 424 is with the resistive memory element 432 coupled with the bit line 416 is coupled. The source connection 426 of the transistor 424 is with the common line 418 coupled.

Because the source connection 406 of the transistor 404 and the source port 426 of the transistor 424 both with the common line 418 coupled, the transistors can 404 and 424 in some embodiments share a common source port. This common source terminal can be implemented in an integrated circuit by providing a common source region for the two adjacent transistors, thereby reducing the average size of the transistors and the memory cells to which they belong.

5 FIG. 12 shows a high level flowchart of a method of fabricating an integrated circuit having a memory cell as described above in accordance with an embodiment of the invention. With reference to 5 described method is for the manufacture of an integrated circuit comprising cells, as described above with reference to 4 however, a similar method of fabricating cells with other arrangements could be used.

In step 502 For example, shallow trench isolation (STI) trenches are formed in a substrate on which a layer of nitride such as silicon nitride (Si ₃ N ₄ ) has been formed. The formation of the STI trenches is done using known techniques, for example by etching. The trenches are filled with an insulating material, such as SiO ₂ . Subsequently, the insulating material is planarized, for example, by known chemical mechanical planarization (CMP) techniques.

In step 504 the buried gate select transistor is formed. This is done by forming a trench, for example by means of lithographic techniques and by means of reactive ion etching (RIE, Reactive Ion Etching) Other known methods of forming a trench could be used in the Si ₃ N ₄ layer and the substrate. Once the trench has been formed, a gate oxide layer is grown comprising a material, such as SiO ₂ , that covers the trench and lies below the Si ₃ N ₄ layer, in other words, lower than the Si ₃ N ₄ layer. Over the gate oxide layer, a gate is formed of a conductive material, such as tungsten (W). This can be done, for example, by chemical vapor deposition (CVD) of a layer of W, followed by planarization (for example by CMP) of the W layer. As described above, the gate may also serve as a word line.

Once the gate has been formed, it can be easily recessed, for example, by RIE. The recess thus formed is filled with an insulating material such as SiO ₂ , with gate and oxide layer buried. Subsequently, the insulating material is planarized, for example, by means of a CMP process.

In step 506 a source and drain implantation is performed. First, the Si ₃ N _{4 is removed,} for example, by means of hot phosphoric acid. In an n-channel device, source regions and drain regions are formed by n ⁺ implantation, for example by doping with arsenic (As), or by p ⁺ in a p-channel device, for example by doping with boron (B) to an ion concentration of about 10 ¹⁵ / cm ² . Subsequently, a mask is applied to the surface, except over a contact region for the drain region. This contact region is opened by removing the SiO ₂ over the contact region, for example by means of an etching technique such as RIE.

In step 508 For example, the common line attached to the source of the buried gate select transistor (as well as the source of the buried gate select transistor of at least one adjacent cell) is formed over the STI trench. This can be done by applying a mask and removing some of the resistive material (eg SiO ₂ ) from the STI trench, for example by RIE. A selective silicon epitaxy over the STI may then be used to form a conductive silicon common source line in the STI trench.

Alternatively, the common source line may be formed by forming a recess in the STI trench and depositing conductive poly-silicon in the recess. Subsequently, the poly-silicon is planarized, for example, by means of CMP. An oxide layer (eg, SiO ₂ ) may be deposited over the common poly-silicon source line.

In step 510 For example, the lower contact for the resistive memory element is formed over the drain portion of the buried gate select transistor. The lower contact may be formed of poly-silicon or other conductive materials. The lower contact can be formed by means of a strip mask, which runs parallel to the intended direction of the bit lines. Subsequently, conductive poly-silicon is deposited to form the lower contacts. Then, in preparation for the next step, a Si ₃ N ₄ hard mask is applied.

In step 512 Isolation trenches are formed, which separate adjacent cell pairs from each other. The isolation trenches may be formed using a mask to determine the locations of the isolation trenches and then etch the isolation trenches using known etching techniques. An insulating material, such as SiO ₂ , is then deposited to fill the isolation trenches and planarized (eg, by CMP) to the plane of the Si ₃ N ₄ deposited in the previous step. Subsequently, the Si ₃ N ₄ can be removed, for example, by means of hot phosphoric acid.

In step 514 the memory layer stack of the resistive memory element is formed. This can be done by forming a switching layer which stores information based on the resistance of the switching layer. For a TMO resistive memory element according to an embodiment of the invention, the switching layer comprises a TMO material such as NiO, TiO ₂ , HfO ₂ , ZrO ₂ , NB ₂ O ₅ , Ta ₂ O _5, or other suitable material or consists of such. This material is deposited by reactive DC sputtering, MF sputtering or RF sputtering of a metal target (or compound target) in an Ar / oxygen mixture or a pure Ar working gas. A pressure of about 3 mbar to 5 mbar and a sputtering power with a power density of about 2 W / cm ² to 3.5 W / cm ² can be used for depositing such TMO materials.

Subsequently, an upper contact is deposited over the switching layer. The upper contact may be formed of a conductive material such as platinum (Pt), palladium (Pd), titanium (Ti) or other metallic or non-metallic conductors. In general, metals such as Pt, Pd or Ti may be deposited by DC sputtering in an Ar working gas at pressures and outputs similar to those used to deposit the TMO switching layer the.

The memory layer stack is then formed using, for example, a tantalum nitride (TaN) hardmask that can be patterned using a resist mask. Once corresponding areas of the memory layer stack have been masked, unwanted material can be etched down onto the SiO ₂ which has been deposited by RIE for the example above.

In step 516 For example, bit lines and bit line contacts are formed over the memory layer stack. To accomplish this, a relatively thick layer of SiO _{2 is} deposited over the device (for example, by CVD). Subsequently, a resist mask is applied for positioning the bit line contact holes. The via holes are etched and filled with a conductive material such as titanium (Ti), titanium nitrate (TiN), or tungsten (W), although other metals or conductive materials may be used. The SiO ₂ layer and the conductive material filling the contact holes are then planarized by, for example, CMP. Subsequently, a conductive material such as W is deposited and patterned, for example, by means of a resist mask and RIE, so that bit lines are formed.

Even though in the method described above, the use of special Techniques such as RIE for etching or CMP for planarizing It is noted that there are other well known Ways to perform the same or similar There are processes. For example, there are a variety of known techniques for etching. The above specific techniques are intended merely as examples serve, and others currently known or developed in the future Techniques can also to perform the same processes or similar Processes are used.

In the following figures, views of the integrated circuit are shown after numerous intermediate steps of the process described above. In 6A FIG. 12 is an integrated circuit memory device according to an embodiment of the invention after depositing an Si ₃ N ₄ layer. FIG 602 on a substrate 604 and the etching and filling of the STI trenches 606 with a resistive material 608 as in step 502 described, shown.

6B shows a buried gate select transistor 610 after step 504 , The buried gate select transistor 610 is in a ditch 612 in the substrate 604 educated. The ditch 612 is formed for example by means of lithographic techniques and by reactive ion etching (RIE), although other known methods for forming a trench in the Si ₃ N ₄ layer 602 and the substrate 604 could be used. Subsequently, a gate oxide layer 614 formed of a material such as SiO ₂ , for example, by means of conventional thermal processes for oxide growth. Alternatively, the gate oxide layer 614 be deposited. Over the gate oxide layer 614 is a gate 616 made of a conductive material, such as tungsten (W). The gate material can also serve as a word line.

The gate 616 is easily deepened, for example, by the application of RIE. The recess thus formed is coated with an insulating material 618 , such as SiO ₂ , where the gate 616 and the oxide layer 614 to be burried. The insulating material 618 is planarized, for example, by means of a CMP process.

6C shows the buried gate select transistor 610 during the step 506 , In 6C became the Si ₃ N ₄ layer 602 removed by means of hot phosphoric acid, wherein the insulating material 618 was left behind. In addition, by N ⁺ implantation, a source region 622 and a drain area 643 educated.

Next is the insulating material 618 , as in 6D shown leveled by wet etching techniques. As in 6E shown, becomes a mask 628 applied to the surface, except over a contact area 630 for the drain area. The contact area 630 is by removing the SiO ₂ over the contact area 630 for example, by means of an etching technique, such as RIE.

6F shows forming a common source line 632 over an STI trench 606 as in step 508 described. This common source line 632 is electrical to the source region 622 as well as a source area 634 a select transistor of an adjacent cell (not shown). In one embodiment, the common source line becomes 632 by applying a mask (not shown) and by removing part of the resistive material 608 (for example, SiO ₂ ) from the STI trench 606 formed for example by RIE. Subsequently, a silicon epitaxy is formed over the STI to form the silicon common source conductive line 632 in the STI trench 606 used.

As in 6G may represent a common source line by forming a recess in the STI trench 606 and depositing a layer of conductive poly-silicon 638 in the depression and over an oxide layer 637 educated become. As in 6H shown, the poly-silicon 638 planarized, for example, by CMP, and an oxide layer 640 (For example, SiO ₂ ) is above the poly-silicon 638 deposited. In an alternative in 6G and 6H illustrated embodiment, the poly-silicon is used 638 as the common source line.

6I shows a lower contact 642 for the resistive memory, which is above the drain area 624 of the buried gate select transistor 610 is formed, as in step above 510 described. The lower contact 624 may be formed of poly-silicon or other conductive materials.

6J shows the integrated circuit after step 512 , being an isolation trench 646 is formed. The isolation ditch 646 can be formed by known mask techniques and etching techniques. The isolation ditch 646 is filled with an insulating material such as SiO ₂ .

In 6K the integrated circuit is shown after forming the memory layer stack, as in step above 514 described. A switching layer 650 will be above the bottom contact 642 deposited. In some embodiments, the switching layer 650 a TMO material such as NiO, TiO ₂ , HfO ₂ , ZrO ₂ , Nb ₂ O ₅ , Ta ₂ O ₅ or other suitable material.

An upper contact 652 gets over the switching layer 650 deposited. The upper contact 652 may be formed of a conductive material such as platinum (Pt), palladium (Pd), titanium (Ti), or other metallic or non-metallic conductors. Masking and downsizing on the SiO ₂ are used to shape the storage layer stack.

6L shows bit lines and bit line contacts which, as in step 516 described above the memory layer stack are formed. An SiO ₂ layer 660 is deposited over the device, and masking and etching are used to form contact holes 662 applied. The contact holes 662 are filled with a conductive material such as titanium (Ti), titanium nitrate (TiN) or tungsten (W), although other metals or conductive materials may be used. Above the contact holes is a bit line 664 educated. The bit line 664 has a conductive material such as W.

Memory cells, such as the memory cells described above, can be used in memory devices containing large numbers of such cells. These cells may, for example, be arranged in an array of memory cells having numerous rows and columns of cells, each storing one or more bits of information. Memory devices of this type can be used in a variety of applications or systems. As in 7A and in 7B In some embodiments, memory devices such as those described herein may be used in modules. In 7A is a memory module 700 illustrated on which one or more storage devices 704 on a substrate 702 are arranged. Every storage device 704 may include numerous memory cells according to an embodiment of the invention. The memory module 700 may also include one or more electronic devices 706 comprising one or more memories, one or more processing circuits, one or more control circuits, one or more addressing circuits, one or more bus connection circuits, or one or more other circuits or electronic devices mounted on a module having a memory device 704 can be combined. Furthermore, the memory module 700 several electrical connections 708 on, connecting to the memory module 700 can be used on other electronic components including other modules.

As in 7B In some embodiments, these modules may be stackable to form a stack 750 form. A stackable memory module 752 For example, one or more storage devices 756 have, arranged on a stackable substrate 754 , Each of the storage devices 756 includes memory cells using memory elements according to one embodiment of the invention. The stackable memory module 752 may also include one or more electronic devices 758 comprising one or more memories, one or more processing circuits, one or more control circuits, one or more addressing circuits, one or more bus binding circuits, or one or more other circuits or electronic devices mounted on a module having a memory device 756 can be combined. Electrical connections 760 are used to connect the stackable memory module 752 to other modules in the stack 750 or to other electronic devices. Other modules in the stack 750 may include additional stackable memory modules, similar to the stackable memory module described above 752 , or other types of stackable modules, such as stackable processing modules, control modules, communication modules or other modules having electronic components.

While the Invention in particular with reference to particular embodiments As shown and described, one of ordinary skill in the art should recognize that many changes in form and details can be carried out without thereby departing from the spirit and scope of the invention, as defined by the appended claims is. The scope of the invention is thus described by the appended claims, and any changes, relating to the meaning and scope of the claims, are included for this reason.

Claims (25)

Integrated circuit, comprising: a Memory cell having a buried gate select transistor and one with the buried gate select transistor coupled resistive memory element, wherein the resistive memory element based on the resistivity of the resistive memory element Information stores. Integrated circuit according to claim 1, the Buried gate select transistor having: • one depression formed in an active region of a substrate, wherein the active region comprises a source region and a drain region wherein the recess between the source region and the drain region is arranged • one Gate oxide layer that covers the recess, and • a gate, that a conductive Material which at least partially fills the recess. An integrated circuit according to claim 1 or 2, wherein the resistive memory element comprises a transition metal oxide material. The integrated circuit of claim 3, wherein the transition metal oxide material is selected from the group consisting of NiO, TiO ₂ , HfO ₂ , ZrO ₂ , Nb ₂ O ₅ and Ta ₂ O ₅ . Integrated circuit according to one of Claims 1 to 4, wherein the resistive memory element has a switching layer, by reversibly forming a conductive filament in the switching layer between a high resistance state and a low resistance state. Method of manufacturing an integrated circuit, in which the method comprises: • Form a buried gate select transistor, and • Form a resistive memory element connected to the buried gate transistor coupled, wherein the resistive memory element based on the resistivity of the resistive memory element information stores. Method according to claim 6 wherein forming the buried gate select transistor having: • Form a trench in a substrate of the integrated circuit; • Separate a gate oxide layer overlying the trench, and • Separate a gate in the ditch. Method according to claim 7, further forming a source region and a drain region in the substrate having. Method according to claim 8, wherein forming a source region and a drain region comprises forming of at least one of the source region and the drain region as one Area which is connected to an adjacent selection transistor is shared. Method according to claim 7 or 8, wherein depositing the gate comprises depositing a conductive material having. Method according to one the claims 6 to 10, wherein forming the resistive memory element comprises: • Form a lower contact; • Form a switching layer, and • Form an upper contact. Method according to claim 11, wherein forming the switching layer comprises depositing a transition metal oxide material having. The method of claim 12, wherein depositing a transition metal oxide material comprises depositing a material selected from a group consisting of NiO, TiO ₂ , HfO ₂ , ZrO ₂ , Nb ₂ O _5, and Ta ₂ O ₅ . Method according to one the claims 6-13, further comprising forming a bit line electrically is coupled to the resistive memory element. Integrated circuit, comprising: • one above one Buried gate select transistor formed resistive memory element, Wherein the buried gate select transistor a trench formed in a substrate, a trench covering the trench Gate oxide layer and at least partially filling the trench Gate has. An integrated circuit according to claim 15, wherein the resistive Memory element, a transition metal oxide material having. An integrated circuit according to claim 15 or 16, wherein the resistive memory element comprises a switching layer, the by reversibly forming a conductive filament in the switching layer between a high resistance state and a low resistance state. Memory cell, comprising: a buried gate select transistor and a resistive coupled to the buried gate select transistor Memory element, wherein the resistive memory element based on a resistivity of the resistive memory element information stores. Memory cell according to claim 18, the Buried gate select transistor having: • one formed in an active region of a substrate recess, wherein the active region has a source region and a drain region wherein the recess between the source region and the Drain area is arranged A gate oxide layer, the deepening the depression, and • one Gate, which is a conductive Material which at least partially fills the recess. A memory cell according to claim 18, wherein the resistive Memory element, a transition metal oxide material having. A memory cell according to claim 18, wherein the resistive Memory element has a switching layer by reversible Forming a conductive Filaments in the switching layer between a high resistance state and a low resistance state on. Memory module, comprising: a plurality of integrated circuits, the integrated circuits a memory cell having a buried gate select transistor and a resistive coupled to the buried gate select transistor Memory element, wherein the resistive memory element on the Basis of a resistivity of the resistive memory element Information stores. Memory module according to claim 22, the Buried gate select transistor having: • one formed in an active region of a substrate recess, wherein the active region has a source region and a drain region wherein the recess between the source region and the Drain area is arranged A gate oxide layer, the deepening the depression, and • one Gate, which is a conductive Material which at least partially fills the recess. A memory module according to claim 22 or 23, wherein the resistive memory element comprises a transition metal oxide material. Memory module according to one of claims 22 to 24, wherein the resistive memory element has a switching layer, by reversibly forming a conductive filament in the switching layer between a high resistance state and a low resistance state.