DE102008007543B3 - Stack of chips has multiple semiconductor chips arranged on one another, where each semiconductor chip has upper side, lower side and lateral surface encircling border of upper and lower sides - Google Patents

Abstract

The stack of chips has multiple semiconductor chips arranged on one another. Each semiconductor chip (100) has an upper side (110), a lower side and a lateral surface (120) encircling a border of the upper and lower sides. The lateral surface is formed by a metallic material in a form of a layer, which encircles a semiconductor chip. An independent claim is included for a manufacturing method for a semiconductor chip.

Description

The The present invention relates to a multi-stacked stack of chips arranged semiconductor chips. The invention further relates to a Method for producing a semiconductor chip.

microelectronic Semiconductor devices with integrated circuits form today the basis for electronic applications of all kinds. These components have a complex arrangement of electronic structures which are supported on carrier substrates, so-called "chips" or "semiconductor chips" interconnected are. As part of the production of semiconductor chips are the electronic Structures first together on a substrate wafer referred to as "wafer" produced. By a subsequent separation process, which For example, a sawing and a thinning process performed on the wafer covers are single unhoused Chips, also known as "die", won. For further training of Hableiterbauelemente be the occasional chips usually in a corresponding housing accommodated. It can the chips also in the form of a so-called chip stack ("chip stack", "chip package", "3D chip sandwich arrangement") on top of each other to be ordered.

A The main objectives of the semiconductor industry is the steady increase in performance through ever faster circuits, which is linked with a continuous reduction of electronic structures. The increase in data rates and performance due to the increase in performance Signal densities, however, have the consequence that electrophysical properties of semiconductor chips and chip stacks such as in particular the EMC behavior (Electromagnetic compatibility) and thermal behavior is becoming increasingly important. For memory modules such as Dynamic Random Access Memory (DRAM) are for Example the clock rate or switching time and the signal rise time decisive parameters on the basis of which the performance to judge. At a clock rate of more than 1 GHz and a switching time of more than 3 ns, a DRAM device can be classified as a "high-speed circuit", in which the above-mentioned electrophysical properties in come to the fore.

Under electromagnetic compatibility (EMC) becomes the ability a device or a system understood in an electromagnetic environment to work satisfactorily without even electromagnetic disorders causing the functioning of others in the environment Could affect devices or systems. Examples of such disorders are electromagnetic interference (EMI, Electromagnetic Interference) or high-frequency interference (RFI, Radio Frequency Interference).

at a stack of chips are usually different electrical and electronic structures such as memory cell arrays, Tracks, vias ("via"), redistribution layers, "Power Planes ", etc. on top of each other arranged. The higher are the clock frequencies used in the transmission of signals, the bigger it is the mutual influence of these structures and devices in the vicinity of the chip stack due to electromagnetic Fields, which during signal transmission occur. Although will be present In semiconductor chips, precautions are taken to improve EMC performance to improve. This includes, for example, the use of impedance-defined Conductor structures, the use of ground planes and layers as well as a Termination of signal lines. With regard to future high-frequency applications encounter such Activities, which are also associated with a space requirement on the chips, however to their limits. There is therefore the problem that a reliable signal transmission not complete anymore guaranteed is.

One further limiting factor, which at high signal frequencies or clock rates is becoming increasingly important, is the thermal warming during operation of the semiconductor chips. At present, semiconductor chips are used and / or chip stacks active and passive heat sinks and surfaces used. On this way, a more homogeneous temperature distribution can be achieved and an excess amount of heat by heat conduction, thermal radiation and convection are dissipated to the environment. The development of ever more powerful However, systems with increasing integration densities, despite such cooling measures more and more problems with the regulation of thermal behavior. About that In addition, the use of heat sinks consuming and takes on the chips in particular a "valuable" lateral area to complete, which due to the required increasingly compact dimensions less and less to disposal stands.

One Another problem is mechanical damage to the semiconductor chips at the edges which in the processing of the chips after separation as well can occur in the production of chip stacks. Such damage can in particular to cracks into the active areas of the semiconductor chips to lead, what a destruction of the affected chip or chip stack.

The US 2006/0128119 A1 describes a semiconductor chip and a method of making the same ment, wherein a circumferential lateral surface of the semiconductor chip has a metallic layer.

Another semiconductor chip with a metallic sheath and an associated manufacturing method are known from the DE 10 2006 033 319 A1 known.

The US 2006/0043533 A1 describes the production of plated-through holes in semiconductor chips, by means of which the semiconductor chips can be contacted with one another in a chip stack.

From the US 2002/0047199 A1 For example, a semiconductor chip with a wiring at one side edge is known. Further described is a method for producing such a semiconductor chip and a chip stack composed of a plurality of chips.

The Object of the present invention is to provide an improved To provide chip stack, in which avoided the disadvantages described above become. It is another object of the invention to provide a method for Produce an improved semiconductor chip specify.

These The object is achieved by a chip stack according to claim 1 and a method according to claim 8 solved. Further advantageous embodiments of the invention are in the dependent claims specified.

According to the invention is a Chip stack proposed in which a plurality of semiconductor chips on top of each other are arranged. Each semiconductor chip has an upper side and a Bottom and one adjacent to the top and bottom circumferential lateral surface on, which is formed by a metallic material.

These Design of the lateral surface a semiconductor chip provides a simple and space-saving measure Improvement and control of the EMC behavior. By the metallic Material can on the one hand on the semiconductor chip from the outside acting electromagnetic Fields and on the other hand from the semiconductor chip outgoing electromagnetic Fields with a high reliability be shielded.

Furthermore allows the metallic material of the lateral surface an improvement of the thermal Behavior of the semiconductor chip. Thus, during operation of the semiconductor chip resulting amount of heat forwarded to the edge of the semiconductor chip or the metallic material which causes the temperature on the semiconductor chip to drop. outgoing from the lateral surface can the amount of heat continue be delivered to the environment. That at the edge of the semiconductor chip arranged metallic material takes no valuable place on the top of the semiconductor chip to complete.

By the metallic material of the lateral surface, the semiconductor chip also opposite mechanical stresses or damage are protected. In this way, the handling of the semiconductor chip designed while a processing uncritical and cracks in the semiconductor chip, by which the semiconductor chip fails for further use avoided.

The invention rotates metallic material the semiconductor chip. Such around the semiconductor chip arranged around metallic material allows a high EMC protection of the semiconductor chip. Also, such an embodiment offers the Advantage of effective heat spreading and heat dissipation the environment of the semiconductor chip. In addition, the semiconductor chip with a circulating metallic material a high mechanical stability on.

This is according to the invention metallic material formed in the form of a layer. The thickness of the layer can depend on the desired function in the foreground are selected. For one Improving the EMC properties can already be relatively small Layer thicknesses are sufficient, whereas by larger layer thicknesses a higher one mechanical stability achieve. A possible Layer thickness for the metallic material is for example in the micron range.

According to one another embodiment According to the invention, the metallic material comprises at least one element the group silver, aluminum, gold, copper, nickel, tin on.

According to one another preferred embodiment the invention, the metallic material is a metal or a Alloy up.

According to one another preferred embodiment the invention is the metallic material by a solder paste, a polymer conductive paste or a conductive adhesive is formed.

According to one another preferred embodiment According to the invention, the semiconductor chip has one with the metallic one Material of the lateral surface connected device, such as a trace, for transmitting a quantity of heat to the metallic material. In this way, a in the operation of the Semiconductor chips in one place resulting high amount of heat reliable and transported quickly to the metallic material of the lateral surface become.

With regard to the chip stack according to the invention, the advantages can be summarized as follows:
The chip stack has an effective EMC protection, since the metallic material of the lateral surfaces of the semiconductor chips both an electromagnetic interference of the semiconductor chips of the stack and a radiation of noise, by which devices or systems could be affected outside the chip stack, restricted or suppressed , The metallic material of the lateral surfaces also favors the thermal properties and causes a high mechanical stability of the semiconductor chips, whereby, for example, the handling of the chips in the context of the production of the chip stack designed uncritical.

According to one preferred embodiment of Invention is the metallic material of the lateral surfaces of individual semiconductor chips conductively connected to each other. To this Way, a homogeneous heat distribution and delivery of the entire chip stack achieved and the EMC protection be further improved.

According to the invention is further a method for producing a semiconductor chip is proposed, which providing a semiconductor substrate, forming a first recess in a top surface of the semiconductor substrate, and introducing a metallic material into the first recess includes. The method further comprises forming a second one Recess in the top of the semiconductor substrate, creating a lateral structure of a semiconductor chip set and a part of the metallic material is removed such that an inner sidewall the second recess comprises the metallic material. following becomes substrate material on a lower surface of the semiconductor substrate removed to at least the second recess, so that a isolated semiconductor chip with a metallic material at one the peripheral surface of the semiconductor chip is formed.

The inventive method offers an easy way a semiconductor chip having at least a portion thereof Form metallic material formed lateral surface. With such lateral surface can the advantages described above with regard to the EMC behavior and the thermal and mechanical properties of the semiconductor chip be achieved.

According to one preferred embodiment of Invention is a width of the second recess smaller than a Width of the first well. In this way, several can be isolated semiconductor chips with a metallic material having lateral surface Produce with a relatively low cost, since that in a depression introduced metallic material on several juxtaposed Semiconductor chips can be "distributed".

According to one another preferred embodiment the invention, the metallic material is in the first Inserted recess that the first recess completely with filled with the metallic material becomes. Furthermore, a depth of the second recess is preferable smaller than a depth of the first pit.

According to one another preferred embodiment of the invention have both the first recess and the second Deepening in the plan view of the top of the semiconductor substrate a circumferential shape. The second depression is within formed the first recess, so that all the inner side walls of second recess having the metallic material. Consequently is the metallic material in the isolated semiconductor chip arranged around the semiconductor chip, whereby the semiconductor chip a high EMC protection, an effective thermal behavior and a high mechanical stability having.

According to one another preferred embodiment the invention, the introduction of the metallic material in the first depression was carried out by means of a galvanization process. A An alternative to this is to carry out a sputtering process. About that In addition, the introduction of the metallic material in the first recess also be done using a screen printing process.

According to one another preferred embodiment The invention is the formation of the first recess and / or the formation of the second recess by means of a mechanical Sawing process. Alternatively, it is possible to for forming the first and / or the second recess, a plasma etching process or perform a laser process.

The The invention will be explained in more detail below with reference to FIGS. It is, however, on it indicated that the figures represent only typical embodiments and therefore, do not limit the scope of the invention. The invention may others as well effective embodiments include. Show it:

1 a schematic perspective view of a semiconductor chip with a lateral surface of a metallic material according to an embodiment;

2 to 6 schematic lateral sectional views of a semiconductor substrate for Illustrating steps of a method of manufacturing semiconductor chips according to an embodiment;

7 to 10 the 2 to 6 corresponding schematic plan views of the semiconductor substrate in the manufacture of the semiconductor chips;

11 a schematic sectional side view of a chip stack according to an embodiment; and

12 a schematic sectional side view of a chip stack according to another embodiment.

The explained with reference to the figures embodiments based on the circumferential surface of a semiconductor chip, which up to now hardly attached any importance in the design of chips was made, at least in part, of a metallic material train to specific electrophysical and / or mechanical To achieve properties. The term "lateral surface" should hereby be synonymous for the peripheral edge surface or the peripheral edge (area) of a semiconductor chip. The lateral surface, which connects a top and a bottom of a semiconductor chip, is made up of all Sidewalls of the concerned semiconductor chips together.

Of the Expression "metallic Material "should be on all Obtain materials that have metallic properties. Such properties include in particular a high electrical conductivity as well as a high thermal conductivity. Therefore, both metals containing materials come into consideration as well as materials without a metal content. Examples of possible Materials are given below.

1 shows a schematic perspective view of a semiconductor chip 100 according to one embodiment. The semiconductor chip 100 , which may be a memory chip such as a DRAM chip or a logic or processor chip, has an upper surface 110 one substantially parallel to the top 110 arranged lower side and one at the top 110 and the bottom adjacent circumferential surface 120 on. The entire lateral surface 120 has a metallic material in the form of a layer, which the semiconductor chip 100 circulates. The thickness of the layer, which can be selected as a function of a desired electrophysical and / or mechanical function, is for example in the μm range.

The metallic material of the lateral surface 120 allows effective shielding of the semiconductor chip 100 from outside acting electromagnetic signals or fields and / or fields, which of the semiconductor chip 100 be sent out and therefore the environment of the semiconductor chip 100 could disturb. In this way, the EMC behavior of the semiconductor chip 100 be optimized or controlled with a relatively low cost. This takes on the edge of the semiconductor chip 100 arranged metallic material no valuable space on the top 110 of the semiconductor chip 100 to complete.

Due to the metallic material is the lateral surface 120 particularly suitable for shielding radiofrequency electromagnetic fields and thereby suppressing interference caused. In this case, for example, interference with a frequency of more than 1 GHz come into consideration. At such frequencies can be already with relatively thin layer thicknesses of the metallic material of the lateral surface 120 , which deviate from the above-mentioned micron range, for example, in the submicrometer range, achieve effective EMC protection.

The metallic material of the lateral surface 120 also causes an improvement in the thermal performance of the semiconductor chip 100 , One during operation of the semiconductor chip 100 The resulting amount of heat is in this case of the "hot" positions of the semiconductor chip 100 to the lateral surface 120 directed. The metallic material of the lateral surface 120 represents as a "flat band" around the semiconductor chip 100 an additional heat capacity is available and therefore acts as a heat sink ("heat sink") due to the distribution of the amount of heat on the semiconductor chip 100 circumferential lateral surface 120 what is also referred to as heat spreading may be the temperature of the semiconductor chip 100 or on its top 110 reduced and a more homogeneous temperature distribution can be achieved. Starting from the lateral surface 120 the amount of heat absorbed by further example, heat radiation and convection to the environment of the semiconductor chip 100 delivered what is in 1 indicated by arrows. Such an effective thermal behavior of the semiconductor chip 100 can with a layer thickness of the metallic material of the lateral surface 120 in the micron range, for example in a range between 5 to 20 microns can be achieved.

To one at a point of the semiconductor chip 100 local amount of heat as quickly as possible and targeted to the lateral surface 120 can transport on the semiconductor chip 100 optionally a corresponding device for forwarding the amount of heat to the lateral surface 120 be provided. This is schematically in 1 on the basis of the top 110 arranged conductor tracks 140 illustrates which with the metallic material of the lateral surface 120 are connected and therefore a quantity of heat from a heat source 130 can transfer to the metallic material. The tracks 140 , which are also referred to as so-called "heat pipes", have a thermally highly conductive material such as copper or aluminum instead of the conductor tracks 140 on the top 110 The tracks can also be integrated into the top 110 or within the semiconductor chip 100 and / or be formed on the bottom. Also, the semiconductor chip 100 instead of a single heat source 130 have a plurality of heat sources, which thermally via corresponding heat conductors to the lateral surface 120 are coupled (not shown).

The metallic material of the lateral surface 120 of the semiconductor chip 100 In addition to the improvement of the EMC behavior and the thermal properties, this increases the mechanical stability. In this way, the semiconductor chip 100 protected against mechanical stresses or damage in the edge region, resulting in the handling of the semiconductor chip 100 made more uncritical in the context of processing. In particular, by the metallic material of the lateral surface 120 the formation of cracks from the edge region into the semiconductor chip 100 in, through which the semiconductor chip 100 is destroyed, avoided. Reliable mechanical stability can already be achieved with the abovementioned layer thickness of the metallic material in the μm range. Provided the mechanical stability of the semiconductor chip 100 can be further increased, larger layer thicknesses, for example, several 100 microns can be provided for the metallic material.

For the lateral surface 120 of the semiconductor chip 100 come in a variety of materials and configurations into consideration. For example, the metallic material in the form of a pure metal or an alloy at the edge of the semiconductor chip 100 available. In addition, the metallic material of the lateral surface 120 also be formed by a Polymerleitpaste or a conductive plastic or a conductive adhesive, which are cured. Such substances may comprise a "matrix material" in which a multiplicity of metallic particles are contained 120 may also be formed in the form of a molten and cured solder paste. As a metal or metallic component for these different embodiments, for example, silver, aluminum, gold, copper, nickel and / or tin can be used.

alternative is the possibility given to use materials that do not have metal, but by metallic properties like in particular one high electrical conductivity or a high thermal conductivity distinguished. This includes, for example, carbon comprehensive Materials as well as polymer compounds or polymer conductive pastes and conductive Adhesives.

The following 2 to 6 show schematic lateral sectional views of a semiconductor substrate 200. to illustrate steps of a simple process for the production of semiconductor chips 250 with a lateral surface formed from a metallic material according to an embodiment. For a better illustration of the method are in the 7 to 10 additional schematic plan views of the semiconductor substrate 200. in the manufacture of the semiconductor chips 250 shown. The substrate 200. which comprises a semiconductor material such as silicon, for example, represents a semiconductor wafer referred to as a "wafer".

The semiconductor substrate 200. will be like in the 2 and 7 indicated with several active chip areas or chip areas 210 provided. The substrate may therefore be a processed so-called "front-end wafer". 2 is the lateral sectional view along the section line AA of 7 , The active chip areas 210 include electrical and electronic structures for integrated circuits (not shown).

Subsequently, as in the 3 and 8th shown in the top of the semiconductor substrate 200. at a distance to the active chip areas 210 a specialization structure 220 which is referred to below as "first recess" 8th hatching shown becomes clear that the first recess 220 in the plan view of the top of the substrate 200. one each around an active chip area 210 has circumferential or spanning shape. In this case, the first recess 220 or have sections of the first recess 220 between the individual chip surfaces 210 as in 3 represented a width W1.

For forming the first recess 220 For example, a mechanical sawing process is considered. In such a sawing process, a sawing device usually used in the context of a dicing process of semiconductor chips can be used with a corresponding saw blade. In addition, there is the possibility of a focused laser beam on top of the semiconductor substrate 200. to lead along to the first recess 220 in the top of the substrate 200. contribute. Such a laser pro Zess is also known as "laser cutting".

Alternatively, the first recess 220 also be produced using a plasma etching process. In such an etching process, areas are formed on the upper surface of the semiconductor substrate 200. which are not to be etched, covered by one or more suitable masking layers (not shown). Considered, for example, the use of a photoresist layer, which on the top of the substrate 200. applied and patterned by performing a lithography process. It is also possible to use a hard mask layer on top of the substrate 200. , which is patterned using a patterned photoresist layer in an additional etching process. During the plasma etching, the substrate becomes 200. Etched in the exposed, unmasked areas and thereby the first recess 220 in the top of the substrate 200. educated. After performing the plasma etching process, the masking layer or the masking layers can be removed again.

Following the formation of the first recess 220 will be like in 4 represented a metallic material 230 in the first well 220 brought in. It is hereby granted that the first depression 220 completely with the metallic material 230 is filled. The metallic material 230 For example, has a highly conductive metal such as silver, aluminum, gold, copper, nickel and / or tin.

For the introduction of the metallic material 230 in the first well 220 There are a variety of procedures available. For example, the metallic material 230 initially over a large area while filling the first recess 220 on top of the semiconductor substrate 200. be applied and subsequently removed to a part such that the metallic material 230 as in 4 shown only in the first recess 220 remains. The metallic material 230 may be present in the form of a pure metal or an alloy.

Before large-scale application of the metallic material 230 can be the active chip areas 210 be covered with a corresponding protective layer (not shown). For example, a polyimide layer or a photoresist layer may be considered. It is also possible to use the above-described masking layers used in an optionally performed plasma etching process, which are therefore left to stand.

Large area application of the metallic material 230 can be done using a galvanization process. In advance of the galvanization process, a seed layer of the material in question can additionally be applied to the top side of the substrate by means of a coating method such as CVD (Chemical Vapor Deposition) or ALD (Atomic Layer Deposition) 200. be deposited. Alternatively, the large-scale application of the metallic material 230 using a sputtering process, also referred to as sputtering.

The large area applied metallic material 230 is subsequently partially removed, as described above, only within the first recess 220 to remain. For example, a polishing process such as chemical mechanical polishing (CMP) may be performed for this purpose. It is also possible to use a wet-chemical etching process.

Instead of a large-scale application in the context of a galvanization or a sputtering process and a subsequent partial removal, the metallic material 230 also in the form of a solder paste in the first recess 220 are introduced, which hardens after waiting for a predetermined period of time. For targeted introduction of the solder paste in the first recess 220 a stencil or screen printing process is preferably used. Optionally, the solder paste can be additionally melted in an optional temperature step.

Furthermore, the metallic material 230 in the form of a polymer conductive paste, a conductive plastic or a conductive adhesive in the first recess 220 be introduced. The introduction of such substances into the first well 220 takes place in (tough) liquid form, again preferably a stencil or screen printing process is used. For rapid curing of such substances, following the introduction into the first recess 220 an additional temperature step be performed. In such a temperature step, the semiconductor substrate 200. be exposed to a temperature of, for example, 180 ° C for a period of, for example, 30 minutes.

Subsequently, as in the 5 and 9 shown in the top of the semiconductor substrate 200. another deepening structure 240 which is referred to below as the "second depression." The second depression 240 or their subsections between the individual chip areas 210 show as in 5 1, a width W2 that is smaller than the width W1 of the first recess 220 , Also, a depth of the second recess 240 preferably smaller than a depth of the first recess 220 , The formation of the second deepening 240 can according to the first recess 220 again by means of a mechanical sawing process, a laser process or a plasma etching process. For details on these processes, reference is made to the above statements.

The second well 240 points like the first recess 220 in the plan view of the top of the semiconductor substrate 200. one each around an active chip area 210 circumferential or spanning shape, which is based on the in 9 hatching shown, and defines the lateral structures of the later semiconductor chips 250 firmly. In addition, the second recess 240 within the first recess 220 formed, leaving a part of the metallic material 230 is removed and the metallic material 230 as in 5 shown in cross section has a U-shaped configuration. Also, all of the "inner" side walls or side surfaces of each have an active chip surface 210 circumferential part of the second recess 240 the metallic material 230 or border on the metallic material 230 at. By way of illustration, in 9 inner sidewalls of the hatched and around a chip area 210 circumferential part of the second recess 240 with the reference number 245 characterized.

Subsequently, substrate material is applied to a lower surface of the semiconductor substrate 200. to at least the second recess 240 removed, to isolated semiconductor chips 250 like in the 6 and 10 illustrated form. Such backside removal of substrate material, also referred to as "thinning", can be accomplished by a grinding process. The isolated semiconductor chips 250 each have a circumferential layer 231 of the metallic material at the edge or on the lateral surface of the chips 250 which offers the advantages described above with regard to the EMC behavior, the thermal behavior and the mechanical properties. Since the width W2 of the second recess 240 is smaller than the width W1 of the first recess 220 , and the second recess 240 within the first recess 220 is formed, each in a section of the first recess 220 between two juxtaposed chip surfaces 210 introduced metallic material 230 in the singulation of the associated semiconductor chips arranged side by side 250 "distributed".

In addition to the described process steps, further optional process steps can be carried out. For example, the formation of devices on the semiconductor chips is considered 250 , which with the metallic material 231 at the chip edges or the layers 230 are connected and formed, a quantity of heat to the layers 230 transferred to. Such a device can, in particular, strip conductors 140 according to the in 1 illustrated semiconductor chip 100 include. The formation of such conductor tracks can after the singulation process of the semiconductor chips 250 or even before that on the "undivided" semiconductor substrate 200. respectively. Such traces may, for example, on the tops or bottoms of the chips 250 be arranged.

11 shows a schematic side sectional view of a chip stack 300 according to one embodiment. The chip stack 300 has a plurality of semiconductor chips arranged one above the other 320 on, being between the chips 320 For example, adhesive or spacer layers 325 are arranged. Instead of in 11 illustrated three semiconductor chips 320 can the chip stack 300 also a different number of chips 320 exhibit. The semiconductor chips 320 are electrically interconnected (e.g., via via), redistribution layers and / or wirebond connections (not shown).

Every semiconductor chip 320 of the chip stack 300 has a layer on the edge 330 of a metallic material. The layer 330 can be an edge of a semiconductor chip 320 completely cover and therefore a semiconductor chip 320 completely circulate. Regarding the possible materials for the layers 330 Reference is made to the above statements.

The chip stack 300 is characterized by an effective EMC protection, since the around the semiconductor chips 320 arranged around layers 330 of the metallic material both shielded from the chips 320 acting electromagnetic fields, as well as the emission of noise or fields in the environment of the chips 320 or the chip stack 300 in the operation of the chips 320 reliably suppress. The layers 320 moreover favor the thermal properties of the semiconductor chips 320 and ensure a high mechanical stability of the chips 320 , The high mechanical stability, for example, facilitates the handling of the chips 320 when stacked as part of a production of the chip stack 300 ,

In the chip stack 300 from 11 In addition, there is the possibility of the layers 330 the individual semiconductor chips 320 conductively connect with each other. This can be done by appropriate metallic connections such as at the edge between the chips 320 Locally provided solder joints done (not shown). In this way, a more homogeneous heat distribution and delivery of the entire chip stack 300 achieved and the EMC behavior can be further improved.

In addition, a connection of the layers of the metallic material of semiconductor chips of a chip stack can also take place via an additional continuous layer of a metallic material or a metallization on the flank of a chip stack. This shows 12 a schematic side sectional view of a chip stack 310 according to a further embodiment. The chip stack 310 again has stacked semiconductor chips 320 on, their edges with a layer 330 a metallic material are provided. In contrast to the chip stack 300 from 11 has the chip stack 310 according to 12 an additional layer 340 of a metallic material which forms the layers 330 the individual semiconductor chips 320 conductively connects with each other.

The layer 340 can like the individual layers 330 the chips 320 only a part or the entire chip stack 310 circulate. The layers 330 . 340 may have the same metallic material or different materials. Through the additional layer 340 allows a particularly homogeneous heat distribution and delivery of the entire chip stack 310 and high EMC protection can be achieved. To form the layer 340 For example, the chip stack can be immersed in a metallic bath. It is also possible, the shift 340 as solder paste, for example, with a Dispensevorrichtung apply to the edge of the stack.

The explained with reference to the figures embodiments represent preferred embodiments. About that In addition, further embodiments can be realize further modifications.

For example In a semiconductor chip, a lateral surface may not be complete, but rather only be formed in part of a metallic material. This includes, for example, embodiments in which only on one or more side walls or on selected ones Sections of the lateral surface a chip is a metallic material is formed. such embodiments can For example, be provided to the EMC behavior of a chip selectively influence.

For the production of such semiconductor chips, the basis of the 2 to 10 explained method are modified such that a first recess formed in an upper surface of a substrate in the plan view does not have around an active chip area circulating, self-contained form. A second recess is therefore formed in the top such that with respect to an active chip surface, at least one or a portion of an inner sidewall of the second recess has the metal material introduced into the first recess.

Also, an edge of a semiconductor chip viewed in cross-section may have only a part of a metallic material. Such an embodiment can be made, for example, that in the basis of the 2 to 10 explained method, a first recess is not completely, but only partially filled with a metallic material or a part of the introduced into the first recess metallic material is removed again. Also, a depth of the second recess can be selected to be greater than a depth of the first recess, as a result of which an isolated semiconductor chip has substrate material underneath the metallic material at the edge region.

Of others can the side walls the second recess in cross section instead of a straight profile have a different profile such as a step shape. By such a profile is in a corresponding way the shape of the metallic material at the edge of a semiconductor chip.

Furthermore is the possibility given, the metallic material of the lateral surface in a semiconductor chip form in different layer thicknesses. For example, can the metallic material at a region or sidewall the lateral surface a semiconductor chip with a relation to other locations of the lateral surface enlarged Schichtdi bridge be educated. Such an embodiment may, for example come into consideration to the chip in terms of mechanical stresses while to increase processing, which only at certain locations or sides of the border area occur.

Furthermore, for the production of semiconductor chips with a boundary layer of a metallic material instead of the basis of the 2 to 10 described method other methods conceivable. One possible approach, for example, is to provide the top and bottom of a singulated semiconductor chip with a masking layer and to dip the chip in a bath of liquid metal to metallize the shell surface or a portion thereof. Furthermore, a metallic material in the form of a solder paste, a polymer conductive paste or a conductive adhesive can be applied by means of a dispensing device to an edge of a singulated semiconductor chip.

100

Semiconductor chip

110

top

120

lateral surface

130

heat source

140

conductor path

200

Semiconductor substrate

210

active chip area

220

First deepening

230

metallic material

231

layer (metallic material)

240

Second deepening

245

Inner Side wall

250

Semiconductor chip

300, 310

stack

320

Semiconductor chip

325

adhesive layer

330

layer (metallic material)

340

layer (metallic material)

A-A

intersection

W1

width the first well

W2

width the second well

Claims (21)

Chip stack with a plurality of semiconductor chips ( 320 ), each semiconductor chip ( 320 ) has an upper side, a lower side and an encircling peripheral surface adjoining the upper and lower sides, the lateral surface being formed by a metallic material ( 330 ) is formed in the form of a layer, which the semiconductor chip ( 320 ) rotates. The chip stack of claim 1, wherein the layer comprises a Layer thickness in the μm range having. Chip stack according to one of the preceding claims, wherein the metallic material ( 330 ) has at least one element of the group silver, aluminum, gold, copper, nickel, tin. Chip stack according to one of the preceding claims, wherein the metallic material ( 330 ) comprises a metal or an alloy. Chip stack according to one of the preceding claims, wherein the metallic material ( 330 ) is formed by a solder paste, a Polymerleitpaste or a conductive adhesive. A chip stack according to any one of the preceding claims, further comprising one with the metallic material ( 330 ) of the lateral surface connected conductor track for transferring a quantity of heat to the metallic material ( 330 ). Chip stack according to one of the preceding claims, wherein the metallic material ( 330 ) of the lateral surfaces of the individual semiconductor chips ( 320 ) is conductively connected to each other. Method for producing a semiconductor chip, comprising the method steps: - providing a semiconductor substrate ( 200. ); - forming a first recess ( 220 ) in an upper surface of the semiconductor substrate ( 200. ); - introducing a metallic material ( 230 ) into the first well ( 220 ); - forming a second recess ( 240 ) in the top of the semiconductor substrate ( 200. ), whereby a lateral structure of a semiconductor chip ( 250 ) and a part of the metallic material ( 230 ) is removed such that an inner side wall ( 245 ) of the second recess ( 240 ) the metallic material ( 230 ) having; - Removal of substrate material on a bottom side of the semiconductor substrate ( 200. ) to at least the second recess ( 240 ), so that an isolated semiconductor chip ( 250 ) with a metallic material ( 231 ) on a semiconductor chip ( 250 ) circumferential lateral surface is formed. Method according to claim 8, wherein a width (W2) of the second recess (W2) 240 ) is smaller than a width (W1) of the first recess ( 220 ). Method according to one of claims 8 or 9, wherein the metallic material ( 230 ) in the first well ( 220 ), that the first recess ( 220 ) completely with the metallic material ( 230 ) is filled. Method according to one of claims 8 to 10, wherein the first recess ( 220 ) and the second recess ( 240 ) in the plan view of the top side of the semiconductor substrate ( 200. ) have a circumferential shape, and wherein the second recess ( 240 ) within the first well ( 220 ) is formed, so that all inner side walls ( 245 ) of the second recess ( 240 ) the metallic material ( 230 ) exhibit. Method according to one of claims 8 to 11, wherein the metallic material ( 230 ) has at least one element of the group silver, aluminum, gold, copper, nickel, tin. Method according to one of claims 8 to 12, wherein the metallic material ( 230 ) in the form of a metal or an alloy in the first recess ( 220 ) is introduced. The method of claim 13, wherein the metallic material ( 230 ) by means of a galvanization process or a sputtering process into the first well ( 220 ) is introduced. Method according to one of claims 8 to 12, wherein the metallic material ( 230 ) in the form of a solder paste, a polymer paste or a conductive adhesive in the first recess ( 220 ) is introduced. Process according to claim 15, wherein the metallic material ( 230 ) using a screen-printing process into the first well ( 220 ) is introduced. Method according to one of claims 15 or 16, further comprising carrying out a temperature step after the introduction of the metallic material ( 230 ). Method according to one of claims 8 to 17, wherein the formation of at least one of the two depressions ( 220 . 240 ) is performed by means of a mechanical sawing process. Method according to one of claims 8 to 18, wherein the formation of at least one of the two depressions ( 220 . 240 ) is performed using a plasma etching process. Method according to one of claims 8 to 19, wherein the forming of at least one of the two recesses ( 220 . 240 ) is performed using a laser process. Method according to one of claims 8 to 20, further comprising forming a conductor track ( 140 ) connected to the metallic material of the semiconductor chip and configured to transfer an amount of heat to the metallic material.