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DE102007045930A1 - Partial galvanic pure tin-surface producing method for printed circuit board, involves stripping photo-layer by alkaline stripper, tin-plating and soldering solder pad, and covering regions provided as copper surfaces with solder resist - Google Patents

Partial galvanic pure tin-surface producing method for printed circuit board, involves stripping photo-layer by alkaline stripper, tin-plating and soldering solder pad, and covering regions provided as copper surfaces with solder resist Download PDF

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Publication number
DE102007045930A1
DE102007045930A1 DE200710045930 DE102007045930A DE102007045930A1 DE 102007045930 A1 DE102007045930 A1 DE 102007045930A1 DE 200710045930 DE200710045930 DE 200710045930 DE 102007045930 A DE102007045930 A DE 102007045930A DE 102007045930 A1 DE102007045930 A1 DE 102007045930A1
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Germany
Prior art keywords
tin
circuit board
layer
photo
printed circuit
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Ceased
Application number
DE200710045930
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German (de)
Inventor
Rolf Bauer
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Individual
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Individual
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Priority to DE200710045930 priority Critical patent/DE102007045930A1/en
Publication of DE102007045930A1 publication Critical patent/DE102007045930A1/en
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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/243—Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/0257—Brushing, e.g. cleaning the conductive pattern by brushing or wiping
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0361—Stripping a part of an upper metal layer to expose a lower metal layer, e.g. by etching or using a laser
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0562—Details of resist
    • H05K2203/0577—Double layer of resist having the same pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0094—Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061—Etching masks
    • H05K3/062—Etching masks consisting of metals or alloys or metallic inorganic compounds
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061—Etching masks
    • H05K3/064—Photoresists
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)

Abstract

The method involves laminating a dry film-photo-resist on a wash primer for closing boreholes in a solder pad. A photo-layer is exposed with UV light by a negative film. An exposed printed circuit board is developed in the soda solution, and an unexposed photo- layer is washed. Uncovered tin surfaces are taken away in a tin stripper. The photo-layer present on the tin-plated solder pad is stripped by an alkaline stripper. The pad is tin-plated and soldered. The regions provided as copper surfaces are covered with a solder resist.

Description

Beschrieben wird ein Verfahren zur partiellen galvanischen Reinzinn Verzinnung von Leiterplattenoberflächen mit einer mindestens 10 μm starken absolut planen und für mehrere Jahre sehr gut lötbaren Zinnschicht, auf den vom Lötstopplack unbedeckten Lötflächen und Pads.described is a process for partial galvanic pure tin tinning of printed circuit board surfaces with a minimum of 10 μm strong absolutely plan and for Solderable very well for several years Tin layer on top of the solder resist uncovered soldering surfaces and Pads.

Infolge gesetzlicher Regelungen dürfen Leiterplatten bis auf einige Ausnahmen nicht mehr mit Bleizinn Oberflächen produziert werden. Es ist zum Verzinnen von Leiterplatten nur noch Reinzinn erlaubt. Dieses führt bei der Heißluftverzinnung zu erheblichen Problemen, da der Schmelzpunkt von Reinzinn gegenüber Bleizinn erheblich höher liegt. Es bilden sich auf den zu verzinnenden Lötflächen oft dicke Zinnhügel, die zu Kurzschlüssen zwischen den Pads führen können. Des Weiteren muss bei der Bestückung mit wesentlich höheren Temperaturen gearbeitet werden, wodurch empfindliche Bauteile Schaden nehmen können.As a result legal regulations PCBs, with some exceptions, are no longer produced with lead-tin surfaces become. It is for tin plating of PCB only pure tin allowed. This leads in hot air tinning to significant problems, since the melting point of pure tin compared to lead tin considerably higher lies. Thick Zinnhügel often form on the soldered surfaces, the to short circuits between the pads can. Furthermore, in the assembly with much higher Temperatures are worked, causing sensitive components damage can take.

Es gibt auch noch die Möglichkeit der chemischen Verzinnung, die jedoch noch schlechter geeignet ist. Die Zinnschicht hat hierbei nur eine Stärke von 0,8–1,2 μm. Diese Schicht hat keinerlei lötunterstützende Wirkung und diffundiert wegen der fehlenden Sperrschicht innerhalb weniger Tage in das darunter liegende Kupfer. Die Flächen und Pads sind danach absolut nicht mehr lötbar. Um die Lötbarkeit etwas zu verlängern wird von einigen Herstellern unter der chemisch verzinnten Oberfläche eine Sperrschicht aus Nanometall mit einer Schichtstärke von ca. 70–90 Nanometer aufgebracht. Diese kann die Diffusion zwar etwas verzögern, jedoch nicht wesentlich unterbinden. Eine chemische Zinnoberfläche hat gegenüber der Heißluftverzinnung nur den Vorteil, dass die Lötflächen und Pads absolut plan sind.It There is also the possibility the chemical tinning, which is even worse suited. The tin layer in this case only has a thickness of 0.8-1.2 microns. This layer has no soldering support effect and diffuses within less due to the missing barrier layer Days in the underlying copper. The surfaces and pads are then absolute no longer solderable. To the solderability to extend something is made by some manufacturers under the chemically tinned surface one Barrier layer of nanometal with a layer thickness of approx. 70-90 nanometers applied. This can slow down the diffusion a bit, however do not significantly prevent. A chemical tin surface has opposite the Hot Air Leveling only the advantage that the soldering surfaces and Pads are absolutely flat.

Aufgabe der Erfindung ist ein Verfahren zur Schaffung einer partiellen Leiterplatten-Reinzinnoberfläche, die absolut plan und bleifrei ist, eine Schichtstärke von mindestens 10 μm besitzt, mehrere Jahre gut lötbar bleibt und kein Spezialfluxer benötigt.task The invention is a method for creating a partial printed circuit board pure tin, the absolutely flat and lead-free, has a layer thickness of at least 10 microns, Solderable for several years remains and no special fluxer needed.

Die Lösung dieser Aufgabe erfolgt durch ein Verfahren, bei dem die Lötflächen und Pads mit einem galvanischen Reinzinn von mindestens 10 μm und einer absolut planen Oberfläche beschichtet werden. Zwischen dem Kupferuntergrund und der Zinnschicht baut sich beim Galvanisieren eine intermetallische Sperrschicht von 0,2–0,4 μm Stärke auf; diese verhindert für mehrere Jahre, dass das Zinn in den Kupferuntergrund eindiffundiert.The solution This object is achieved by a method in which the solder pads and Pads with a pure galvanic tin of at least 10 μm and one absolutely plan surface be coated. Between the copper substrate and the tin layer During plating, an intermetallic barrier layer builds up from 0.2-0.4 μm thickness; these prevents for several years that the tin diffuses into the copper substrate.

Das galvanische Reinzinnverfahren muss schon bei der Fertigung der Leiterplatten Berücksichtigung finden. Eine nachträgliche Beschichtung fertig geätzter Leiterplatten ist nicht mehr möglich. Zunächst werden die Leiterplatten in den üblichen bekannten Verfahren gefertigt. Auf die kupferkaschierten (durchkontaktierte) und fotobeschichteten Platten wird das entsprechende Leiterbild mittels Positivfilm und UV-Licht übertragen. Dann wird das Leiterbild entwickelt und die unbelichteten Bereiche werden ausgewaschen. Im Anschluss wird das Leiterbild galvanisch aufgekupfert und anschließend im Reinzinnbad galvanisch verzinnt. Zuletzt wird noch die Fotoschicht gestrippt und die Platten geätzt. Jetzt ist auf den Platten nur noch das entsprechende Leiterbild mit den verzinnten Leiterbahnen und Anschlusspads vorhanden.The Galvanic pure tin must already during the production of printed circuit boards consideration Find. An afterthought Coating finished etched Printed circuit boards are no longer possible. First the printed circuit boards are in the usual manufactured known methods. On the copper-clad (plated-through) and photo-coated plates will be the corresponding circuit pattern transmitted by positive film and UV light. Then the ladder picture is developed and the unexposed areas are washed out. In connection the circuit diagram is electroplated and afterwards in the Reinzinnbad galvanically tin-plated. Last still is the photo shift stripped and the plates etched. Now only the corresponding circuit diagram is on the plates the tinned conductor tracks and connection pads available.

Die Zinnoberfläche wird im Anschluss angeraut (gebürstet), entfettet und getrocknet. Dann wird ein flüssiges Fotoresist auf die Leiterplatte aufgetragen und getrocknet. Dieses dient als Haftvermittler zwischen der Zinnoberfläche und dem Trockenfilm-Fotoresist, das anschließend auf die Leiterplatte auflaminiert wird und die Bohrungen in den Lötpads verschließt. Danach wird die Leiterplatte durch ein Filmnegativ mit UV-Licht belichtet. Dadurch wird die Fotoschicht an den UV-lichtdurchlässigen Stellen ausgehärtet. Als nächstes wird die Leiterplatte in Sodalösung entwickelt, wobei an den unbelichteten Stellen die Fotoschicht abgewaschen wird. Nun ist die Fotoschicht nur noch an den zuvor belichteten Stellen auf der Zinnoberfläche vorhanden und schützt diese beim anschließenden Zinnstrippen. Die Zinnschicht wird dann im Zinnstripper (Säurebad) von allen unbedeckten Stellen entfernt (gestrippt). Danach wird noch die Fotoschicht von den Pads und Lötflächen in einer alkalischen Stripperlösung entfernt (gestrippt). Die nach diesem Verfahren gefertigte Leiterplatte hat eine Kupfergrundfläche mit partiell verzinnten Lötpads. Im Anschluss wird die Leiterplatte mit Lötstopplack beschichtet.The tin surface is then roughened (brushed), degreased and dried. Then a liquid photoresist is applied to the circuit board applied and dried. This serves as a bonding agent between the tin surface and the dry film photoresist, which is subsequently laminated to the circuit board and closes the holes in the solder pads. After that the printed circuit board is exposed to UV light by a film negative. As a result, the photo layer is cured at the UV-transparent sites. When next becomes the circuit board in soda solution developed, washed at the unexposed areas of the photo layer becomes. Now the photo layer is only on the previously exposed areas on the tin surface exists and protects this in the subsequent Zinnstrippen. The tin layer is then in Zinnstripper (acid bath) of removed from all uncovered areas (stripped). After that will still remove the photo layer from the pads and pads in an alkaline stripper solution (Stripped). The manufactured according to this method PCB has a copper base with partially tinned solder pads. Subsequently, the printed circuit board is coated with solder mask.

Claims (1)

Verfahren zur partiellen galvanischen Reinzinn-Oberflächenbeschichtung, gekennzeichnet durch folgende Arbeitsschritte in der angegebenen Reihenfolge: – die Zinnoberfläche bleibt nach dem Ätzen auf der Leiterplatte erhalten, – die Zinnoberfläche wird mechanisch angeraut (gebürstet), entfettet und getrocknet, – auf die Leiterplatten Zinnoberfläche wird ein flüssiges Fotoresist als Haftgrund aufgetragen und getrocknet, – zum Verschließen der Bohrungen in den Lötpads wird auf diesen Haftgrund ein Trockenfilm-Fotoresist auflaminiert, – diese Fotoschicht wird durch eine negative Filmvorlage mit ultraviolettem Licht belichtet, – bei einer zweiseitigen Leiterplatte werden diese Arbeitsschritte auf beiden Seiten durchgeführt, – die belichtete Leiterplatte wird in Sodalösung entwickelt, wobei die unbelichtete Fotoschicht abgewaschen wird, – die jetzt unbedeckten Zinnflächen werden in einem Zinnstripper entfernt, – die noch auf den verzinnten Lötpads vorhandene Fotoschicht wird in einem alkalischem Stripper entfernt (gestrippt), – jetzt sind nur noch die Pads und Stellen verzinnt, die später verlötet werden, – die übrigen als Kupferfläche vorhandenen Bereiche werden mit Lötstopplack abgedeckt.Process for partial galvanic pure tin surface coating, characterized by the following steps in the order given: - the tin surface is retained after etching on the circuit board, - the tin surface is mechanically roughened (brushed), degreased and dried, - on the circuit boards tin surface is a applied liquid photoresist as a primer and dried, - to close the holes in the solder pads on this primer a dry film photoresist is laminated, - this photo layer is exposed by a negative film original with ultraviolet light, - in a two-sided circuit board, these steps on both sides carried out, - The exposed printed circuit board is developed in sodium carbonate solution, whereby the unexposed photo layer is washed off, - The now uncovered tin surfaces are removed in a tin stripper, - The still existing on the tinned solder pads photo layer is removed (stripped) in an alkaline stripper, - now only tinned still the pads and points, which are soldered later, - the remaining existing as a copper surface areas are covered with solder mask.
DE200710045930 2007-09-24 2007-09-24 Partial galvanic pure tin-surface producing method for printed circuit board, involves stripping photo-layer by alkaline stripper, tin-plating and soldering solder pad, and covering regions provided as copper surfaces with solder resist Ceased DE102007045930A1 (en)

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DE200710045930 DE102007045930A1 (en) 2007-09-24 2007-09-24 Partial galvanic pure tin-surface producing method for printed circuit board, involves stripping photo-layer by alkaline stripper, tin-plating and soldering solder pad, and covering regions provided as copper surfaces with solder resist

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DE200710045930 DE102007045930A1 (en) 2007-09-24 2007-09-24 Partial galvanic pure tin-surface producing method for printed circuit board, involves stripping photo-layer by alkaline stripper, tin-plating and soldering solder pad, and covering regions provided as copper surfaces with solder resist

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102018129358A1 (en) * 2018-11-21 2020-05-28 Siteco Gmbh CIRCUIT BOARD FOR AN LED MODULE, LED MODULE AND METHOD FOR THE PRODUCTION THEREOF
CN114980562A (en) * 2022-06-28 2022-08-30 珠海中京电子电路有限公司 Manufacturing method of pure tin plated plate, PCB and terminal equipment
CN118854429A (en) * 2024-09-14 2024-10-29 江苏省沙钢钢铁研究院有限公司 A treatment method and application of coated tinplate

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2209178B2 (en) * 1972-02-26 1974-12-19 Robert Bosch Fernsehanlagen Gmbh, 6100 Darmstadt Process for the production of printed circuits
DE3623505C2 (en) * 1986-07-09 1988-04-28 Deutsche Telephonwerke Und Kabelindustrie Ag, 1000 Berlin, De
US5296333A (en) * 1990-11-16 1994-03-22 Raytheon Company Photoresist adhesion promoter

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2209178B2 (en) * 1972-02-26 1974-12-19 Robert Bosch Fernsehanlagen Gmbh, 6100 Darmstadt Process for the production of printed circuits
DE3623505C2 (en) * 1986-07-09 1988-04-28 Deutsche Telephonwerke Und Kabelindustrie Ag, 1000 Berlin, De
US5296333A (en) * 1990-11-16 1994-03-22 Raytheon Company Photoresist adhesion promoter

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Online Internet- Veröffentlichung ElektronikPraxis VT: 27.01.2007 Aktiv-Zinn-Schicht punktet gegenüber HAL und Chemisch Zinn http://www.elektronikpraxis.vogel.de/themen/hardwareentwicklung/leiterplatten/article/52810/?bcsiscan_1BCF1BFBAB29F959= +4MwhXaCeh7JXPSwSRpYggYAAACYr *
Online Internet- Veröffentlichung ElektronikPraxis VT: 27.01.2007 Aktiv-Zinn-Schicht punktet gegeübe r HAL und Chemisch Zinn http://www.elektronikpraxi s.vogel.de/themen/hardwareentwicklung/ leiterplatt en/article/52810/?bcsi_scan_1BCF1BFBAB29F959= +4Mw hXaCeh7JXPSwSRpYggYAAACYr

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102018129358A1 (en) * 2018-11-21 2020-05-28 Siteco Gmbh CIRCUIT BOARD FOR AN LED MODULE, LED MODULE AND METHOD FOR THE PRODUCTION THEREOF
CN114980562A (en) * 2022-06-28 2022-08-30 珠海中京电子电路有限公司 Manufacturing method of pure tin plated plate, PCB and terminal equipment
CN118854429A (en) * 2024-09-14 2024-10-29 江苏省沙钢钢铁研究院有限公司 A treatment method and application of coated tinplate

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