DE102007033517A1 - Integrated circuit, particularly matrix of multiple integrated circuits, has terminal and another terminal for potential and third terminal for another potential and two four-layer arrangements have two conductivity types on common track - Google Patents

Abstract

The integrated circuit has a terminal (PADI) and another terminal (VDD) for a potential and third terminal (VSS) for another potential. Two four-layer arrangements have two conductivity types on common track. The track of a former conductivity type has a zone of a former conductivity type and two zones of latter conductivity type. The track of the latter conductivity type has a zone of a latter conductivity type and two zones of former conductivity type. All zones are at a distance from each other by insulations (30).

Description

The The invention relates to a protective structure against electrostatic discharges for electronic components. In production, handling or operation of electronic components can be electrostatic Discharges occur at the terminals of the components.

When crossing the load limit of the affected circuit parts of an electronic circuit Destruction can occur.

To protect against electrostatic discharges (ESD: electro-static discharge) protective measures are provided to increase the resistance against electrostatic overvoltages. Protective elements formed of protective structures are connected between inputs or outputs and supply potentials which become conductive when a threshold voltage is exceeded and derive a voltage to a supply potential. Some prior art protective measures are in the US-2002/0154463 described.

The Realization of known protective elements takes up a lot of space and long leads. An electronic to protect Component, such as a circuit is in addition loaded capacitively and an adjustment of the switching threshold for protection the circuit can only be done inadequately.

A Object of the present invention is to protect structures to realize with precisely adjustable switching thresholds, Protective structures to save space in a system to integrate and to To load protective component with little capacitive.

These The object is achieved by a protective structure arrangement having the features of claim 1.

advantageous Training and further education are in the dependent claims Are defined.

The The present invention is based on the idea of connecting a electronic component, against electrostatic charges should be protected, with at least two trained in a protective structure To couple four-layer arrangements, which is a common area of a have first conductivity type and a second conductivity type and are realized as complementary thyristors.

In order to It is possible with a protective structure several to be protected Paths of an electronic circuit against electrostatic charge to protect. The space required for protective structures decreases noticeably, ideally by almost half, and in particular, by combining protective structures, the Switching threshold and the capacitive load of a protected Circuit can be adjusted.

following be different embodiments with respect to the attached figures explained in more detail.

It demonstrate:

1 a cross section of a protective structure with a possible wiring arrangement;

2 a representation of the layout of in 1 cross-sectional protection structure;

3 a cross section of a protective structure as in 1 with an alternative Beschaltungsmöglichkeit;

4 a representation of the layout of in 3 listed protective structure;

5 the cross section of a protective structure with a possible first protection path for an intrigued circuit;

6 the cross section of a protective structure with a possible second protection path for an intrigued circuit;

7 the cross section of a protective structure with a possible third protection path for an intrigued circuit;

8th in the layout of the layout 2 the position of the structures that can be combined into thyristors;

9 in cross-section according to 8th possible interconnection taking into account the diffusion resistances Rd1 or Rd2 formed in trays;

10 a schematic representation of in 9 realized arrangement;

11 a representation of the layout of a possible further development of a protective structure;

12 a representation of the layout of a possible combination of protection structures 11 ;

13 a possible distribution of protection structures within an electronic circuit;

1 shows the cross section of a protection structure (SS), which can be used to protect against electrostatic discharge in electronic components, such as integrated circuits, semiconductor memory or processors.

In the 1 The illustrated protective structure (SS) has two adjacent, for example trough-shaped, doping regions (US Pat. 10 . 20 ) on,
made of n-conductive material ( 10 ) and p-type material ( 20 ) are formed.

The n-conductive area ( 10 ) has a zone formed of n-type material ( 11 ) and two zones formed of p-type material ( 22 . 23 ) on.

The p-type region ( 20 ) has a zone formed of p-type material ( 21 ) and at least two zones formed of n-type material ( 12 . 13 ) on. The n- and p-type zones ( 11 . 22 . 23 . 12 . 13 . 21 ) are isolated by an isolation ( 30 ) separated from each other.

A realization of a p-type or n-type zone can take place, for example, by diffusion and / or implantation, an implementation of an isolation of adjacent zones, for example by means of a so-called shellow trench isolation (STI). The protective structure (SS) off 1 shows two four-layer arrangements ( 23 . 10 . 20 . 13 ; 12 . 20 . 10 . 22 ), which is a common area ( 10 . 20 ) exhibit.

sketchy is over the cross section a possible wiring the protection structure (SS) for the first terminal PADI, an inner terminal, an integrated circuit shown.

The first port to be protected (PADI) is associated with the sliding zone ( 22 ) of the n-type area ( 10 ) and with the n-type zone ( 13 ) of the p-type region ( 20 ) connected. A second terminal of a first potential (VDD) is connected to the p-type zone ( 23 ) of the n-type area ( 10 ) connected.

A third terminal of a second potential (VSS) is connected to the n-type zone ( 12 ) of the p-type region ( 20 ) connected.

The sensitivity of the protective structure (SS) can be determined via the resistor (R1), whose first connection to the n-type region of the n-type region ( 10 ) and whose second terminal is connected to the second terminal of the first potential (VDD) and / or to a second resistor (R2) whose first terminal is connected to the p-type zone of the p-type region ( 20 ) and whose second terminal is connected to the third terminal of the second potential (VSS).

A possible embodiment of the resistances of (R1, R2) can be used as a discrete element, as a semiconductor structure or as Track done.

For the in 1 to be protected first terminal (PADI) of an integrated circuit acting as thyristors four-layer arrangements from the zones or areas ( 23 . 10 . 20 . 13 ) and ( 12 . 20 . 10 . 22 ) realized.

2 shows a possible realization of the in 1 Cross-sectional protection structure (SS).

An interconnection of the protective structure (SS) takes place for example via the connected to the terminals ( 11 . 22 . 23 . 12 . 13 . 21 ) Conductor tracks ( 40 ).

By the resistors (R1, R2) become the operating points of the two set in the protective structure (SS) realized thyristors.

Due to the dependence of the resistance on the doping, it is possible to 10 ) or ( 20 ) provided resistor (Rd1, Rd2) to adjust the operating point of the thyristors.

This in 1 respectively. 2 illustrated example of a protective structure (SS) allows two acting as thyristors four-layer arrangements to save space. There is a need to produce only a four-layer arrangement in a protection arrangement and consequently the realization of one of the zones ( 22 . 23 ) and ( 12 . 13 ), the chip area required for this purpose corresponds almost to the required chip area required for the realization of two four-layer arrangements. The saving of two doped zones, for example ( 12 . 23 ), leads to no significant reduction in chip area. As in 1 or in 2 can be shown, acting as two thyristors four-layer arrangements ( 23 . 10 . 20 . 13 ) and ( 12 . 20 . 10 . 22 ) in a protective structure (SS) on a surface that is usually used for a four-layer arrangement ( 23 . 10 . 20 . 13 ) or ( 12 . 20 . 10 . 22 ) is needed. 3 shows an alternative wiring of the in 1 respectively. 2 described protective structure (SS).

In contrast to 1 takes place in 3 the first terminal of a circuit to be protected (PADI) to the p-type zone ( 23 ) of the n-type area ( 10 ) and to the n-type zone ( 12 ) of the p-type region ( 20 ). The second terminal of the first potential (VDD) is connected to the p-type zone ( 22 ) of the n-type area ( 10 ) and the third terminal of the second potential (VSS) with the n-type region of the p-type region ( 20 ). Without To make changes to the production of the protective structure (SS), the sensitivity of the formed thyristors ( 22 . 10 . 20 . 12 ; 13 . 20 . 10 . 23 ) can be varied due to a different connection arrangement. Like the juxtaposition of the orders 1 and 3 shows, the n-type regions ( 10 ) or the p-conducting regions ( 20 ) different effective resistors (Rd1, Rd2) "tub resistors" on.

4 represents a layout technical realization of in 3 In cross-section shown protective structure (SS). In a simplified manner, the strip-like metallization ( 40 ), via which the protective structure (SS) can be connected to the first and second potentials (VDD, VSS), to a protected first terminal (PADI) of an integrated circuit, or to an external switchable resistor (R1) or (R2) ,

In 1 to 4 are described starting from the realization of a protective structure (SS) two ways to form two different four-layer arrangements with different electrical properties.

Based on 5 . 6 and 7 It is shown that, starting from a wiring combination of a protective structure (SS) with a first terminal (PADI) of a circuit to be protected, several protection paths can be activated simultaneously. A protective structure (SS) with a corresponding 2 Selected circuitry also allows the activation of multiple protection paths.

Starting from the in 2 The circuitry of a protection structure with connections for the first and second potentials (VDD, VSS) and a first connection of an integrated circuit (PADI) shown in FIG 5 graphically emphasized the protection path between the third terminal of the second potential (VSS) and the first terminal (PADI) of an integrated circuit.

Also starting from 2 shows 6 an effective protection path between the second terminal of the first potential (VDD) and the first terminal (PADI) of an integrated circuit.

Also starting from 2 shows 7 a protection path between the second and third terminals of the first and second potentials (VDD) and (VSS).

Starting from the in 2 Selected circuitry of a multi-potential protection structure and an integrated circuit are shown with schematic symbols in FIG 8th sketched the transistors, from which thyristors can be formed. P1, p2 and p3 denote PNP transistors, n1, n2 and n3 denote NPN transistors, all resulting from the process engineering production of the protective structure (SS).

In 9 is sketchy the acting resistance (Rd1) of the n-conducting area ( 10 ) and the acting resistance (Rd2) of a p-type region ( 20 ) of the protective structure (SS).

10 shows a possible electrical equivalent circuit diagram of the protective structure (SS) 8th , The property of the protection structure (SS) can be influenced by switchable elements or by suitable selection of technological process parameters. For example, the resistors (R1) and (R2) may be formed discretely, as a semiconductor element or as a conductor track. The dopants of the p- or n-type regions ( 10 . 20 ) or the p- or n-type zones ( 11 . 12 . 13 . 21 . 22 . 23 ) can serve as technological parameters, for example, to set switching thresholds or resistance values. Furthermore, it is possible to increase the distance between adjacent doped zones ( 11 . 22 . 23 . 12 . 13 . 21 ), for example by a trench isolation, to set switching thresholds or resistance values.

11 shows a further layout technical embodiment of a protective structure (SS).

An n-type or p-type region has two adjacent to each other and a zone of a p-type or n-type material spaced above or below it by insulation. By way of example, the n-type region ( 10 ) an n-type zone ( 11 ) and two p-type zones ( 22 . 23 ), the p-type region ( 20 ) a sliding zone ( 21 ) and two n-type zones ( 12 . 13 ) on. The example in 11 The illustrated protection structure arrangement can be used when there is a need to realize a high resistance (Rd1) or (Rd2) without sacrificing the protection circuit's response. The, as in 11 shown, laterally arranged p-type zones ( 22 . 23 ) of the n-type area ( 10 ) or the laterally arranged n-type zones ( 12 . 13 ) of the p-type region ( 20 ) increase the effective resistance (Rd1) and (Rd2) of the p- and n-type regions, respectively. On an additional wiring with resistors (R1) and / or (R2), as in 1 to 4 can therefore be dispensed with. The parallel juxtaposed zones ( 22 . 12 ) respectively. ( 23 . 13 ), which are placed with a minimum distance to the diffusion limit, for example to the tub boundary, however, allow an optimal response. 12 shows a further embodiment of a plurality of coupled protective structures (SS) accordingly 11 , If exact coordination between an integrated circuit to be protected and a protective structure is required, it can be achieved by combining a plurality of protective structures (SS), for example as shown in FIG 11 or 12 shown, optimal adjustment can be achieved. Often, protective structures are arranged on the edge of integrated circuits in the vicinity of a connection pad, so-called "PADs", in order not to impair the properties of a circuit or to dispense with a high packing density.

One effective protection against electrostatic charges integrated Circuits or sensitive parts within integrated circuits can be enabled by multi-stage protection structure devices become.

13 shows in sketchy form the arrangement of two resistors (R100) connected protective structures (SS1) and (SS2).

The first stage of the protective structure arrangement, a protective structure (SS1), has been realized near a connection field. The connection field shows as a cut a connection (PAD). A second compared to the first protection structure (SS1) in modified, for example, reduced size trained Protective structure (SS2), located near to protective integrated circuit respectively in the Close to a protected part of an integrated Circuit. Sensitive parts of an integrated circuit can For example, connections to thin-oxide transistors be. In contrast to the protective structure (SS1) in reduced size trained protective structure (SS2) can be simple and space saving inserted into a layout and also has a sensitive Responsiveness to. Also possible are a variety Protective structures connected with resistors (R100) (SS1) and (SS2).

One resistor connected to the protective structures (SS2) and (SS1) (R100) can act as current limiting and keeps the inner Connection (PARI) of a circuit to be protected in operationally safe Limits.

SS, SS1, SS2

protective structure

PAD

part a connection field

PADI

first Connection

VDD

second Connection of a first potential

VSS

third Connection of a second potential

R1, R2

resistance

Rd1, Rd2

resistance

10

n-type area

20

P-type area

11 12, 13

n-type Zone

21 22, 23

P-type Zone

30

isolation

40

conductor path

QUOTES INCLUDE IN THE DESCRIPTION

This list The documents listed by the applicant have been automated generated and is solely for better information recorded by the reader. The list is not part of the German Patent or utility model application. The DPMA takes over no liability for any errors or omissions.

Cited patent literature

• - US 2002/0154463 [0003]

Claims (14)

Integrated circuit having the features: - a first terminal (PADI). A second terminal for a first potential (VDD) and a third terminal for a second potential (VSS); At least two four-layer arrangements ( 23 . 10 . 20 . 13 ; 12 . 20 . 10 . 22 ), which is a common area ( 10 . 20 ) of a first conductivity type ( 10 ) and a second conductivity type ( 20 ), the area ( 10 ) of the first conductivity type a zone ( 11 ) of a first conductivity type and two zones ( 22 . 23 ) of a second conductivity type, to which a first potential (VDD) and the first terminal (PADI) to be protected are connected, the area of the second conductivity type ( 20 ) a zone ( 21 ) of a second conductivity type and two zones ( 12 . 13 ) of a first conductivity type, to which a second potential (VSS) and the first connection (PADI) to be protected are connected, and all zones ( 11 . 22 . 23 . 12 . 13 . 21 ) by an isolation ( 30 ) are spaced from each other. An integrated circuit according to claim 1, wherein two four-layer arrangements ( 23 . 10 . 20 . 13 ; 12 . 20 . 10 . 22 ) are formed as complementary thyristors. Integrated circuit according to one of Claims 1 to 2, in which a four-layer arrangement ( 23 . 10 . 20 . 13 ; 12 . 20 . 10 . 22 ) as a layer sequence from a region of a first conductivity type ( 10 ) having a zone formed therein ( 23 ) of a second conductivity type and an area ( 20 ) of a second conductivity type with a zone formed therein ( 13 ) of a first conductivity type or as a layer sequence from a region of a second conductivity type ( 20 ) having a zone formed therein ( 12 ) of a first type of line and an area ( 10 ) of a first conductivity type having a zone formed therein ( 22 ) of a second conductivity type is realized. Integrated circuit according to one of Claims 1 to 3, in which a four-layer arrangement ( 23 . 10 . 20 . 13 ; 12 . 20 . 10 . 22 ) is coupled to a resistor (Rd1, Rd2) formed in the region of a first conductivity type and / or second conductivity type. Integrated circuit according to Claim 4, in which the size of the resistor (Rd1, Rd2) depends on the geometric dimensions of an insulation (Rd1, Rd2). 30 ) is adjustable. Integrated circuit according to one of claims 1 to 5, wherein the operating point of a four-layer arrangement ( 23 . 10 . 20 . 13 ; 12 . 20 . 10 . 22 ) is adjustable by a resistor (R1, R2). An integrated circuit according to claim 6, wherein the Resistor (Rd1, Rd2) is realized by a line. Integrated circuit according to claim 6, wherein a four-layer arrangement ( 23 . 10 . 20 . 13 ; 12 . 20 . 10 . 22 ) is coupled to a resistor (R1) connected at one end to a first potential (VDD) and at the other end to the zone ( 11 ) of a first type of charge which is present in the area ( 10 ) of a first charge type is formed. Integrated circuit according to claim 6, wherein a four-layer arrangement ( 23 . 10 . 20 . 13 ; 12 . 20 . 10 . 22 ) is coupled to a resistor (R2) connected at one end to a second potential (VSS) and at the other end to the zone (VSS). 21 ) of a second type of charge which is present in the area ( 20 ) of a second charge type is formed. Matrix of a variety of integrated circuits according to any one of claims 1 to 9, wherein a plurality of Four-layer structures is connected in parallel. Matrix of a variety of integrated circuits according to any one of claims 1 to 9, wherein a plurality of Four-layer structures connected in series. Integrated circuit according to one of the claims 1 to 9, wherein a plurality of integrated circuits on one Semiconductor component is summarized. Integrated circuit according to one of the claims 10 to 12, wherein between lines of a plurality of on a Semiconductor Device Integrated Circuits Resistor Elements (R100) are realized. Integrated circuit according to one of the claims 10 to 13, wherein the integrated circuits have different geometric Have sizes.