DE102007028602B4 - Field effect transistors including source / drain regions extending under pillars - Google Patents

Abstract

A field effect transistor comprising: a substrate (100); a column (170) extending away from the substrate (100), the column (170) having a base (152) adjacent the substrate (100), a top end (154) spaced from the substrate (100), and a side wall (145) extending between the base (152) and the top end (154); an insulated gate (155, 160) on the sidewall (145); a first source / drain region (175; 305) in the substrate (100) under the pillar (170) and adjacent to the insulated gate (155, 160); and a second source / drain region (180; 225; 280; 310) which is heavily doped compared to the first source / drain region (175; 305) in the substrate (100) under the pillar (170) and spaced from the insulated gate (155, 160).

Description

FIELD OF THE INVENTION

This invention relates to microelectronic devices and manufacturing methods, and more particularly to field effect transistors (FETs) of an integrated circuit and manufacturing method thereof.

BACKGROUND OF THE INVENTION

Field effect transistors (FETs) of an integrated circuit, often referred to as metal oxide semiconductor field effect transistors (MOSFETs), metal-insulator-semiconductor field effect transistors (MISFETs), insulated gate field effect transistors, or simply MOS / MIS devices, are widely used in integrated circuits Logic, memory, processor or analog circuits and / or other integrated circuits for consumer, commercial and / or other applications. As the integration density of the field effect transistors of an integrated circuit continues to increase, the size of the active region and the channel length thereof are expected to further decrease. With the reduction of the channel length of the transistor, the influence of the source / drain region on the electric field or potential in the channel region could become considerable, resulting in so-called "short channel effects". Moreover, as the active areas become smaller, the channel width may decrease, which may also increase the threshold voltage of the device and / or may lead to other so-called "narrow width effects".

Vertical columnar transistors have been proposed in attempts to reduce these and / or other effects. In a vertical column transistor, a vertical channel may be provided in a column extending from the substrate of an integrated circuit. A vertical column transistor is disclosed in U.S. Patent US 5480838 A entitled "Method Of Manufacturing A Semiconductor Device Having Vertical Transistor With Tubular Double-Gate" by Mitsui. 2 by Mitsui is as 1 reproduced herein. As set forth in the Mitsui abstract, a semiconductor device is disclosed which allows control of its threshold voltage without having to change the materials of its gate electrodes and which allows a high integration density. The semiconductor device comprises a p-doped monocrystalline silicon substrate 1 which has a cylindrical part with inner and outer surfaces and extends in a vertical direction. A first gate electrode 8th and a second gate electrode 10 are on the inner surface and the outer surface of the cylindrical part 2 arranged. A source / drain region 5 is at the upper end of the cylindrical part 2 formed while a source / drain region 3 on the inner bottom surface at the lower part of the cylindrical part 2 is trained. Therefore, the cylindrical part 2 be used as a channel region of an MIS field effect transistor. The threshold voltage of the transistor can be easily controlled by applying separate voltages to the two gate electrodes, to the first and second electrodes.

Another vertical column field effect transistor is disclosed in the US patent US 6015725 A entitled "Vertical Field Effect Transistor and Manufacturing Method Thereof" by Hirayama. 2 Hirayama is as 2 reproduced herein. As stated in the abstract of Hirayama, become a vertical field effect transistor 1 and a manufacturing method thereof, wherein a buried layer 3 a conductivity type, that of a substrate 2 is opposite, to a predetermined depth in the substrate 2 is formed by ion implantation. The lower end of the recess 2a to form a projection 2 B on the substrate 2 lies in a corresponding buried layer 3 , The width of the recess 2a is set smaller than the width of the buried layer 3 , The surface of the projection 2 B and the lower end of the recess 2a become by impurity regions 4a . 4b ; 5a . 5b formed, which form a source or a drain. A channel length L of the channel region, which is on the side wall of the projection 2 B is formed by the distance between the buried layer 3 and the impurity region 5a . 5b on the surface of the projection 2 B Are defined.

Unfortunately, the vertical column transistors described above may also have a gate-induced drain leakage current (GIDL), which may also reduce the power of the vertical column transistor.

From the publication US 2002/0175365 A1 For example, a vertical field effect transistor and a method of manufacturing the same is known in which a buried layer having a conductivity type opposite to that of the substrate is formed to a predetermined depth in the substrate by ion implantation. The bottom of a recess for forming a projection on the substrate is disposed inside the corresponding buried layer. The width of the recess is less than the width of the buried layer. Impurity regions forming a source and a drain region are formed in the surface of the protrusion and in the bottom surface of the recess. A channel length of the channel region formed on the side walls of the protrusion is defined by the distance between the buried layer and the impurity regions at the surface of the protrusion.

SUMMARY OF THE INVENTION

Field effect transistors according to the present invention comprise a substrate and a pillar extending away from the substrate. The pillar has a base adjacent the substrate, an upper end spaced from the substrate, and a sidewall extending between the base and the upper end. An insulated gate is provided on the sidewall. A first source / drain region is provided in the substrate below the pillar and adjacent to the insulated gate. A second source / drain region, which is heavily doped compared to the first source / drain region, is provided in the substrate under the pillar and spaced from the insulated gate.

In some embodiments, the column is an I-shaped column that is narrower in an intermediate portion between the base and top compared to the portion adjacent the base and top, such that the side wall has a recessed intermediate portion between the base and the top having the upper end. The insulated gate may include an insulating layer extending on the recessed portion and a gate electrode on the insulating layer spaced from the sidewall. A trench isolation region may also be provided in the substrate outside the pillar, with the first and second source / drain regions extending in the substrate adjacent the trench isolation region.

In some embodiments, the second source / drain region extends farther to a center axis of the pillar than the first source / drain region. In other embodiments, the first source / drain region extends farther to the central axis of the pillar than the second source / drain region. In further embodiments, a third source / drain region is also provided in the substrate under the pillar and spaced from the first source / drain region. The third source / drain region is lightly doped compared to the second source / drain region. In these embodiments, the second source / drain region may extend farther to the central axis of the pillar than the first and third source / drain regions.

Moreover, in some embodiments, the first and second source / drain regions may extend below the recessed portion. In other embodiments, the first source / drain region may extend below the recessed portion and the second source / drain region may extend only partially below the recessed portion. In still other embodiments wherein the first, second, and third source / drain regions are provided, the second source / drain region may extend below the recessed part, and the first and third source / drain regions may extend. Region only partially extend under the recessed part.

In each of the embodiments described above, a sidewall spacer may be provided on the gate electrode spaced from the insulating layer. In addition, the trench isolation region in the substrate may extend from outside the pillar to the sidewall spacer. Finally, in each of the above embodiments, a fourth source / drain region may be provided in the column adjacent the top.

Other embodiments of the present invention may provide field effect transistors that provide an I-shaped pillar, but need not have the first and second source / drain regions in the substrate under the pillar. In particular, field effect transistors according to these embodiments may include a substrate and an I-shaped pillar extending away from the substrate. The I-shaped pillar has a base adjacent the substrate, an upper end spaced from the substrate, and an intermediate portion between the base and the upper end which is narrower than the base and the upper end. An insulated gate is provided on the intermediate part. A source / drain region is provided in the substrate adjacent the base.

In any of these embodiments, the insulated gate may include an insulating layer and a gate electrode on the insulating layer, and / or a trench isolation region may be provided in the substrate, as already described. Moreover, in any of these embodiments, the source / drain region may include a first source / drain region, a second source / drain region, and / or a third source / drain region, as previously described. A sidewall spacer and / or a fourth source / drain region may also be provided, as described above.

Field effect transistors may be fabricated according to various embodiments of the present invention by etching a plurality of spaced apart columns in an integrated circuit substrate. The pillars have a base adjacent the substrate, an upper end spaced from the substrate, and an intermediate portion between the base and the upper end which is narrower than the base and the upper end. Isolated gates will be on the Intermediate parts formed. Ions are implanted in the substrate between the spaced apart columns to form source / drain regions. Annealing may then be performed to diffuse at least some of the implanted ions under the columns. Some of the ions may already be under the columns prior to annealing.

In some embodiments, the source / drain regions are first source / drain regions, and the methods may further include etching the substrate between the spaced apart columns to form a plurality of spaced apart trenches, and implanting ions into the trenches to form second ones Source / drain regions that are more heavily doped than the first source / drain regions in the substrate, among the first source / drain regions. In some embodiments, the ions are implanted into the trenches at an oblique angle relative to the substrate.

In other embodiments, ions are implanted into the substrate between the spaced apart columns to form source / drain regions by performing a first ion implantation for implanting ions into the substrate between the spaced apart columns to form first source / drain regions Performing a second ion implantation at higher energy than that of the first ion implantation to implant ions into the substrate between the spaced apart pillars and below the first source / drain regions to form second source / drain regions. The order of these ion implantations may also be reversed. Moreover, after performing these ion implantations, the substrate may be etched between the spaced apart pillars to form a plurality of spaced apart trenches.

In yet other embodiments, spacers are formed on the insulated gates spaced from the pillars, between implanting ions into the substrate between the spaced apart pillars to form first source / drain regions, and etching the substrate between them spaced apart pillars for forming the spaced apart trenches.

In yet other embodiments, implanting ions into the substrate to form source / drain regions is performed by performing a first ion implantation to implant first ions into the substrate between the spaced apart columns and by performing a second ion implantation with higher energy and higher density than the first ion implantation for implanting second ions into the substrate between the spaced apart columns, the second ions having a shorter diffusion length than the first ions.

Annealing is then performed to form second source / drain regions in the substrate under the pillars and spaced therefrom, first source / drain regions that are lightly doped compared to the second source / drain regions, between the second source / drain Regions and the pillars, as well as third source / drain regions, which are lightly doped compared to the second source / drain regions, under the pillars and spaced from the first source / drain regions. The substrate may then be etched between the spaced apart pillars to form spaced apart trenches. An insulating layer may be formed in the spaced apart trenches.

BRIEF DESCRIPTION OF THE DRAWINGS

1 is a reprint of 2 of U.S. Patent 5,480,838 ,

2 is a reprint of 2 from U.S. Patent 6,015,725 ,

3A - 3J 10 are sectional drawings of the field effect transistors according to first embodiments of the present invention at intermediate manufacturing steps according to first embodiments of the present invention.

4A - 4B 10 are sectional drawings of field effect transistors according to second embodiments of the present invention at manufacturing intermediate steps according to second embodiments of the present invention.

5A - 5B 10 are sectional drawings of field effect transistors according to third embodiments of the present invention at intermediate manufacturing steps according to third embodiments of the present invention.

6A - 6B 10 are sectional drawings of field effect transistors according to fourth embodiments of the present invention at intermediate manufacturing steps according to fourth embodiments of the present invention.

7 Graphically illustrates the gate voltage versus the leakage current for vertical field effect transistors according to embodiments of the present invention.

DETAILED DESCRIPTION

The invention will be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. However, the invention may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, the disclosed embodiments are provided to make the disclosure complete and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of the layers and regions may be exaggerated for clarity. Moreover, each embodiment described and illustrated herein also includes its complementary conductivity type embodiment. Same numbers refer to the same elements throughout.

It should be understood that when an element or layer is referred to as being "on," "connected to," and / or "coupled to" another element or layer, then it may be directly connected, coupled, or coupled to the other element or layer, or intervening elements or layers may be present. However, if an element is referred to as being "directly on," "directly connected to," and / or "directly coupled to" another element or layer, then there are no intervening elements or layers. As used herein, the term "and / or" may include any or all combinations of one or more of the associated listed items.

It should be understood that although the terms first, second, third, etc. may be used herein to refer to various elements, components, regions, layers and / or sections, these elements, regions, layers and / or sections are not should be limited by these expressions. These terms can be used to distinguish one element, component, region, layer, or section from another region, layer, and / or section. For example, a first element, component, region, layer, and / or section, discussed below, could be termed a second element, component, region, layer, and / or section, without departing from the teachings of the present invention.

Spatially relative expressions such as "Lower," "lower," "above," "upper," and the like, may be used herein to facilitate illustration To describe element and / or the relationship of a feature to another element (s) and / or feature (s), as illustrated in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations described in the figures. If z. For example, when the device in the figures is turned over, elements described as "below" other elements or features would then be oriented "above" the other elements or features. Therefore, the exemplary term "under" may include both an orientation above and below. The device may also be oriented differently (rotated 90 ° or in other orientations) and the spatially relative descriptions used herein interpreted accordingly.

As used herein, a second region is below a first region when it is outside the first region but extends within a projection of the first region. Conversely, a second region is not below a first region if it is entirely outside a projection of the first region. Therefore, z. For example, a source / drain region in the substrate under a pillar extending away from the substrate when the source / drain region extends within a projection of the pillar into the substrate. The source / drain region may be contained entirely within the projection of the column, but may also extend outside the projection and may also extend into the column itself. Conversely, a source / drain region is not considered to be under a column if it is completely transversely offset from the projection of the column into the substrate. Moreover, the term "below" indicates a relationship of one layer or region to another layer or region relative to the substrate as illustrated in the figures.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the individual terms "a" and "the" are meant to include plurals, unless the context clearly dictates otherwise indicates. It should also be understood that the terms "comprising," "comprising," "includes," or "including," when used in this specification, includes the presence of indicated features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more features, integers, steps, operations, elements, components, and / or groups thereof.

Exemplary embodiments of this invention are described herein with reference to sectional drawings which are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations of the forms of illustrations as a result of e.g. B. of manufacturing techniques and / or tolerances can be expected. Therefore, the disclosed example embodiments of the invention should not be construed as limited to particular forms of regions illustrated herein unless expressly so defined herein, but are intended to include deviations from shapes that are described, for example, in the art. B. resulting from the production include. For example, an implanted region, shown as a rectangle, will typically have more rounded or curved features and / or have a gradient of implant concentration at its corners than will have a binary change from implanted to unimplanted region. Similarly, a buried region formed by implantation may result in implantation in the region between the buried region and the surface through which the implantation occurred. Therefore, the regions illustrated in the figures are schematic in nature and their shapes are not intended to describe the actual shape of a region or device and are not intended to limit the scope of the invention except as expressly stated herein so defined.

Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It should be further understood that such terms as used in commonly used dictionaries are to be interpreted as having a meaning consistent with meaning in the context of the relevant art and the present disclosure and they should not are interpreted in an idealized or oversimplified sense unless expressly so defined herein.

3A - 3J 10 are sectional drawings of manufacturing methods of field effect transistors according to first embodiments of the present invention and field effect transistors thus produced. Referring to 3A , may be a buffer oxide layer 105 on a substrate 100 be formed by means of chemical vapor deposition, thermal oxidation and / or other conventional processes. The substrate 100 may include a single element and / or a composite semiconductor volume substrate, or may include a single element and / or a composite semiconductor layer on another substrate, which is commonly referred to as semiconductor-on-insulator (SOI) technology, and / or other substrates normally used in microelectronic device fabrication.

Still referring to 3A , can be a mask layer 110 which is often referred to as a "hard mask" on a buffer oxide layer 105 be formed by means of chemical vapor deposition and / or other conventional techniques. The masking layer material 110 may be a different etch rate than the buffer oxide layer 105 to have. A photoresist pattern 115 gets on the mask layer 110 formed by a conventional photo-imaging process.

Referring to 3B become first trenches 130 by etching into the mask layer 110 and the buffer layer 105 formed to a patterned mask layer and a patterned buffer layer 120 to form as shown. As also shown, etching of the first trenches may occur 130 partly in the substrate 100 continue. The photoresist 115 can then be removed. Other conventional etching techniques may be used.

Referring to 3C , becomes a protective layer 135 on the walls of the first ditch 130 trained, z. By means of a conventional chemical vapor deposition and etchback process. The protective layer may contain an oxide and / or nitride. The protective layer 135 may be helpful in forming an I-pillar, as described below. However, the protective layer needs 135 not to be used in other embodiments.

Referring to 3D , becomes the substrate 100 with the help of the protective layer 135 etched as an etch mask, around second trenches 140 form a plurality of spaced pillar structures 148 define. Other etching techniques may be used.

Referring to 3E , a combination of dry etching and wet etching (and / or other conventional techniques) may be performed to form an intermediate portion of the sidewalls of the pillar structures 148 so take away, that thereby a recessed part 145 the side walls is formed. Accordingly, an I-shaped pillar structure 153 formed with a base 152 which are attached to the substrate 100 adjacent, one from the substrate 100 spaced upper end 154 and an intermediate part 150 between the base 152 and the upper end 154 which is narrower than the base 152 and the top end 154 is. The intermediate part 150 includes a recessed side wall 145 , The intermediate part 150 may define a channel region, as described in detail below. Thus, an I-shaped pillar structure 153 educated. Other techniques for forming an I-shaped column can also be used.

Referring to 3F , becomes a gate insulation layer 155 on the recessed side wall 145 with the help of z. As chemical vapor deposition and etchback formed. The gate insulation layer 155 can conventional gate dielectrics, such as. For example, silica and / or high dielectric constant materials such. As Hf ₂ O ₃ , Al ₂ O ₃ and / or other materials include. Other techniques, such. As thermal oxidation, can also be used.

Referring to 3G , becomes a gate electrode 160 on the gate insulation layer 155 z. B. formed by chemical vapor deposition and etch back and / or by other techniques. The gate electrode 160 may include polysilicon, metal and / or other conventional materials used for gate electrodes. Thus, the gate insulation layer form 155 and the gate electrode 160 an insulated gate on the recessed side wall 145 , The pillars with the isolated gates on the recessed sidewalls thereof are indicated by the reference numeral 170 characterized.

Still referring to 3G , becomes a first source / drain region 175 by implanting ions between the columns 170 as by the arrows 172 shown, trained. In some embodiments, N-type ions are implanted to lightly doped first (N) source / drain regions 175 with the help of orthogonal ion implantation. In other embodiments, oblique implantation may be used. In some embodiments, prior to performing the first ion implantation 172 Sidewall spacers on the sidewalls of the columns 170 be trained and then after the ion implantation 172 be removed. The first source / drain regions 175 can get under the pillars 170 ie within a projection 176 the columns 170 , extend. In other embodiments, the first source / drain regions may be 175 not before a later annealing under the columns 170 extend.

Referring to 3H , Now the substrate is between the spaced pillars 170 etched to third trenches 185 to build. In some embodiments, the sidewall spacers shown in FIG 3G optionally formed, are used to the third trenches 185 so they are narrower than the second trenches 140 are, as in 3H shown. Other techniques can also be used to access the third trenches 185 train.

Then, as in 3H shown become ions 182 in the third trenches 185 implanted to second source / drain regions 180 in the substrate 100 under the columns 170 and among the first source / drain regions 175 and which are more heavily doped (N +) than the first source / drain regions 175 are. This second ion implantation 182 can be at an oblique angle, as in 3H shown, so that the more heavily doped second source / drain regions 180 continue to a central axis 174 the columns 170 can extend as the first source / drain regions 175 , The second ions 182 can be deeper than the first ions by implanting at a higher energy than the first ions 172 be implanted. In other embodiments, orthogonal implantation and / or different energy may be used.

Annealing may then be performed to obtain the final source / drain structure which is in 3H is shown, wherein the first source / drain regions 175 in the substrate under the column, ie within the projections 176 the column 170 and to the isolated gate 155 / 160 adjacent, extend.

Second source / drain regions 180 compared to the first source / drain regions (N-) 175 are heavily doped (N +), are also present in the substrate 100 under the column 170 are provided and are spaced from the insulated gate 155 / 160 , As well as in 3H In some embodiments, the second source / drain regions 180 continue to the central axis 174 the column 170 extend as the first source / drain regions 175 , It should be understood that in other embodiments, a separate annealing need not be performed.

Referring to 3I , now becomes an insulation layer 190 z. B. of silicon dioxide in the third trenches 185 formed by means of chemical vapor deposition and etch back and / or other conventional processes. In some embodiments, the insulating layer fills 190 the trenches 185 , As in 3I shown, the first and second source / drain regions can 175 . 180 in the substrate 100 next to the trench isolation layer 190 extend.

Finally, referring 3J , the transistor may be formed by formation of source / drain regions 205 (also referred to as fourth source / drain regions ( 205 ) in the upper end 154 by implantation of third ions 206 in the as shown by a photoresist 200 masked substrate completed become. Orthogonal implantation as shown and / or oblique implantation may be used. Before and / or after the formation of the source / drain regions 205 can be a wordline and / or another region (regions) 192 in the second trenches 144 can be formed, and the second trenches can also by a dielectric intermediate layer 195 filled using conventional techniques.

Accordingly illustrated 3J also field effect transistors according to first embodiments of the present invention, which is a substrate 100 and a pillar 170 include, moving away from the substrate 100 extends, with the column one to the substrate 100 adjacent base 152 , one from the substrate 100 spaced upper end 154 and a side wall 145 that are between base 152 and upper end 154 extends, includes. An isolated gate 155 / 160 is on the sidewall 145 intended. A first source / drain region 175 is in the substrate 100 under the column 170 and adjacent to the isolated gate 155 / 160 intended. A second source / drain region 180 compared to the first source / drain region 175 is heavily doped, is in the substrate 100 under the column 170 and spaced from the isolated gate 155 / 160 intended.

As well as in 3J In some embodiments, the column is shown 170 an I-shaped pillar between the base 152 and the upper end 154 narrower is compared to adjacent to the base 152 and the top end 154 so that the recessed sidewall 145 an intermediate part 150 between the base 152 and the upper end 154 defines and the insulated gate an insulating layer 155 includes, referring to the intermediate part 150 extends and a gate electrode 160 on the insulating layer 155 spaced from the side wall 145 , The base 152 and the top end 154 may be as wide or, in some embodiments, may be of different widths. In other embodiments, a trench isolation region 190 in the substrate 100 outside the pillar 170 and the first and second source / drain regions 175 / 180 extend into the substrate adjacent to the trench isolation region 190 , In addition, the second source / drain regions 180 in some embodiments, further to a central axis 174 the column 170 as the first source / drain regions 170 extend. As well as in 3J As shown, in some embodiments, the first and second source / drain regions extend 175 both to below the intermediate part 150 , Source / drain regions 205 can also in the column 170 adjacent to the upper part 154 be provided.

4A and 4B FIG. 4 are sectional views of methods of fabricating field effect transistors according to second embodiments of the present invention and field effect transistors thus fabricated. From a structural point of view, these second embodiments may have the same structures as those of the first embodiments of FIGS 3A - 3J produce. However, the manufacturing processes may differ.

Especially referring to 4A , the operations of the 3A - 3G be executed. These operations will not be described again for the sake of brevity. Then, as in 4A shown a second implantation 220 at a higher energy than at the first implantation 172 of the 3G be performed to second source / drain regions 205 form, compared to the first source / drain regions 175 are heavily doped, located in the substrate 100 under the columns 170 and spaced from the isolated gates 155 / 160 are located. It should also be understood that implantation 220 of the 4A before implantation 172 of the 3G can be carried out. Orthogonal implantation may be used, although oblique implantation (s) may be used in other embodiments.

Referring to 4B , become the third trenches 210 formed, similar to the formation of the third trenches 185 in 3H , An annealing can then be carried out. The transistor can then be completed, as already in 3I and 3J described.

5A and 5B 10 are sectional views of the methods of fabricating field effect transistors according to the third embodiment of the present invention and field effect transistors thus fabricated. Before performing the operations of 5A can the operations of 3A to 3G to thereby execute the lightly doped (N) first source / drain regions 175 train. These operations will not be described again for the sake of brevity.

As in 5A then become gate spacers 250 on the pillars 170 formed, for example, by means of a conventional chemical vapor deposition and etchback process. The gate spacers 250 may include an oxide, nitride, and / or conventional spacer materials. Other conventional gate spacer fabrication techniques may be used.

Referring to 5B , then becomes a third ditch 270 with the help of the gate spacer 250 as a mask, for example by means of a conventional dry etching process. A second implantation 182 of ions can be at a higher energy than at the first implantation 172 be performed and at an oblique angle as in 5B shown to second source / drain structures 280 under the first source / drain regions 175 which are more heavily doped (N +) to form. In other embodiments, orthogonal implantation may be used. An optional anneal may then take place to control the final source / drain structures present in 5B are shown to produce. As in 5B 3, the first source / drain regions extend in these three embodiments 175 continue to a central axis 174 the columns 170 as the second source / drain regions 280 because the second implantation 180 through the gate spacer 250 and / or at an oblique angle. The structure can then as in the 3I and 3J was completed. As in 5B As shown in these embodiments, the first source / drain regions extend below the intermediate portion 150 whereas the second source / drain regions 280 only partially below the intermediate part 150 extend. In addition, as in 5B shown in these embodiments may be the trench 270 up to the sidewall spacer 250 extend so that the subsequently formed layer isolation region 190 in the substrate 100 from outside the pillar 270 up to the sidewall spacers 250 can extend.

Finally are 6A and 6B Cross-sectional views illustrating the fabrication of field effect transistors according to fourth embodiments of the present invention and field effect transistors thus produced. Before performing the operations in 6A can the operations which take place in the 3A - 3G are shown executed. These operations will not be discussed again for the sake of brevity.

Then, as in 6A shown a second implantation 310 performed with higher energy and higher density than the first ion implantation 172 to get second ions into the substrate 100 between the spaced columns 170 to implant, as in region 305 shown. In some embodiments, the second ions have a shorter diffusion length than the first ions. For example, the first ions 172 Phosphorus ions and the second ions 310 Be arsenic ions. As well as in 6A In some embodiments, the second ion implantation may be shown 310 be performed at an oblique angle, while in other embodiments orthogonal implantation can be used. It should also be understood that the order of execution of the first and second ion implantations may be reversed.

Referring to 6B , then an annealing is performed to the first ions 175 above and below the second ions 305 to diffuse, thereby forming second source / drain regions 310 (N +) under the columns 170 and spaced therefrom first source / drain regions 305 compared to the second source / drain regions 310 weakly doped (N-) are between the second source / drain regions 310 and the columns 170 and third source / drain regions 315 which compared to the second source / drain regions 310 are lightly doped (N-) under the second source / drain regions 310 and spaced from the first source / drain regions 305 to build. As in 6B Finally, a third ditch can be shown 320 etched as already described above. The transistor can be completed as described above in connection with 3J described.

In addition, the second source / drain regions can become 310 in some embodiments, as in 6B described, further to a central axis 174 of the column extend as the first and third source / drain regions 305 respectively. 315 , In addition, as well as in 6B In some embodiments, the second source / drain region extends 310 until under the intermediate part 150 the columns 170 whereas the first and third source / drain regions 305 . 315 only partially to below the intermediate parts 150 the columns 170 extend.

7 graphically illustrates the gate voltage plotted against the leakage current for a vertical field effect transistor of FIG 6B ( I ) and a vertical field effect transistor of 3J ( II ) according to some embodiments of the present invention. As in 7 For low values of the gate voltage, a reduction of the leakage current can be shown for embodiments of the 3J to be obtained.

As described herein, some embodiments of the present invention may provide first and second source / drain regions in the substrate that extend beneath the columns. These extended (N +) and (N-) source / drain regions may reduce gate-induced drain leakage current compared to conventional vertical field-effect transistors, with one or both of the source / drain regions being out of the column and not extending below the column ,

Claims (39)

Field effect transistor comprising: a substrate ( 100 ); a column ( 170 ) extending from the substrate ( 100 ) extends away, the column ( 170 ) one to the substrate ( 100 ) adjacent base ( 152 ), one of the Substrate ( 100 ) spaced upper end ( 154 ) and a side wall ( 145 ), which are located between the base ( 152 ) and the upper end ( 154 ); an isolated gate ( 155 . 160 ) on the side wall ( 145 ); a first source / drain region ( 175 ; 305 ) in the substrate ( 100 ) under the column ( 170 ) and to the isolated gate ( 155 . 160 ) adjacent; and a second source / drain region ( 180 ; 225 ; 280 ; 310 ) compared to the first source / drain region ( 175 ; 305 ) is heavily doped in the substrate ( 100 ) under the column ( 170 ) and spaced from the isolated gate ( 155 . 160 ). Field effect transistor according to claim 1, wherein the column ( 170 ) is an I-shaped column which extends between the base ( 152 ) and the upper end ( 154 ) is narrower compared to adjacent to the base ( 152 ) and the upper end ( 154 ), so that the side wall ( 145 ) a recessed part between the base ( 152 ) and the upper end ( 154 ) and wherein the isolated gate ( 155 . 160 ) an insulating layer ( 155 ) located on the recessed part and a gate electrode ( 160 ) on the side wall ( 145 ) spaced, insulating layer ( 155 ). Field effect transistor according to claim 1, further comprising a trench isolation region ( 190 ) in the substrate ( 100 ) outside the column ( 170 ) and where the first ( 175 ; 305 ) and the second source / drain region ( 180 ; 225 ; 280 ; 310 ) into the substrate ( 100 ), adjacent to the trench isolation region ( 190 ). Field effect transistor according to claim 1, wherein the second source / drain region ( 180 ; 225 ; 280 ; 310 ) continues to a central axis ( 174 ) of the column ( 170 ) extends as the first source / drain region ( 175 ; 305 ). Field effect transistor according to claim 1, wherein the first source / drain region extends further to a central axis ( 145 ) of the column ( 170 ) extends as the second source / drain region. Field effect transistor according to claim 1, further comprising a third source / drain region ( 315 ), which compared to the second source / drain region ( 310 ) is lightly doped, in the substrate ( 100 ) under the column ( 170 ) and under the second source / drain region ( 310 ). Field effect transistor according to claim 6, wherein the second source / drain region ( 310 ) continues to a central axis ( 145 ) of the column ( 170 ) extends as the first ( 305 ) and the third source / drain region ( 315 ). Field effect transistor according to claim 2, wherein the first ( 175 ; 305 ) and the second source / drain region ( 180 ; 225 ; 280 ; 310 ) both extend below the recessed part. Field effect transistor according to claim 2, wherein the first source / drain region ( 175 ; 305 ) extends under the recessed part; and wherein the second source / drain region ( 180 ; 225 ; 280 ; 310 ) extends only partially below the recessed part. Field effect transistor according to claim 6, wherein the second source / drain region ( 310 ) extends under the recessed part; and where the first ( 305 ) and the third source / drain region ( 315 ) extend only partially below the recessed part. Field effect transistor according to claim 2, further comprising a sidewall spacer ( 250 ) on the gate electrode ( 160 ) spaced from the insulating layer ( 155 ). Field effect transistor according to claim 3, further comprising a sidewall spacer ( 250 ) on the side wall ( 145 ), wherein the trench isolation region ( 190 ) in the substrate ( 100 ) from outside the column ( 170 ) extends to the sidewall spacer. Field effect transistor according to claim 1, further comprising a fourth source / drain region ( 205 ) in the column ( 170 ) ( 170 ) adjacent to the upper end ( 154 ). Field effect transistor according to claim 1, wherein: the column ( 170 ) Is I-shaped and an intermediate part ( 150 ) between the base ( 152 ) and the upper end ( 154 ), which is narrower than the base ( 152 ) and the upper end ( 154 ); and the isolated gate ( 155 . 160 ) on the intermediate part ( 150 ) is trained. Field effect transistor according to claim 14, wherein the insulated gate ( 155 . 160 ) an insulating layer ( 155 ) on the intermediate part ( 150 ) and a gate electrode ( 160 ) on the gate insulating layer ( 155 ), spaced from the I-shaped column ( 170 ). Field effect transistor according to claim 14, further comprising a trench isolation region ( 190 ) in the substrate ( 100 ) outside the I-shaped column ( 170 ) and wherein the source / drain region in the substrate ( 100 ) adjacent to the trench isolation region ( 190 ). A field effect transistor according to claim 14, wherein: the first source / drain region ( 175 ; 305 ) adjacent to the base ( 152 ) is trained; and the second source / drain region ( 180 ; 225 ; 280 ; 310 ), spaced from the base ( 152 ) is trained. Field effect transistor according to claim 17, wherein the second source / drain region ( 180 ; 225 ; 280 ; 310 ) continues to a central axis ( 174 ) of the I-shaped column ( 170 ) extends as the first source / drain region ( 175 ; 305 ). A field effect transistor according to claim 17, wherein said first source / drain region extends further to a central axis ( 174 ) of the I-shaped column ( 170 ) extends as the second source / drain region. Field effect transistor according to claim 14, wherein: the first source / drain region ( 305 ) adjacent to the base ( 152 ) is trained; the second source / drain region ( 310 ) spaced from the base ( 152 ) is trained; and the field effect transistor further comprises a third source / drain region ( 315 ) compared to the second source / drain region (FIG. 310 ) is lightly doped, and that in the substrate ( 100 ) under the I-shaped column ( 170 ) and spaced from the first source / drain region ( 305 ) is trained. Field effect transistor according to claim 20, wherein the second source / drain region ( 310 ) continues to a central axis ( 174 ) of the I-shaped column ( 170 ) extends as the first and the third source / drain region ( 305 . 315 ). Field effect transistor according to claim 17, wherein the first and the second source / drain region are both under the intermediate part ( 150 ). Field effect transistor according to claim 17, wherein the first source / drain region ( 175 ; 305 ) under the intermediate part ( 150 ) extends; and wherein the second source / drain region ( 180 ; 225 ; 280 ; 310 ) extends only partially under the intermediate part. Field effect transistor according to claim 20, wherein the second source / drain region ( 310 ) under the intermediate part ( 150 ) extends; and wherein the first and third source / drain regions ( 305 . 315 ) only partially under the intermediate part ( 150 ). A field effect transistor according to claim 15, further comprising a sidewall spacer (10). 250 ) on the gate electrode ( 160 ) spaced from the insulating layer ( 155 ). Field effect transistor according to claim 14, further comprising a fourth source / drain region ( 205 ) in the I-shaped column ( 170 ) adjacent to the upper end ( 154 ). A method of fabricating a field effect transistor, comprising: etching a plurality of spaced apart columns ( 170 ) in a substrate ( 100 ) of an integrated circuit, the columns ( 170 ) one to the substrate ( 100 ) adjacent base ( 152 ), one from the substrate ( 100 ) spaced upper end ( 154 ) and an intermediate part ( 150 ) between the base ( 152 ) and the upper end ( 154 ), which is narrower than the base ( 152 ) and the upper end ( 154 ), Forming isolated gates ( 155 . 160 ) on the intermediate parts ( 150 ); and implanting ions into the substrate ( 100 ) between the spaced apart pillars ( 170 ) for forming source / drain regions ( 175 ; 205 ; 305 ). The method of claim 27, wherein the annealing followed by annealing to diffuse at least some of the ions implanted under the columns ( 170 ). The method of claim 27, wherein the source / drain regions comprise first source / drain regions ( 175 ), the method further comprising: etching the substrate ( 100 ) between the spaced apart pillars ( 170 ) for forming a plurality of spaced trenches (US Pat. 185 ); and implanting ions into the trenches ( 185 ) for forming second source / drain regions ( 280 ), which are more heavily doped than the first source / drain regions ( 175 ), in the substrate ( 100 ) among the first source / drain regions ( 175 ). The method of claim 29, wherein implanting ions into the trenches ( 185 ) for forming the second source / drain regions ( 180 ) at an oblique angle relative to the substrate ( 100 ) is carried out. The method of claim 27, wherein said implanting comprises: performing a first ion implantation to implant ions into said substrate ( 100 ) between the spaced apart pillars ( 170 ) for forming first source / drain regions ( 175 ); and performing a second ion implantation with higher energy than the first ion implantation for implanting ions into the substrate ( 100 ) between the spaced apart pillars ( 170 ) and below the first source / drain regions ( 175 ) for forming second source / drain regions ( 310 ). The method of claim 31, further comprising: Etching the substrate ( 100 ) between the spaced apart pillars ( 170 ) for forming a plurality of spaced trenches (US Pat. 210 ; 270 ). The method of claim 29, wherein the following is performed between implanting ions into the substrate ( 100 ) between the spaced apart pillars ( 170 ) for forming first source / drain regions ( 175 ) and the etching of the substrate ( 100 ) between the spaced apart pillars ( 170 ) for forming a plurality of spaced trenches (US Pat. 270 ): Forming spacers ( 250 ) on the isolated gates ( 155 . 160 ) spaced from the columns ( 170 ). The method of claim 27, wherein the implanting comprises: performing a first ion implantation to implant first ions into the substrate ( 100 ) between the spaced apart pillars ( 170 ); Performing a second ion implantation with higher energy and higher density than the first ion implantation for implanting second ions in the substrate ( 100 ) between the spaced apart pillars ( 170 ), wherein the second ions have a shorter diffusion length than the first ions; and annealing to form second source / drain regions ( 310 ) in the substrate ( 100 ) under the columns ( 170 ) and spaced apart first source / drain regions ( 305 ) compared to the second source / drain regions ( 310 ) are lightly doped, between the second source / drain regions ( 310 ) and the columns ( 170 ) as well as third source / drain regions ( 315 ) compared to the second source / drain regions ( 310 ) are more easily doped under the columns ( 170 ) and spaced from the first source / drain regions ( 305 ). The method of claim 34, further comprising: etching the substrate ( 100 ) between the spaced apart pillars ( 170 ) for forming a plurality of spaced trenches (US Pat. 320 ). The method of claim 30, further comprising: forming an insulating layer ( 190 ) in the spaced apart trenches ( 185 ). The method of claim 32, further comprising: forming an insulating layer in the spaced apart trenches ( 210 ; 270 ). The method of claim 35, further comprising: forming an insulating layer in the spaced apart trenches ( 320 ). The method of claim 27, further comprising: forming source / drain regions ( 205 ) in the columns ( 170 ) adjacent to the upper ends ( 154 ).

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