DE102007024410B4 - Method for operating a counter and counter circuitry - Google Patents

Abstract

Method for operating a counter, in which a current counter reading is stored in the form of a group of binary memory words in a memory, wherein the following method steps are carried out for incrementing or decrementing the counter reading:
a) reading the memory words (SW) of the counter reading from the memory (2),
b) rearranging bits of the memory words (SW) using an inverse permutation rule to generate a group of third data words (DW ₃ ), each representing in an extended Gray code coded digits of a count coded in a Gray code,
c) converting the individual third data words (DW ₃ ) using an inverse numerical coding rule into second data words (DW ₂ ), which respectively represent the digits of the count coded in the Gray code,
d) converting the group of second data words (DW ₂ ) using an inverse counter encoding rule to generate a group of first data words (DW ₁ ) each representing the digits of the count (ZS) defined by an ordinal number to a base n, ...

Description

The The invention relates to a method for operating a counter, in a current meter reading each in the form of a group of binary memory words in one nonvolatile Memory is deposited. About that In addition, the invention relates to a counter circuit arrangement, too short called "counter", with a nonvolatile Memory to a current count each to be deposited in the form of a group of binary memory words, and a computing unit with a working memory, for example a programmable logic device or a programmable one Processor.

Counter of mentioned type are widely used in modern controls and regulations used. To keep the meter readings persistent and independent From the power supply, these are often in rewritable Read-only memory such. B. stored EEPROMs whose memory cells a by the number of writes dependent limited Have lifespan. The counters be in many cases used with an increment or decrement of "1." In a conventional one Binary counter is So the value "1" continues to count added or subtracted and this new meter reading persistently stored. It changes the least significant digit of the counter most often, the changes at the rest Numbers take logarithmically to the selected base and number the digits of the counter from. Become after a count only those data words of the count are stored, the modified Numerals of the counter included, so the life of the meter through the life that memory cell determines which is the least significant digit contains.

In the DE 101 44 077 A1 A method is provided to increase the useful life of the meter by skillfully storing the data in read-only memory. With this method, with simple incrementing or decrementing, the changes to the least significant digit of a counter reading are equally distributed to all the memory words of the counter. So z. For example, given a selected base of 16 for the digits of a counter whose digits can be stored in four memory words, the least significant digit is changed at least 16 times more frequently than any other digit. These changes are then distributed equally in all memory words. However, at every sixteenth write, the memory word containing the second digit is also changed, at each 256th write, that memory word containing the third digit, and so forth. In the worst case, even all data words of a counter are changed simultaneously. For this reason, the achieved in the DE 101 44 077 A1 For example, the algorithm does not uniformly distribute the writes to the memory words, and the lifetime of the counter is again limited by the one word word that is changed most frequently.

The DE 691 32 626 T2 describes a method for operating a counter, in which an incremented or decremented counter reading is converted into data words by means of a coding rule.

The US 2004/0141580 A1 describes a digital counter which maximizes the count capacity of a given number of memory cells by evenly distributing the count load and ensuring that each individual state change in each memory cell represents a count pulse.

The US 2004/0113822 A1 describes a counter circuit in which a binary incremented or decremented count is converted to data words using a Gray code encoding rule.

The GB 2 180 083 A describes a method in which the permutation of the bit position in data words to optimize the uniform distribution of write operations in a memory module.

It An object of the present invention is an improved method to operate a meter as well as a corresponding counter specify.

These The object is achieved by a method according to claim 1 and a Counter circuitry according to claim 9 solved.

The underlying principle of the invention is based on the fact that the count is first binary coded in three steps explained below and stored in this converted binary form in the non-volatile memory. The starting point is initially a count that is defined by an ordinal number to an arbitrary base n. For example, it may be the base 10, then the count is defined as a decimal number. However, it may also be the base 16, so that the count is defined in a hexadecimal form. Since all computer units such as processors, logic modules, etc. and also working memory only binary, while the individual digits of the ordinal are each binary in the form of first data words, for example, with a length of 4 bits, stored in memory and are also in this form of machine a computer unit, for example a logic module or a programmable processor verarbei tet.

This first By the ordinal number to base n defined count is then in a coded first coding stage in a Gray code. this happens with a specific counter encoding rule. By definition, a Gray code is one Code where each increment or decrement occurs a number around the value "1" in each case only one the digits of the number changes. For this reason, a Gray code is often referred to as so-called "one-step Code ". In a Gray code, therefore, adjacent numbers differ only in a single digit. Usually such Gray codes as a coding method for robust transmission digital sizes over analog Signal paths used. This becomes advantageous in the method according to the invention used, so that in an increment / decrement only one Number of ordinal numbers to the base n of the code changes. The individual numbers of the gray-coded count are doing as binary second data words, which are also 4 bits long, for example, digitally processed within the arithmetic unit of the counter and in the working memory deposited.

By a following further conversion of the individual second data words, d. H. the single digit of the gray-coded meter reading, using a digit encoding rule then becomes the digits of the gray code coded counter states coded in an extended Gray code in third data words. at this step will be for that made sure that the individual digits in the third data words do so are deposited that when changing a digit around the value "1" again only one bit within the third data word concerned, which is the represents each digit changes. Through this double conversion, once the meter reading itself and then The individual digits, that is achieved in the whole Group of third data words, which ultimately the meter reading in coded form, in the increment / decrement the meter reading around the value "1" only a single one Bit changes. It is for the digit encoding rule used a so-called extended Gray code, for example a extended balanced or extended reflected gray code. An extended Gray code is to be understood that it is for different consecutive cycles representing the binary coded digit in total can go through (for example, at a hexadecimal digit the Cycle from 0 to 15), different cycle coding rules or partial Gray codes in turn, these cycle coding rules in turn cyclically reflect be used cyclically one after the other. Exact examples of this will be later still explained. By The extended Gray code can be used to ensure that a very cheap Distribution of changes the individual bits in the digits to the different bit locations he follows.

Then done in a third step using a certain permutation rule one possible even distribution all bits of these third data words, which are the extended gray-coded ones Digits of the gray-coded count specify on the memory words. This ensures that every increment / decrement as possible only exactly one memory word of the counter changes, and Although largely equally distributed over all memory words.

A complete incrementation or decrementation of the meter reading takes place according to the invention so that first the memory words of the meter reading are read from memory and then according to the inverted permutation rule the bits of the memory words are distributed to the third data words. These third data words are then using the inverse Digit encoding rule converted to the second data words, which the digits (base n) of the meter reading coded in Gray code in binary form represent. Finally done a complete conversion of the group of second data words, d. H. of the total meter reading in turn, using the inverse counter encoding rule to Group of first binary To generate data words that contain the numbers of the ordinal numbers Base n of the meter reading represent. This count is then incremented or decremented. Then done again a conversion of the entire group of first data words into the group of second data words using the counter encoding rule, then the conversion of the individual second data words respectively into the third data words using the mentioned digit encoding rule and finally again a rearrangement of the bits of the third data words using the permutation rule for generating the new memory words of incremented or decremented meter reading. As explained above, has become in such a process preferably only one of the memory words changed. It will then be the memory words generated with the memory deposited memory words compared and then only those Memory words or only that memory word newly stored or overwritten, which has been changed by incrementing or decrementing.

The specified method makes it possible to implement binary counters in technical systems in such a way that, with continued incrementing or decrementing, the number of necessary write operations to the individual memory words of the counter is distributed as equally as possible. This is limited in memory media whose life is limited by the number of write accesses to individual memory words It maximizes the number of possible counts and thus the life of the storage medium.

A inventive counter circuit arrangement has the same as the previous counter circuit arrangements next to a non-volatile memory, for example, an EEPROM or similar memory device, which serves the current meter reading each store in the form of a group of binary memory words, an arithmetic unit with a working memory. At the arithmetic unit it may be one or more logic devices, for example one or more FPGAs or ASICs, which act accordingly are programmed. Alternatively, it can also be one or more act with a corresponding program provided processors. The main memory is usually in the logic block or the arithmetic unit integrated. But this is not absolutely necessary. The working memory can also be formed in other ways and used by the computing unit be.

• a) eine Leseschnittstelle zum Auslesen der Speicherworte des Zählerstands aus dem Speicher und Ablegen in dem Arbeitsspeicher,
• b) ein erstes Permutationsmodul zur Umordnung von Bits der Speicherworte unter Verwendung einer inversen Permutationsregel zur Erzeugung einer Gruppe von dritten Datenworten, welche jeweils in einem erweiterten Gray-Code codierte Ziffern eines in einem Gray-Code codierten Zählerstand repräsentieren,
• c) ein erstes Ziffern-Konvertierungsmodul zum Konvertieren der einzelnen dritten Datenworte unter Verwendung einer inversen zweiten Kodierungsregel jeweils in zweite Da tenworte, welche jeweils die Ziffern des im Gray-Code codierten Zählerstands repräsentieren,
• d) ein erstes Zählerstand-Konvertierungsmodul zum Konvertieren der gesamten Gruppe von zweiten Datenworten unter Verwendung einer inversen ersten Kodierungsregel zur Erzeugung einer Gruppe von ersten Datenworten, welche jeweils die Ziffern des durch eine Ordinalzahl zu einer Basis n definierten Zählerstands repräsentieren,
• e) ein Inkrementierungs-/Dekrementierungsmodul zum Inkrementieren oder Dekrementieren des Zählerstands,
• f) ein zweites Zählerstand-Konvertierungsmodul zum Konvertieren der gesamten Gruppe von ersten Datenworten unter Verwendung der ersten Kodierungsregel in eine Gruppe von zweiten Datenworten, wobei der durch eine Ordinalzahl zu einer bestimmten Basis n definierte Zählerstand wieder in einem Gray-Code kodiert wird und die zweiten Datenworte jeweils die Ziffern des gray-kodierten Zählerstands repräsentieren,
• g) ein zweites Ziffern-Konvertierungsmodul zum Konvertieren der einzelnen zweiten Datenworte unter Verwendung der zweiten Kodierungsregel jeweils in dritte Datenworte, wobei jeweils die Ziffern des im Gray-Code codierten Zählerstands in einem erweiterten Gray-Code in den dritten Datenworten kodiert werden,
• h) ein zweites Permutationsmodul zur Umordnung von Bits der dritten Datenworte unter Verwendung der Permutationsregel zur Erzeugung der Speicherworte, so dass die Bits der dritten Datenworte jeweils möglichst gleichmäßig auf die Speicherworte verteilt sind,
• i) ein Vergleichermodul zum Vergleichen der so im Arbeitsspeicher erzeugten Speicherworte mit den im nichtflüchtigen Speicher hinterlegten Speicherworten und
• j) eine Speicherschnittstelle zum Speichern bzw. überschreiben vorzugsweise nur derjenigen Speicherworte im nichtflüchtigen Speicher, welche durch die Inkrementierung oder Dekrementierung geändert wurden.

The arithmetic unit here comprises, for example in the form of software modules or in the form of modules permanently programmed in the logic module, the following components:

• a) a read interface for reading the memory words of the counter reading from the memory and storing in the working memory,
• b) a first permutation module for reordering bits of the memory words using an inverse permutation rule to generate a group of third data words each representing digits coded in an extended Gray code of a count coded in a Gray code,
• c) a first digit conversion module for converting the individual third data words using an inverse second coding rule respectively into second data words, which respectively represent the digits of the count code encoded in the Gray code,
• d) a first counter reading conversion module for converting the entire set of second data words using an inverse first coding rule to generate a group of first data words, each representing the digits of the count defined by an ordinal number to a base n,
• e) an increment / decrement module for incrementing or decrementing the meter reading,
• f) a second meter reading conversion module for converting the entire group of first data words into a group of second data words using the first coding rule, wherein the count defined by an ordinal number at a certain base n is coded again in a Gray code and the second ones Data words in each case represent the digits of the gray-coded meter reading,
• g) a second digit conversion module for converting the individual second data words using the second coding rule into third data words in each case, wherein in each case the digits of the count coded in Gray code are encoded in an extended Gray code in the third data words,
• h) a second permutation module for rearranging bits of the third data words using the permutation rule for generating the memory words, so that the bits of the third data words are each distributed as evenly as possible to the memory words,
• i) a comparator module for comparing the memory words thus generated in the main memory with the memory words stored in the nonvolatile memory, and
• j) a memory interface for storing or overwriting preferably only those memory words in the nonvolatile memory which have been changed by the incrementing or decrementing.

there can the first and the second permutation module, the first and the second Digit conversion module and the first and second meter reading conversion module also each by a single permutation module, a single Digit conversion module or a single counter reading conversion module be realized which are each capable of rearranging the bits or conversion the data words using the appropriate permutation rule or Apply coding rule directly or in inverse form.

As already mentioned, a programmable logic module or processor is preferably used as the arithmetic unit, so that the individual modules can be realized in the form of software modules, which are then programmed into the respective module. Therefore, the invention also includes a corresponding computer program product, which is directly loadable into a memory of such a programmable arithmetic unit of counter circuitry, with program code means for carrying out all steps of said method when the program is executed on said arithmetic unit. In principle, however, it is also possible to implement such a computing unit in terms of hardware, for example within an IC or other module, or through a plurality of interconnected, cooperating ICs or other modules. This is ultimately a question of the concrete use of the meter, ie the technical environment in which the meter is to be used, as well as the effort and the cost th.

The dependent claims each contain particularly advantageous embodiments and developments of the invention, wherein in particular also the counter circuit arrangement according to the invention the dependent method claims can be trained.

Preferably the digit encoding rule is chosen so that the digits of the gray-coded meter reading in the third data words in an extended balanced Gray code are encoded. This can be a particularly good distribution of bit changes within the individual digits.

Particularly preferably, the ordinal number counter reading and thus also the gray-coded counter reading are respectively defined by an ordinal number to a base n, which is a power of 2, ie the digits are respectively defined to a base 2 ^m = n. For example, n = 16 can be chosen so that the digits are defined in the form of hexadecimal numbers. As described in an article by G. Bhat and CD Savage "Balance Gray Codes" in The Electronic Journal of Combinatorics, Vol. 3, No. 1, 1996, it is possible to use a 2 ^n- bit Code in which the number of bit changes is totally balanced. Although there are generally no simple mapping rules between the ordinal numbers and the corresponding balanced Gray code for such totally balanced Gray codes. Therefore, for example, it is not easy to convert the count directly into such a totally balanced Gray code, since otherwise every conversion direction using very large tables must be converted and even in a simple conventional 32-bit counter these tables would go beyond the scope of most technical systems. However, since only the individual digits of the already gray-coded counter reading are coded here in the extended balanced Gray code (and, for example, customary hexadecimal digits in a simple 4-bit data word can be coded in each case), a very simple, small table is sufficient for converting the Digits to base n = 2 ^m in a totally balanced Gray code. Therefore, preferably the number coding rules and thus also the inverse number coding rules are stored in a table, for example a usual look-up table, in a memory of the computer device or a memory to which the computer unit has access.

Basically but it is also possible the counter reading or the gray-coded counter reading Digits to define a base that is not a power of 2 is, for example, as decimal numbers. Then the advanced one Gray code in which the individual digits are encoded, not Completely balanced, however, is the distribution of bit changes to the individual bit positions in the data already significantly better as with the previously known counters, so that ultimately a lifespan increase of the counter over conventional meters can be achieved.

As mentioned above, an extended Gray code is a code that uses the digit encoding rule for one Number of consecutive cycles, one to be coded Number goes through, each comprises different cycle coding rules, one after the other cyclically or reflected cyclically. It is preferred ensured, that the number of cycle encoding rules is the number or one Multiples of the number of bits of a single one of the third data words, d. H. the to the binary Storage of the third data word necessary bits, corresponds. To the extended Gray code as possible To keep it straightforward, it is preferred that the number the cycle encoding rules correspond exactly to the number of bits, d. H. For example, in a 4-bit binary encoding, it becomes a hexadecimal digit an extended Gray code with exactly four different cycle encoding rules used. Which of the cycle encoding rules is used depends on in which counting cycle the counter regarding this Numeral is straight and in which direction the cycle is straight is going through. A concrete example for this is still in the Description of the figures explained.

Basically, almost Any length of data words are used. But, as already described, a representation the individual digits of the meter reading by ordinal pay to base 16, d. H. in the form of hexadecimal digits especially good, is the length the first data words, the length the second data words and the length the third data words each 4 bits. Through a 4-bit data word let yourself optimally represent a hexadecimal digit.

Around with such 4-bit data words a count of a usual 32-bit counter, as it is used in most cases today to encode are each eight data words in a group, d. H. eight first data words, eight second data words and eight third data words required.

There Most of the memories are constructed in such a way that they are each byte-wise can be described is the length the memory words are preferably each 1 byte (i.e., 8 bits), so that four memory words are required to encode a 32-bit counter are.

Basically the invention but also on counters with other memory lengths or data word lengths and memory word lengths be used. For example, could be a 20-bit counter count be stored in four memory words with 5 bits each. These could then for processing and incrementing according to the inventive method in each groups of five converted first, second and third data words of 4 bits in length become.

Basically also the counter encoding rule be defined in the form of a look-up table, on the basis of which the entire meter reading in a gray-coded counter reading can be implemented. It can then be used any Gray code.

at a preferred embodiment the counter encoding rule like this selected that the count defined by an ordinal number to the base n is encoded in a cyclically-reflected Gray code. The application Such a cyclically-reflected Gray code may have the advantage have it easier to calculate than other Gray codes. at an easily calculable, cyclically-reflected Gray code for example, the preferred way that the counter coding rule and the inverse counter encoding rule are each predetermined by a calculation algorithm and for Conversion of the group of first data words into the group of second data words and vice versa each calculation using help the corresponding calculation algorithm is performed. This means, It is then not necessary to convert to a relative size Look-Up-Table, which would take more time than that Calculation with a simple numerical coding rule or inverse coding rule. It could then very long counters be implemented in simple technical systems.

The The invention will be described below with reference to the attached figures based on embodiments once again closer explained. Show it:

1 3 a schematic representation of a possible method sequence for coding a meter reading into the memory words to be stored in the non-volatile memory according to an exemplary embodiment of the method according to the invention,

2 a simple embodiment for a reflected cyclic Gray code of a three-digit number to the base B = (2, 3, 4),

3 an embodiment for an extended Gray balanced code for an ordinal number based on n = 16,

4 a block diagram of essential components and their interaction of an embodiment of a counter circuit arrangement according to the invention,

5a and 5b a concrete embodiment of a possible method sequence according to the invention when incrementing a 32-bit counter,

5c a representation of the steps Z ⁽⁴⁾ to Z ^{(7) of} the procedure according to 5b at a further increment of the meter reading.

At the in 1 illustrated embodiment of a possible method according to the invention is the coding of a 20-bit counter reading, which is stored in four memory words SW in the non-volatile memory module, each having a length of 5 bits. Accordingly, the counter is described as an ordinal number or in coded form by five digits, which are each stored in the form of individual data words DW ₁ , DW ₂ , DW ₃ with 4-bit length in the working memory. There is a group of five first data words DW ₁ , which represent the digits of the total counter as ordinal, a group of five second data words DW ₂ , which respectively represent the digits of the reflected gray coded counts as ordinal numbers, and a group of five third data words DW ₃ , in which the individual numbers are encoded again in an extended Gray code.

For incrementing or decrementing, the in 1 in each case from top to bottom through the permutation or coding steps shown.

Ie. First, the encoded counter reading, which is stored in the memory words SW, is read in, and the individual bits of this counter reading are distributed to the third data words DW _{3 in} accordance with a specific permutation rule. These individual third data words DW ₃ then each contain the individual digits of the gray-coded counter reading in an extended Gray code. This is followed by an inverse number coding, so that the individual digits are converted back into their ordinals, which are stored in the form of the individual second data words DW ₂ in the main memory. The digits stored in the individual second data words are then the digits of the gray-coded meter reading. In a further step, the entire counter value is then recoded, in order to deposit it in the form of first data words DW ₁ in the main memory. This counter reading becomes ordinal then incremented or decremented. Subsequently, a counter coding for generating the changed second data words DW ₂ , a coding of the individual digits for generating the modified third data words DW ₃ and finally the permutation of the bits for distribution of the individual bits of the third data words DW ₃ to the memory words SW. These new memory words are then compared with the originally stored counter reading, and the memory words which have changed are overwritten.

By the coding according to the invention is there for it ensured that at each incrementation step or decrementing step exactly only one of the memory words changes and that when counting up the counter or counting down of the meter The changes are distributed equally to all memory words.

A particularly preferred procedure and coding will be explained in the following, in which case the way from the coding of the counter reading as the original ordinal number in the counter reading ultimately coded in the memory words will be described:
If a counter is incremented continuously, this results in a sequence in which the byte containing the least significant digit changes most frequently, the byte with the next highest digit the second most, and the byte with the most significant digit the least. In general, the number of changes per digit decreases logarithmically from the base of the numerical representation. Furthermore, it inevitably happens that sometimes more than one digit can change at once. For example, during the jump from the number 19999 to the number 20000 all digits change. Thus, all bytes of the meter would change.

This latter effect can be avoided by storing the count in the form of a Gray code. A Gray code ensures that consecutive counter readings are only one character each. At the in 1 illustrated embodiment, a reflected cyclic Gray code is applied. One possible reflected cyclic Gray code is in 2 shown. Each number is given its own base. That is, the base may B = b each point are given ₍₀ b _n-1, b _n-2, b _j, ..., b) to the base here as a vector. In 2 is this base B = (2, 3, 4), ie the digits of the last column of the ordinal number and the Gray code run from 0 to 3, the digits of the middle column from 0 to 2 and those of the first column from 0 to 1. The Gray code shown on the right is a so-called reflected Gray code, because it is created by mirroring sequences of numbers so that the numbers in each column are counted up and down. For example, in the last column, the numbers go through the sequence 0, 1, 2, 3, 3, 2, 1, 0, 0, 1, 2, 3, 3 ... etc. The Gray code is also called "cyclic". because after the last number can be counted again with the first number of the Gray code and nevertheless only a single bit changes, such a cyclic Gray code can be generated whenever the base b _{n-1 of} the highest-order digit is even-numbered is.

One cyclic Gray reflected code to any given Base B can be defined by a design rule given from a given ordinal number of the base B the representation as Gray code of the base B is clearly generated and by accordingly indicating an inverse design specification becomes, from a given Gray code, the corresponding ordinal number clearly generated.

As a counter coding rule for converting a number Z into a corresponding Gray code G, the following design rule can preferably be used: For all numbers g i with i = 0, 1, 2, ..., n - 2, if the number z i + 1 + z i + 2 + ... + z m straight is: g i = z i otherwise: g i = (b i - 1) - z i (1) and for i = n-1, g _n-1 = z _n-1

there m is defined as the position of the first digit of Z with even number Basis, if Z consists of numbers of different bases, and m: = n - 1, if Z is complete consists of digits of odd base.

Conversely, as an inverse counter coding rule, the following design rule can be given, which converts the number in gray code G back into the corresponding ordinal number Z: For all numbers z i with i = 0, 1, 2, ..., n - 2, if the number g i + 1 + g i + 2 + ... + g n-1 straight is: z i = g i otherwise: z i = (b i - 1) - g i (2) and for i = n-1: z _n-1 = g _n-1

The design rule (1) applies to digits of any basis or numbers with any basis vector. Also the in 2 Gray code given as example for base B = (2, 3, 4) was generated using this design rule. In practice, ordinal numbers are used in most technical applications whose numbers are defined exclusively on an even-numbered basis. In this case, the design rule (1) reduces to the simplified form. For all numbers g i with i = 0, 1, 2, ..., n - 2, if the number z i + 1 straight is: g i = z i otherwise: g i = (b i - 1) - z i (1a) and for i = n-1, g _n-1 = z _n-1

If only numbers are used whose numbers are defined on an odd-numbered basis, the following design rule applies: For all numbers g i with i = 0, 1, 2, ..., n - 2, if the number z i + 1 + z i + 2 + ... + z n-1 straight is: g i = z i otherwise: g i = (b i - 1) - z i (1b) and for i = n-1, g _n-1 = z _n-1

at a particularly preferred embodiment For example, to realize a 32-bit counter, the count may be in an eight-digit hexadecimal Ordinal number represents be, d. H. the individual numbers are each hexadecimal numbers, each of which can be coded in a 4-bit long data word.

Such a 32-bit counter is thus realized with four 8-bit memory words each having eight 4-bit first data words DW ₁ , second data words DW ₂ and third data words DW ₃ .

By this counter coding of the hexadecimal ordinal number of the counter reading in the hexadecimal gray cyclic gray code during conversion of the group of first data words DW ₁ into the group of second data words DW ₂ , it is already ensured that two consecutive counter readings differ by only one digit. However, the least significant digit still changes most frequently and the number of changes in the other digits decreases logarithmically to the base.

In principle, it would now be possible to distribute the digits within the permutation step to the different memory words in such a way that the changes of the least significant digit are distributed among the individual memory words. However, since the digits themselves are stored as a binary number, many bits of the digit representation are often changed on incrementing. For this reason, according to the invention, the digits of the already gray-coded meter reading are coded once again with a Gray code. This takes place during the conversion with the aid of the digit coding rule of the individual second data words DW ₂ into the respectively associated third data words DW ₃ . For this purpose, an extended balanced Gray code is used, which is stored in a look-up table. A balanced Gray code is defined as equaling the number of bit changes when passing through a complete cycle of multiple sequences, for example, at a hexadecimal number of 0 ... 15 and 15 ... 0. Since in the present embodiment individual hexadecimal digits of the count are already coded in a cyclically reflected Gray code, they are always counted from 0 to 15 and back to 0 again.

An expanded Gray balanced code used in the practice of the invention is disclosed in U.S. Patent Nos. 4,135,774; 2 shown. The leftmost column contains the ordinal number to the base 10. In the adjacent second column, the ordinal number to the base 16, ie in the usual definition as a hexadecimal number from 0 to e, indicated. To the right of this is the expanded, balanced Gray code for base 2, that is, a 4-bit binary code in four columns, each corresponding to four different cycle encoding rules. In an up and down counting the ordinal number of this gray code is in each case along the displayed th arrow directions column-wise meandering from the first column in the top row to the last column in the top row. Subsequently, in this extended Gray code, backwards in a meandering manner along the direction of the arrow.

The Use of such different cycle encoding rules for four consecutive cycles Cycles ensures that in a four-time through the entire cycle (four times from 0 to 15 and back again) change all bits the same number of times. For a single Column of the Gray code, d. H. For a single cycle coding rule, this is not the case. This is easy at the first (left) Gray code column. When going through this Gray code changes from 0 to 15 the left least significant bit as well as the two bits in the Center exactly four times, whereas the most significant left bit changes only three times. Therefore a total of four episodes of this Gray code are reflected in each other (which here meandering through the Columns of the Gray code corresponds) and thereby the columns in the respective cycles are so permuted (permuted) that the column with the fewest bit changes occurring once at each bit position. there are individual bit columns (each marked by an underscore) inverted so that after the first counting from 0 to 15 and the subsequent counting down of 15 to 0 the bit representation for the 15 in both episodes matches and the next incrementing from 0 to 15 the bit representation matches 0 and the last one countdown from 15 to 0 again the bit representation of the 15.

This ensures that for a complete counting cycle 0-15-0-15-0, like when incrementing the gray-coded meter reading into the each digit occurs, the number of bit changes for each bit of the bit positions 1 to 4 is the same.

As 3 For such a 4-bit representation of the hexadecimal digits, only a very small look-up table is required so that the digit conversion step can be carried out very quickly, effectively and without great computation. It only needs to be determined when counting the Gray code counter which cycle of counting up or down each digit is currently in, and then the gray code of the particular cycle defined in the lookup table (ie appropriate cycle coding rule). This position in the series can be calculated for each digit from the immediately adjacent next higher-order digit of the cyclic Gray code of the meter reading.

In the case of the Gray code shown here, for converting a hexadecimal digit into a 4-bit Gray code according to 3 can this determination by the higher-order digit very easily realized by the higher-order digit is encoded into a binary 2-bit long, cyclically reflected Gray code, the sequence 0, 1, 2, 3, 3, 2, 1, 0, 0, 1 ... etc. goes through. This Gray code of the higher-order digit determined in this way then automatically indicates which cycle coding rule, ie which of the cycle codes in 3 adjacent columns must be used for the conversion of the lower order digit. In this case, the coding of the higher-order digit in the binary, cyclically reflected 2-bit Gray code ensures that the direction is also taken into account, which is just along the in 3 shown arrows meandering through the columns.

Only for the most significant digit of the counter, this position can not be determined in the cycle, since there is no higher-order digit. Therefore, for the most significant digit, a predetermined cycle can always be adopted, for example, without loss of generality, the first cycle conversion rule. However, since the Gray code of the individual digits is already balanced, the number of bit changes of the most significant bit, the most significant digit of the counter and thus the change of the associated memory word in a distribution of the individual bits of the digits to the various memory words only 1 less than the remaining bits or memory words. However, this is already the most balanced number of bit changes ever, since z. For example, in a number of 2 ³² possible states of a 32-bit counter, exactly 2 ³² - 1 state changes may occur, just as when incrementing a decimal counter from 1 to 10, exactly nine state changes occur.

Will then, as in 1 as shown, the individual bits of the extended gray-coded digits of the gray-coded counter in the third data words DW ₃ are distributed to the memory words SW such that each of the memory words SW contains exactly 1 bit of each of the third data words DW ₃ , as a whole provided that the changes of the individual memory words SW are completely compensated for a complete cycle when the counter is incremented, and thus the maximum service life can be achieved, as far as it is determined by the number of write operations.

Instead of a balanced extended Gray code, however, any other extended Gray code can also be used to represent the individual digits. For example, for the numerical representation no extended balanced, but z. For example, if an extended single-reflection Gray code is used, the number of bit changes of each digit is generally also balanced. Only when changing the most significant digit will the number of bit changes be different and decrease logarithmically to the chosen base. For digits that are represented by 4 bits as here in the preferred embodiment, this case occurs only at the first change of the most significant digit, so after 2 ²⁸ change state. Even after all 2 ³² - 1 state changes, the byte containing the least significant bit of the most significant digit will only have undergone 16 more changes than the byte (memory word) containing the most significant bit of the most significant digit. In the case of numbers of this magnitude, this no longer plays a role in the practical implementation, so that actually another extended Gray code can also be used in real use.

4 schematically shows a counter circuit arrangement 1 ("Counter") with which the method according to the invention can be implemented 1 is a non-volatile memory 2 , here an EEPROM, in each of which the count is written in the form of memory words, for example, 1 byte in length. Another essential component of this meter 1 is an arithmetic unit 5 , here a logic module in the form of an FPGA, in which the modules explained below, for example in the form of program sections, are programmed. This logic module 5 contains, inter alia, a working memory 6 , in which the current counter reading can be stored in the form of binary data words and to which all modules have access. Receives this computer unit 5 an incrementation or decrement command IB, so first are the memory words SW from a read interface 7 read out and in memory 6 stored. In a permutation module 10a then takes place in 1 in the first stage Asked permutation of the bits, ie a distribution of the bits of the memory words SW to the individual third data words DW _3rd Next will be a digit conversion module 11a the individual digits are decoded with an inverse number coding rule to the individual digits of the count in the second data words DW ₂ as ordinals in the working memory 6 store. Subsequently, by a counter conversion module 12a with an inverse counter coding rule, the entire counter reading is converted and in the first data words DW ₁ in the main memory 6 filed, each containing the digits of the counter in uncoded form as ordinals. From an increment / decrement module 13 Then, the count is incremented or decremented depending on the increment / decrement command IB. Subsequently, turn from the counter conversion module 12b the counter reading is coded in the reflected Gray codes and the changed second data words DW _{2 are} generated from the first data words DW ₁ . After that are from the digit conversion module 11b the individual digits, ie the individual data words DW ₂ , encoded in the extended balanced Gray code and thus generates the data words DW ₃ .

The individual bits of these data words DW ₃ are then from a permutation module 10b again evenly distributed to the individual memory words SW.

As already explained above, the digit conversion and the inverse digit conversion with the aid of a look-up table LUT, z. B. as in 3 is shown. This can be stored in a non-volatile memory 4 be deposited on the the digit conversion module 11a . 11b Has access. For counter conversion or inverse counter conversion, on the other hand, a specific calculation algorithm BA or inverse calculation algorithms BA 'are predefined, for example the calculation algorithms (1) or (1a) and (2) defined above. These can also be stored in non-volatile memory 3 be deposited. For non-volatile memories 3 . 4 it can also be a shared memory or can also both or one of both stores 3 . 4 with the memory 2 combined for non-volatile storage of the meter reading.

The permutation modules 10a . 10b as well as the digit conversion modules 11a . 11b and the counter conversion modules 12a . 12b can each be completely different modules, but they can also be implemented together in a permutation module or digit conversion module or counter conversion module, as indicated here.

The in-memory 6 after the increment in the form of new memory words SW 'stored count is then to a comparator module 9 pass which the new memory words SW 'with the old memory words SW, the this comparator module 9 for example, from the read interface 7 has received or in addition to the changed memory words SW 'in memory 6 are compared to check which memory word has changed during incrementing. It will then only this changed memory word SW '' from the memory interface 8th in non-volatile memory 2 overwritten.

A complete counting process on a 32-bit counter with four memory words A, B, C, D (hereinafter also referred to as memory bytes) is referred to below 5a and 5b explained. Here are the individual digits of the memory both in the ordinal number and in the Gray code of 4 bits.

The coding of each digit is carried out according to the above, based on 3 illustrated extended balanced Gray code. The ordinals of the counter itself are coded according to the reflected Gray code to the base B = 2 ⁿ with n = 16, ie the digits are hexadecimal numbers.

In step Z ⁽⁰⁾ , the counter reading is initially stored in the four memory words D, C, B, A, each of 1 byte length. The letters a ₀ to a ₇ , b ₀ to b ₇ , c ₀ to c ₇ and d ₀ to d ₇ indicate in each case the bit position in the individual memory words A, B, C, D. Immediately below is a binary value as an example.

In the next step Z ⁽¹⁾ , the individual digits in the balanced Gray code are then shown after re-sorting the individual bit positions to the eight third data words DW ₃ , which each have a length of 4 bits. As can be seen here, the least significant digit contains the bits a ₀ , b ₀ , c ₀ , d ₀ , the next higher digit the bits a ₁ , b ₁ , c ₁ , d ₁ , etc.

In the following step Z ⁽²⁾ then the individual digits are represented as binary coded ordinal numbers (in the form of the second data words DW ₂ ), as they can be generated after the conversion from the balanced Gray code using the inverse digit encoding rule. In addition, here the individual digits on the left side over the bit representations of the second data words DW _{2 of} this gray-coded counter reading are given as hexadecimal ordinal numbers.

In step Z ⁽³⁾ , the count after the inverse counter conversion is then specified in the form of the first data words DW ₁ . This is the non-gray coded original counter stood as ordinal number. Again, the meter reading is additionally given in the form of eight hexadecimal digits.

In the next step Z ⁽⁴⁾ , the counter reading is then incremented by the value 1. The digits affected by this incrementing are marked in the hexadecimal form as well as in the binary representation by a circulating box. As can be seen here, the third lowest digit has been changed from the hexadecimal value 5 to the value 6, so that automatically the two lower order digits previously represented by an "f" have also been changed to the value "0". Accordingly, the three rightmost binary coded first data words DW ₁ representing these numbers have also been changed.

In step Z ⁽⁵⁾ , these first data words DW _{1 are} then again using the cyclic Gray code, as above using the calculation rule ( 1 ) is converted. Like from the 5a and 5b can be seen, is due to the Gray coding of the count by incrementing only one digit, namely the third lowest digit affected. That is, only in the second data word DW ₂ , which relates to the third least significant digit, there is a change from the corresponding data word DW ₂ before the incrementation (see step Z ⁽²⁾ ). However, in this figure a total of 2 bits are affected by the change.

In the next step Z ⁽⁶⁾ , the individual digits are now brought into an extended, balanced Gray code in accordance with the rule also indicated above, ie the second data words DW ₂ are respectively converted back into the third data words DW ₃ . A comparison of the third lowest, modified by the incrementing third data word DW ₃ with the corresponding third data word DW ₃ in step Z ⁽¹⁾ shows that now only a single bit has changed due to the incrementation.

Subsequently, again in step Z ^(7), the individual bits of the third data words DW _{3 are distributed} to the memory words D, C, B, A. Since only one bit of a third data word DW ₃ has changed as a result of the incrementation, the result changes accordingly the incrementation of only one of the counter reading memory words SW, here the memory word C. This must then be overwritten in the non-volatile memory.

5c shows the steps Z ⁽⁴⁾ to Z ⁽⁷⁾ in a subsequent further incrementation. Here, the incremented count changes as ordinal only in the least significant digit, which is again set from 0 to 1 (see hexadecimal representation), ie it changes accordingly only the rightmost data word DW ₁ , which represents the least significant digit.

at the recoding There are no changes in the reflected Gray code here. Similarly, when coding this digit in the advanced balanced Gray code ensures that again only a single bit the entire digits changes. Correspondingly changes at the incremented counter reading memory words again only a single memory word SW, namely in this case the memory word A.

As shown here, the method of the present invention can realize a 32-bit counter that is balanced not at the bit level but even at the byte level. So it is ultimately a four-digit, totally balanced Gray code to base 2 ⁸ = 256 provided. The three-stage process ensures that the respective conversions can be carried out relatively easily. Thus, both the gray coding of the counter content in the first stage with the above-described calculation rules and the conversion of the individual digits into an extended balanced Gray code with the help of a very small table can be made simple and fast. A further advantage may be that the difference in the number of write accesses to the individual memory words within an incomplete subcycle is determined by the number of digit bits, ie the bits which are necessary to describe a single digit. By an appropriate choice of this parameter, as here for example by the use of 4-bit digits, this difference can be kept small accordingly. Due to the quick and easy conversion even long counters can be converted into the corresponding Gray code or into the corresponding ordinal number.

It will be final once again noted that it is the previous one described in detail process flow as well as in the illustrated counter only to exemplary embodiments which is modified by the expert in ver different ways can be without departing from the scope of the invention. So can the invention especially for different word lengths the data words or the memory words of a memory module used become.

Claims (10)

Method for operating a counter, in which a current counter reading is stored in the form of a group of binary memory words in a memory, wherein the following method steps are carried out for incrementing or decrementing the counter reading: a) reading the memory words (SW) of the counter reading from the memory ( 2 b) rearranging bits of the memory words (SW) using an inverse permutation rule to generate a set of third data words (DW ₃ ) each representing digits encoded in an extended Gray code of a count coded in a Gray code, c ) Converting the individual third data words (DW ₃ ) using an inverse numerical coding rule into second data words (DW ₂ ), which respectively represent the digits of the count coded in Gray code, d) converting the group of second data words (DW ₂ ) using an inverse counter encoding rule to generate a set of first data words (DW ₁ ) each representing the digits of the count (ZS) defined by an ordinal number to a base n, e) incrementing or decrementing the count, f) converting the group of first data words (DW ₁₎ in a group of second data words (DW ₂₎ using the Z hler encoding rule, wherein the encoded by an ordinal number to a base n defined count back into a Gray code and the second data words (DW ₂₎ respectively represent the digits of the Gray coded count, g) converting the single second data words (DW ₂ ) in each case in third data words (DW ₃ ) using the digit coding rule, wherein in each case the digits of the gray code encoded count are encoded in an extended Gray code in the third data words (DW ₃ ), h) rearrangement of bits the third data words (DW ₃ ) using the permutation rule for generating memory words (SW '), so that the bits of the third data words (DW ₃ ) in each case to the memory words (SW') are distributed, i) comparing the memory words thus generated ( SW ') with those in the memory ( 2 ) stored memory words (SW) and j) storing those memory words (SW ''), which were changed by the incrementing or decrementing. A method according to claim 1, characterized in that the digit encoding rule is selected so that the digits of the encoded in Gray code count in the third data words (DW ₃ ) are encoded in an extended balanced Gray code. Method according to claim 1 or 2, characterized that the meter reading is defined by an ordinal number to a base n, which is a Power of 2 is. Method according to one of claims 1 to 3, characterized that the numeric coding rule is stored in a table (LUT) is. Method according to one of claims 1 to 4, characterized that the digit encoding rule for a number of consecutive cycles, which passes through a number to be coded, each different Cycle coding rules wherein the number of cycle encoding rules is the number or one Multiples the number of bits of a single one of the third data words equivalent. Method according to one of claims 1 to 5, characterized in that the length of the first data words (DW ₁ ), the length of the second data words (DW ₂ ) and the length of the third data words (DW ₃ ) is four bits each. Method according to one of claims 1 to 6, characterized that the counter coding rule so chosen becomes that defined by an ordinal number to a base n meter reading is encoded in a cyclic gray-reflected code. Method according to one of Claims 1 to 7, characterized in that the counter coding rule and the inverse counter coding rule are respectively predetermined by a calculation algorithm (BA, BA ') and for converting the group of first data words (DW ₁ ) into the group of second data words (DW ₂ ) and vice versa each calculation is carried out with the aid of the corresponding calculation algorithm. Counter circuit arrangement ( 1 ), with a non-volatile memory ( 2 ), in order to store a current counter reading in the form of a group of binary memory words, and a computing unit ( 5 ) with a working memory ( 6 ), which arithmetic unit ( 5 ) comprises the following components: a) a read interface ( 7 ) for reading the memory words (SW) of the counter reading from the memory ( 2 ) and storing in the main memory ( 6 ), b) a first permutation module ( 10a ) for rearranging bits of the memory words (SW) using an inverse permutation rule to generate a set of third data words (DW ₃ ) each representing digits coded in an extended Gray code of a count coded in a Gray code, c) first digit conversion module ( 11a ) for converting the individual third data words (DW ₃ ) using an inverse numerical coding rule into second data words (DW ₂ ), which respectively represent the digits of the count coded in the Gray code, d) a first meter reading conversion module ( 12a ) for converting the entire set of second data words (DW ₂ ) using an inverse counter encoding rule to create a group of first data words (DW ₁ ), which respectively represent the digits of the count defined by an ordinal number to a base n, e) an increment / decrement module ( 13 ) for incrementing or decrementing the meter reading, f) a second meter reading conversion module ( 12b ) for converting the entire group of first data words (DW ₁ ) into a group of second data words (DW ₂ ) using the numerator coding rule, wherein the count defined by an ordinal number to a base n is coded again in a Gray code, and the second data words (DW ₂ ) each represent the digits of the gray-coded counter reading, g) a second digit conversion module ( 11b ) for converting the individual second data words (DW ₂ ) using the digit coding rule in each case in third data words (DW ₃ ), wherein in each case the digits of the gray code encoded count in an extended Gray code in the third data words (DW ₃ ), h) a second permutation module ( 10b ) for rearranging bits of the third data words (DW ₃ ) using the permutation rule for generating memory words (SW), so that the bits of the third data words (DW ₃ ) are respectively distributed to the memory words (SW '), i) a comparator module ( 9 ) for comparing the so in the main memory ( 6 ) generated memory words (SW ') with those in the non-volatile memory ( 2 ) stored memory words (SW) and j) a memory interface ( 8th ) for storing those memory words (SW '') in the nonvolatile memory ( 2 ), which have been changed by incrementing or decrementing. Computer program product, which directly into a memory of a programmable computing unit ( 5 ) a counter circuit arrangement ( 1 ) is loadable with program code means to perform all the steps of a method according to one of claims 1 to 8, when the program on the arithmetic unit ( 5 ) is performed.